View source for Central processing unit

{{Short description|Central computer component that executes instructions}}
{{Redirect|CPU}}

[[File:Intel_i9-14900KF_CPU.jpg|thumb|A high-end consumer CPU made by [[Intel]]: an [[Intel Core i9-14900KF]]]]

[[File:Intel Xeon 3060 Conroe (Reshoot) - Flickr - cole8888.jpg|thumb|280px|upright=1.5|Inside a central processing unit: The [[integrated circuit]] of Intel's [[List of Intel Xeon processors (Core-based)#ark27205|Xeon 3060]], first manufactured in 2006]]

A '''central processing unit''' ('''CPU'''), also called a '''central processor''', '''main processor''', or just '''processor''', is the primary [[Processor (computing)|processor]] in a given [[computer]].<ref>{{Cite book |last=Team |first=YCT Expert |url=https://books.google.com/books?id=O_fZEAAAQBAJ&dq=A+central+processing+unit+(CPU)%E2%80%94also+called+a+central+processor+or+main+processor%E2%80%94is+the+most+important+processor+in+a+given+computer.&pg=PA425 |title=Engineering Drawing & Basic Science |publisher=Youth Competition Times |pages=425 |language=en}}</ref><ref>{{Cite book |last=Nagpal |first=D. P. |url=https://books.google.com/books?id=LAsbEAAAQBAJ&dq=A+central+processing+unit+(CPU)%E2%80%94also+called+a+central+processor+or+main+processor%E2%80%94is+the+most+important+processor+in+a+given+computer.&pg=PA33 |title=Computer Fundamentals |date=2008 |publisher=S. Chand Publishing |isbn=978-81-219-2388-0 |pages=33 |language=en}}</ref> Its [[electronic circuit]]ry executes [[Instruction (computing)|instructions]] of a [[computer program]], such as [[arithmetic]], logic, controlling, and [[input/output]] (I/O) operations.<ref>{{Cite web |title=What is processor (CPU)? A definition from WhatIs.com |date=14 August 2019|publisher=Informa TechTarget|url=https://www.techtarget.com/whatis/definition/processor |access-date=2024-03-15 |website=WhatIs |language=en}}</ref><ref>{{Cite book |last=Chesalov |first=Alexander |url=https://books.google.com/books?id=VlG5EAAAQBAJ&dq=cpu+electronic+circuitry+executes+instructions+of+a+computer+program,+such+as+arithmetic,+logic,+controlling,+and+input/output+(I/O)+operations&pg=PT54 |title=The fourth industrial revolution glossarium: over 1500 of the hottest terms you will use to create the future |date=2023-04-12 |publisher=Litres |isbn=978-5-04-541163-9 |language=en}}</ref><ref>{{Cite book |last=Jagare |first=Ulrika |url=https://books.google.com/books?id=ZwxsEAAAQBAJ&dq=cpu+electronic+circuitry+executes+instructions+of+a+computer+program,+such+as+arithmetic,+logic,+controlling,+and+input/output+(I/O)+operations&pg=PT91 |title=Operating AI: Bridging the Gap Between Technology and Business |date=2022-04-19 |publisher=John Wiley & Sons |isbn=978-1-119-83321-5 |language=en}}</ref> This role contrasts with that of external components, such as [[main memory]] and I/O circuitry,<ref name="kuck">{{cite book|last1= Kuck|first1= David|title= Computers and Computations, Vol 1|date= 1978|publisher= John Wiley & Sons, Inc.|isbn= 978-0471027164|page= 12}}</ref> and specialized [[coprocessor]]s such as [[graphics processing unit]]s (GPUs).

The form, [[CPU design|design]], and implementation of CPUs have changed over time, but their fundamental operation remains almost unchanged.<ref>{{Cite book |last=Prabhat |first=Team |url=https://books.google.com/books?id=sbqcEAAAQBAJ&dq=design,+and+implementation+of+CPUs+have+changed+over+time,+but+their+fundamental+operation+remains+almost+unchanged.&pg=PA95 |title=Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English: Bestseller Book by Team Prabhat: Ultimate Guide to SSC CGL Combined Graduate Level Tier-I & Tier II Prelims & Mains (with Latest Solved Question Papers) Guide Book English |date=2023-04-13 |publisher=Prabhat Prakashan |isbn=978-93-5488-527-3 |pages=95 |language=en}}</ref> Principal components of a CPU include the [[Arithmetic logic unit|arithmetic–logic unit]] (ALU) that performs [[arithmetic operation|arithmetic]] and [[Bitwise operation|logic operations]], [[processor register]]s that supply [[operand]]s to the ALU and store the results of ALU operations, and a [[control unit]] that orchestrates the [[#Fetch|fetching (from memory)]], [[#Decode|decoding]] and [[#Execute|execution (of instructions)]] by directing the coordinated operations of the ALU, registers, and other components. Modern CPUs devote a lot of semiconductor area to [[Cache (computing)|caches]] and [[instruction-level parallelism]] to increase performance and to [[CPU modes]] to support [[operating system]]s and [[virtualization]].

Most modern CPUs are implemented on [[integrated circuit]] [[microprocessor]]s, with one or more CPUs on a single IC chip. Microprocessor chips with multiple CPUs are called [[multi-core processor|''multi-core processors'']] (''MCP'').<ref>{{Cite web |title=What is a multicore processor and how does it work? |url=https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |access-date=2024-03-15 |website=Data Center |language=en}}</ref> The individual physical CPUs, called ''processor cores'', can also be [[Multithreading (computer architecture)|multithreaded]] to support CPU-level multithreading.<ref name="intel-pcm" />

An IC that contains a CPU may also contain [[Computer memory|memory]], [[peripheral]] interfaces, and other components of a computer;<ref>{{Cite book |last=Herres |first=David |url=https://books.google.com/books?id=RYoBEAAAQBAJ&dq=An+IC+that+contains+a+CPU+may+also+contain+memory&pg=PA130 |title=Oscilloscopes: A Manual for Students, Engineers, and Scientists |date=2020-10-06 |publisher=Springer Nature |isbn=978-3-030-53885-9 |pages=130 |language=en}}</ref> such integrated devices are variously called [[microcontroller]]s or [[System on a chip|systems on a chip]] (SoC).

==History==
{{Main|History of general-purpose CPUs}}
[[File:Edvac.jpg|thumb|[[EDVAC]], one of the first stored-program computers]]

Early computers such as the [[ENIAC]] had to be physically rewired to perform different tasks, which caused these machines to be called "fixed-program computers".<ref>{{cite book|last1=Regan|first1=Gerard|title=A Brief History of Computing|isbn=978-1848000834|page=66|url=https://books.google.com/books?isbn=1848000839|access-date=26 November 2014|year=2008|publisher=Springer }}</ref> The "central processing unit" term has been in use since as early as 1955.<ref name= weik1955>{{cite web| last = Weik | first = Martin H. | title = A Survey of Domestic Electronic Digital Computing Systems | publisher = [[Ballistic Research Laboratory]] | url = http://ed-thelen.org/comp-hist/BRL-i.html#IBM-CPC | year = 1955 | access-date = 2020-11-15 | archive-date = 2021-01-26 | archive-url = https://web.archive.org/web/20210126045809/http://ed-thelen.org/comp-hist/BRL-i.html#IBM-CPC | url-status = live }}</ref><ref name="weik1961">{{cite journal | last = Weik | first = Martin H. | title = A Third Survey of Domestic Electronic Digital Computing Systems | publisher = [[Ballistic Research Laboratory]] | url = http://ed-thelen.org/comp-hist/BRL61.html | year = 1961 | access-date = 2005-12-16 | archive-date = 2017-09-11 | archive-url = https://web.archive.org/web/20170911041654/http://ed-thelen.org/comp-hist/BRL61.html | url-status = live |website=Ed Thelen's Nike Missile Web Site }}</ref> Since the term "CPU" is generally defined as a device for [[software]] (computer program) execution, the earliest devices that could rightly be called CPUs came with the advent of the [[stored-program computer]].

The idea of a stored-program computer had already been present in the design of [[J. Presper Eckert|John Presper Eckert]] and [[John William Mauchly]]'s [[ENIAC]], but was initially omitted so that it could be finished sooner.<ref>{{cite web|title=Bit By Bit|url=http://ds.haverford.edu/bitbybit/bit-by-bit-contents/chapter-five/5-1-stored-program-computing/|archive-url=https://web.archive.org/web/20121013210908/http://ds.haverford.edu/bitbybit/bit-by-bit-contents/chapter-five/5-1-stored-program-computing/|publisher=Haverford College|access-date=August 1, 2015|archive-date=October 13, 2012|url-status=dead}}</ref> On June 30, 1945, before ENIAC was made, mathematician [[John von Neumann]] distributed a paper entitled ''[[First Draft of a Report on the EDVAC]]''. It was the outline of a stored-program computer that would eventually be completed in August 1949.<ref>{{cite tech report | title = First Draft of a Report on the EDVAC | publisher = [[Moore School of Electrical Engineering]], [[University of Pennsylvania]] | url = https://www.wiley.com/legacy/wileychi/wang_archi/supp/appendix_a.pdf | year = 1945 | access-date = 2018-03-31 | archive-date = 2021-03-09 | archive-url = https://web.archive.org/web/20210309062704/https://www.wiley.com/legacy/wileychi/wang_archi/supp/appendix_a.pdf | url-status = live }}</ref> [[EDVAC]] was designed to perform a certain number of instructions (or operations) of various types. Significantly, the programs written for EDVAC were to be stored in high-speed [[Memory (computers)|computer memory]] rather than specified by the physical wiring of the computer.<ref>{{cite encyclopedia|title=The Modern History of Computing|url=https://plato.stanford.edu/entries/computing-history/|author=Stanford University|encyclopedia=The Stanford Encyclopedia of Philosophy|access-date=September 25, 2015}}</ref> This overcame a severe limitation of ENIAC, which was the considerable time and effort required to reconfigure the computer to perform a new task.<ref>{{cite web |title=ENIAC's Birthday |url=https://mitpress.mit.edu/blog/eniacs-birthday |publisher=The MIT Press |access-date=October 17, 2018 |date=February 9, 2016 |archive-date=October 17, 2018 |archive-url=https://web.archive.org/web/20181017163347/https://mitpress.mit.edu/blog/eniacs-birthday |url-status=dead }}</ref> With von Neumann's design, the program that EDVAC ran could be changed simply by changing the contents of the memory. EDVAC was not the first stored-program computer; the [[Manchester Baby]], which was a small-scale experimental stored-program computer, ran its first program on 21 June 1948<ref>{{citation |last=Enticknap |first=Nicholas |title=Computing's Golden Jubilee |journal=Resurrection |issue=20 |publisher=The Computer Conservation Society |date=Summer 1998 |url=http://www.computerconservationsociety.org/resurrection/res20.htm#d |issn=0958-7403 |access-date=26 June 2019 |archive-date=17 March 2019 |archive-url=https://web.archive.org/web/20190317222331/http://www.computerconservationsociety.org/resurrection/res20.htm#d |url-status=live }}</ref> and the [[Manchester Mark 1]] ran its first program during the night of 16–17 June 1949.<ref>{{cite web|title=The Manchester Mark 1|url=http://curation.cs.manchester.ac.uk/digital60/www.digital60.org/birth/manchestercomputers/mark1/manchester.html|work=The University of Manchester|access-date=September 25, 2015|archive-date=January 25, 2015|archive-url=https://web.archive.org/web/20150125141909/http://curation.cs.manchester.ac.uk/digital60/www.digital60.org/birth/manchestercomputers/mark1/manchester.html|url-status=live}}</ref>

Early CPUs were custom designs used as part of a larger and sometimes distinctive computer.<ref>{{cite web|title=The First Generation|url=http://www.computerhistory.org/revolution/birth-of-the-computer/4/92|publisher=Computer History Museum|access-date=September 29, 2015|archive-date=November 22, 2016|archive-url=https://web.archive.org/web/20161122064835/http://www.computerhistory.org/revolution/birth-of-the-computer/4/92|url-status=live}}</ref> However, this method of designing custom CPUs for a particular application has largely given way to the development of multi-purpose processors produced in large quantities. This standardization began in the era of discrete [[transistor]] [[Mainframe computer|mainframes]] and [[minicomputer]]s, and has rapidly accelerated with the popularization of the [[integrated circuit]] (IC). The IC has allowed increasingly complex CPUs to be designed and manufactured to tolerances on the order of [[Nanometre|nanometers]].<ref name="nobel">{{cite web|title=The History of the Integrated Circuit|url=https://educationalgames.nobelprize.org/educational/physics/integrated_circuit/history/index.html|website=Nobelprize.org|access-date=July 17, 2022|archive-date=May 22, 2022|archive-url=https://web.archive.org/web/20220522104138/https://educationalgames.nobelprize.org/educational/physics/integrated_circuit/history/index.html|url-status=live}}</ref> Both the miniaturization and standardization of CPUs have increased the presence of digital devices in modern life far beyond the limited application of dedicated computing machines. Modern microprocessors appear in electronic devices ranging from automobiles<ref>{{cite web|last1=Turley|first1=Jim|title=Motoring with microprocessors|date=11 August 2003|url=https://www.embedded.com/motoring-with-microprocessors/|publisher=Embedded|access-date=December 26, 2022|archive-date=14 October 2022|archive-url=https://web.archive.org/web/20221014214157/https://www.embedded.com/motoring-with-microprocessors/|url-status=live}}</ref> to cellphones,<ref>{{cite web|title=Mobile Processor Guide – Summer 2013|url=http://www.androidauthority.com/mobile-processor-guide-summer-2013-234354/|publisher=Android Authority|access-date=November 15, 2015|date=2013-06-25|archive-date=2015-11-17|archive-url=https://web.archive.org/web/20151117034027/http://www.androidauthority.com/mobile-processor-guide-summer-2013-234354/|url-status=live}}</ref> and sometimes even in toys.<ref>{{cite web |title=Section 250: Microprocessors and Toys: An Introduction to Computing Systems |url=https://eng100.engin.umich.edu/list/sec250/ |publisher=The University of Michigan |access-date=October 9, 2018 |archive-date=April 13, 2021 |archive-url=https://web.archive.org/web/20210413194655/https://eng100.engin.umich.edu/list/sec250/ |url-status=dead }}</ref><ref>{{cite web|title=ARM946 Processor |url=https://www.arm.com/products/processors/classic/arm9/arm946.php|publisher=ARM|url-status=dead|archive-url = https://web.archive.org/web/20151117015143/https://www.arm.com/products/processors/classic/arm9/arm946.php|archive-date = 17 November 2015}}</ref>

While von Neumann is most often credited with the design of the stored-program computer because of his design of EDVAC, and the design became known as the [[von Neumann architecture]], others before him, such as [[Konrad Zuse]], had suggested and implemented similar ideas.<ref>{{cite web |title=Konrad Zuse |date=18 August 2025 |url=https://computerhistory.org/profile/konrad-zuse/ |publisher=Computer History Museum |access-date=September 26, 2025}}</ref> The so-called [[Harvard architecture]] of the [[Harvard Mark I]], which was completed before EDVAC,<ref>{{cite web|title=Timeline of Computer History: Computers|url=https://www.computerhistory.org/timeline/computers/|publisher=Computer History Museum|access-date=November 21, 2015|archive-date=December 29, 2017|archive-url=https://web.archive.org/web/20171229052342/http://www.computerhistory.org/timeline/computers/|url-status=live}}</ref><ref>{{cite web |last=White |first=Stephen |title=A Brief History of Computing – First Generation Computers |url=http://trillian.randomstuff.org.uk/~stephen/history/timeline-GEN1.html |url-status=live |archive-url=https://web.archive.org/web/20180102205958/http://trillian.randomstuff.org.uk/~stephen/history/timeline-GEN1.html |archive-date=January 2, 2018 |access-date=November 21, 2015}}</ref> also used a stored-program design using [[Punched tape|punched paper tape]] rather than electronic memory.<ref>{{cite web |title=Harvard University Mark I Paper Tape Punch Unit |url=https://www.computerhistory.org/collections/catalog/102698407 |url-status=live |archive-url=https://web.archive.org/web/20151122011934/http://www.computerhistory.org/collections/catalog/102698407 |archive-date=November 22, 2015 |access-date=November 21, 2015 |publisher=Computer History Museum}}</ref> The key difference between the two is that Harvard architecture separates the storage and treatment of CPU instructions and data, whereas von Neumann architecture uses the same memory space for both.<ref>{{cite web|title=What is the difference between a von Neumann architecture and a Harvard architecture?|url=http://infocenter.arm.com/help/index.jsp?topic=%2Fcom.arm.doc.faqs%2F3738.html|publisher=ARM|access-date=November 22, 2015|archive-date=November 18, 2015|archive-url=https://web.archive.org/web/20151118200529/http://infocenter.arm.com/help/index.jsp?topic=%2Fcom.arm.doc.faqs%2F3738.html|url-status=live}}</ref> Most modern CPUs are primarily von Neumann in design, but CPUs with the Harvard architecture are seen as well, especially in embedded applications; for instance, the [[Atmel AVR]] microcontrollers are Harvard-architecture processors.<ref>{{cite web|title=Advanced Architecture Optimizes the Atmel AVR CPU|url=http://www.atmel.com/technologies/cpu_core/avr.aspx|publisher=Atmel|access-date=November 22, 2015|archive-date=November 14, 2015|archive-url=https://web.archive.org/web/20151114090428/http://www.atmel.com/technologies/cpu_core/avr.aspx|url-status=dead}}</ref>

Prior to the invention of the transistor, [[relay]]s and [[vacuum tube]]s (thermionic tubes) were commonly used as switching elements;<ref>{{cite web|title=Switches, transistors and relays|url=http://www.bbc.co.uk/schools/gcsebitesize/design/electronics/switchesrev5.shtml|publisher=BBC |url-status=dead|archive-url = https://web.archive.org/web/20161205142752/http://www.bbc.co.uk/schools/gcsebitesize/design/electronics/switchesrev5.shtml|archive-date = 5 December 2016}}</ref><ref>{{cite web|title=Introducing the Vacuum Transistor: A Device Made of Nothing|url=https://spectrum.ieee.org/introducing-the-vacuum-transistor-a-device-made-of-nothing|website=IEEE Spectrum|access-date=27 January 2019|date=2014-06-23|archive-date=2018-03-23|archive-url=https://web.archive.org/web/20180323183612/https://spectrum.ieee.org/semiconductors/devices/introducing-the-vacuum-transistor-a-device-made-of-nothing|url-status=live}}</ref> a useful computer requires thousands or tens of thousands of switching devices. The overall speed of a system is dependent on the speed of the switches. [[Vacuum-tube computer]]s such as EDVAC tended to average eight hours between failures, whereas relay computers—such as the slower but earlier [[Harvard Mark I]]—failed very rarely.<ref name="weik1961" /> In the end, tube-based CPUs became dominant because the significant speed advantages afforded generally outweighed the reliability problems. Most of these early synchronous CPUs ran at low [[clock rate]]s compared to modern microelectronic designs. Clock signal frequencies ranging from 100 [[Hertz|kHz]] to 4&nbsp;MHz were very common at this time, limited largely by the speed of the switching devices they were built with.<ref>{{cite book|title=What Is Computer Performance?|url=http://www.nap.edu/read/12980/chapter/5#55|publisher=The National Academies Press|access-date=May 16, 2016|doi=10.17226/12980|year=2011|isbn=978-0-309-15951-7|archive-date=June 5, 2016|archive-url=https://web.archive.org/web/20160605083842/http://www.nap.edu/read/12980/chapter/5#55|url-status=live}}</ref>

===Transistor CPUs===
[[File:IBM PPC604e 200.jpg|thumb|IBM PowerPC 604e processor]]
{{Main|Transistor computer}}
The design complexity of CPUs increased as various technologies facilitated the building of smaller and more reliable electronic devices. The first such improvement came with the advent of the [[transistor]]. Transistorized CPUs during the 1950s and 1960s no longer had to be built out of bulky, unreliable, and fragile switching elements, like [[vacuum tube]]s and [[relay]]s.<ref>{{cite web|title=1953: Transistorized Computers Emerge|url=http://www.computerhistory.org/siliconengine/transistorized-computers-emerge/|work=Computer History Museum|access-date=June 3, 2016|archive-date=June 1, 2016|archive-url=https://web.archive.org/web/20160601191253/http://www.computerhistory.org/siliconengine/transistorized-computers-emerge/|url-status=live}}</ref> With this improvement, more complex and reliable CPUs were built onto one or several [[printed circuit board]]s containing discrete (individual) components.

In 1964, [[IBM]] introduced its [[IBM System/360]] computer architecture that was used in a series of computers capable of running the same programs with different speeds and performances.<ref>{{cite web|url=http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS360.html|title=IBM System/360 Dates and Characteristics|publisher=IBM|date=2003-01-23|access-date=2016-01-13|archive-date=2017-11-21|archive-url=https://web.archive.org/web/20171121223500/http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_FS360.html|url-status=dead}}</ref> This was significant at a time when most electronic computers were incompatible with one another, even those made by the same manufacturer. To facilitate this improvement, IBM used the concept of a [[microprogram]] (often called "microcode"), which still sees widespread use in modern CPUs.<ref name="amdahl1964">{{cite journal | last1 = Amdahl | first1 = G. M. | author-link1 = Gene Amdahl | last2 = Blaauw | first2 = G. A. | author-link2 = Gerrit Blaauw | last3 = Brooks | first3 = F. P. Jr. | author-link3 = Fred Brooks | title = Architecture of the IBM System/360 | journal = IBM Journal of Research and Development | volume = 8 | issue = 2 | pages = 87–101 | issn = 0018-8646 | publisher = [[IBM]] | date = April 1964 | doi = 10.1147/rd.82.0087 }}</ref> The System/360 architecture was so popular that it dominated the [[mainframe computer]] market for decades and left a legacy that is continued by similar modern computers like the IBM [[IBM System z|zSeries]].<ref>{{cite web|last1=Brodkin|first1=John|title=50 years ago, IBM created mainframe that helped send men to the Moon|url=https://arstechnica.com/information-technology/2014/04/50-years-ago-ibm-created-mainframe-that-helped-bring-men-to-the-moon/|website=Ars Technica|date=7 April 2014|access-date=9 April 2016|archive-date=8 April 2016|archive-url=https://web.archive.org/web/20160408105602/http://arstechnica.com/information-technology/2014/04/50-years-ago-ibm-created-mainframe-that-helped-bring-men-to-the-moon/|url-status=live}}</ref><ref>{{cite web |last1=Clarke |first1=Gavin |title=Why won't you DIE? IBM's S/360 and its legacy at 50 |url=https://www.theregister.com/2014/04/07/ibm_s_360_50_anniversary/ |website=The Register |access-date=26 September 2025}}</ref> In 1965, [[Digital Equipment Corporation]] (DEC) introduced another influential computer aimed at the scientific and research markets—the [[PDP-8]].<ref>{{cite web|title=Online PDP-8 Home Page, Run a PDP-8|url=http://www.pdp8.net/index.shtml|website=PDP8|access-date=September 25, 2015|archive-date=August 11, 2015|archive-url=https://web.archive.org/web/20150811174442/http://www.pdp8.net/index.shtml|url-status=live}}</ref>
[[File:Board with SPARC64 VIIIfx processors on display in Fujitsu HQ.JPG|thumb|Fujitsu board with SPARC64 VIIIfx processors]]
Transistor-based computers had several distinct advantages over their predecessors. Aside from facilitating increased reliability and lower power consumption, transistors also allowed CPUs to operate at much higher speeds because of the short switching time of a transistor in comparison to a tube or relay.<ref>{{cite web|title=Transistors, Relays, and Controlling High-Current Loads|url=https://itp.nyu.edu/physcomp/lessons/electronics/transistors-relays-and-controlling-high-current-loads/|publisher=ITP Physical Computing|work=New York University|access-date=9 April 2016|archive-date=21 April 2016|archive-url=https://web.archive.org/web/20160421232136/https://itp.nyu.edu/physcomp/lessons/electronics/transistors-relays-and-controlling-high-current-loads/|url-status=live}}</ref> The increased reliability and dramatically increased speed of the switching elements, which were almost exclusively transistors by this time; CPU clock rates in the tens of megahertz were easily obtained during this period.<ref name = pcgamer>{{cite magazine|last1=Lilly|first1=Paul|title=A Brief History of CPUs: 31 Awesome Years of x86|url=http://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/|magazine=PC Gamer|access-date=June 15, 2016|date=2009-04-14|archive-date=2016-06-13|archive-url=https://web.archive.org/web/20160613202439/http://www.pcgamer.com/a-brief-history-of-cpus-31-awesome-years-of-x86/|url-status=live}}</ref> Additionally, while discrete transistor and IC CPUs were in heavy usage, new high-performance designs like [[single instruction, multiple data]] (SIMD) [[vector processor]]s began to appear.<ref name="patterson">{{cite book |last1=Patterson |first1=David A. |url=https://archive.org/details/computerorganiz000henn/page/751 |title=Computer Organization and Design: the Hardware/Software Interface |last2=Hennessy |first2=John L. |last3=Larus |first3=James R. |date=1999 |publisher=Kaufmann |isbn=978-1558604285 |edition=3rd printing of 2nd |location=San Francisco, California |page=[https://archive.org/details/computerorganiz000henn/page/751 751] |language=en-us}}</ref> These early experimental designs later gave rise to the era of specialized [[supercomputer]]s like those made by [[Cray|Cray Inc]] and [[Fujitsu|Fujitsu Ltd]].<ref name="patterson"/>

===Small-scale integration CPUs===
[[File:PDP-8i cpu.jpg|thumb|CPU, [[magnetic-core memory|core memory]] and [[external bus]] interface of a DEC [[PDP-8]]/I, made of medium-scale integrated circuits]]

During this period, a method of manufacturing many interconnected transistors in a compact space was developed. The [[integrated circuit]] (IC) allowed a large number of transistors to be manufactured on a single [[semiconductor]]-based [[Die (integrated circuit)|die]], or "chip". At first, only very basic non-specialized digital circuits such as [[NOR gate]]s were miniaturized into ICs.<ref>{{cite web |title=1962: Aerospace systems are first the applications for ICs in computers |url=http://www.computerhistory.org/siliconengine/aerospace-systems-are-first-the-applications-for-ics-in-computers/ |publisher=[[Computer History Museum]] |access-date=October 9, 2018 |archive-date=October 5, 2018 |archive-url=https://web.archive.org/web/20181005083606/http://www.computerhistory.org/siliconengine/aerospace-systems-are-first-the-applications-for-ics-in-computers/ |url-status=live }}</ref> CPUs based on these "building block" ICs are generally referred to as "small-scale integration" (SSI) devices. SSI ICs, such as the ones used in the [[Apollo Guidance Computer]], usually contained up to a few dozen transistors. To build an entire CPU out of SSI ICs required thousands of individual chips, but still consumed much less space and power than earlier discrete transistor designs.<ref>{{cite web |title=The integrated circuits in the Apollo manned lunar landing program |url=https://www.hq.nasa.gov/alsj/ic-pg3.html |publisher=National Aeronautics and Space Administration |access-date=October 9, 2018 |archive-date=July 21, 2019 |archive-url=https://web.archive.org/web/20190721173218/https://www.hq.nasa.gov/alsj/ic-pg3.html |url-status=live }}</ref>

IBM's [[System/370]], follow-on to the System/360, used SSI ICs rather than [[Solid Logic Technology]] discrete-transistor modules.<ref>{{cite web|title=System/370 Announcement|url=http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PR370.html|website=IBM Archives|access-date=October 25, 2017|date=2003-01-23|archive-date=2018-08-20|archive-url=https://web.archive.org/web/20180820122836/https://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PR370.html|url-status=dead}}</ref><ref>{{cite web|title=System/370 Model 155 (Continued)|url=https://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP3155B.html|website=IBM Archives|access-date=October 25, 2017|date=2003-01-23|archive-date=2016-07-20|archive-url=https://web.archive.org/web/20160720234350/http://www-03.ibm.com/ibm/history/exhibits/mainframe/mainframe_PP3155B.html|url-status=dead}}</ref> DEC's [[PDP-8]]/I and KI10 [[PDP-10]] also switched from the individual transistors used by the PDP-8 and KA PDP-10 to SSI ICs,<ref>{{cite web|url=http://homepage.divms.uiowa.edu/~jones/pdp8/models/|title=Models and Options|publisher=The Digital Equipment Corporation PDP-8|access-date=June 15, 2018|archive-date=June 26, 2018|archive-url=https://web.archive.org/web/20180626145311/http://homepage.divms.uiowa.edu/~jones/pdp8/models/|url-status=live}}</ref> and their extremely popular [[PDP-11]] line was originally built with SSI ICs, but was eventually implemented with LSI components once these became practical.

===Large-scale integration CPUs===
[[Lee Boysel]] published influential articles, including a 1967 "manifesto", which described how to build the equivalent of a 32-bit mainframe computer from a relatively small number of [[large-scale integration]] circuits (LSI).<ref>{{cite book |author=Bassett |first=Ross Knox |url=https://books.google.com/books?id=UUbB3d2UnaAC |title=To the Digital Age: Research Labs, Start-up Companies, and the Rise of MOS Technology |publisher=[[The Johns Hopkins University Press]] |year=2007 |isbn=978-0-8018-6809-2 |pages=127–128, 256, and 314 |language=en-us}}</ref><ref name="shirriff">{{cite web |first=Ken |last=Shirriff
|url=http://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |title=The Texas Instruments TMX 1795: the first, forgotten microprocessor |archive-url=https://web.archive.org/web/20210126074942/http://www.righto.com/2015/05/the-texas-instruments-tmx-1795-first.html |archive-date=2021-01-26 |url-status=live}}</ref> The only way to build LSI chips, which are chips with a hundred or more gates, was to build them using a [[MOSFET|metal–oxide–semiconductor]] (MOS) [[semiconductor manufacturing process]] (either [[PMOS logic]], [[NMOS logic]], or [[CMOS]] logic). However, some companies continued to build processors out of bipolar [[transistor–transistor logic]] (TTL) chips because bipolar junction transistors were faster than MOS chips up until the 1970s (a few companies such as [[Datapoint]] continued to build processors out of TTL chips until the early 1980s).<ref name="shirriff" /> In the 1960s, MOS ICs were slower and initially considered useful only in applications that required low power.<ref>{{cite web|url=https://www.brown.edu/Departments/Engineering/Labs/ddzo/speed.html|title=Speed & Power in Logic Families|access-date=2017-08-02|archive-date=2017-07-26|archive-url=https://web.archive.org/web/20170726175011/http://www.brown.edu/Departments/Engineering/Labs/ddzo/speed.html|url-status=live}}.</ref><ref>{{cite book |first=T. J. |last=Stonham |url=https://books.google.com/books?id=UE6vFEnGP2kC |title=Digital Logic Techniques: Principles and Practice |date=1996 |page=174|publisher=Taylor & Francis |isbn=9780412549700 }}</ref> Following the development of [[silicon-gate]] MOS technology by [[Federico Faggin]] at Fairchild Semiconductor in 1968, MOS ICs largely replaced bipolar TTL as the standard chip technology in the late 1970s.<ref>{{cite web |title=1968: Silicon Gate Technology Developed for ICs |url=https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |website=Computer History Museum |access-date=2019-08-16 |archive-date=2020-07-29 |archive-url=https://web.archive.org/web/20200729145834/https://www.computerhistory.org/siliconengine/silicon-gate-technology-developed-for-ics/ |url-status=live }}</ref>

As the [[microelectronic]] technology advanced, an increasing number of transistors were placed on ICs, decreasing the number of individual ICs needed for a complete CPU. MSI and LSI ICs increased transistor counts to hundreds, and then thousands. By 1968, the number of ICs required to build a complete CPU had been reduced to 24 ICs of eight different types, with each IC containing roughly 1000 MOSFETs.<ref>{{cite conference |first=R. K. |last=Booher |url=http://www.computer.org/csdl/proceedings/afips/1968/5072/00/50720877.pdf |title=MOS GP Computer |publisher=[[AFIPS]] |page=877 |date=1968 |conference=International Workshop on Managing Requirements Knowledge
|doi=10.1109/AFIPS.1968.126 |archive-url=https://web.archive.org/web/20170714014430/https://www.computer.org/csdl/proceedings/afips/1968/5072/00/50720877.pdf |archive-date=2017-07-14 |url-status=live}}</ref> In stark contrast with its SSI and MSI predecessors, the first LSI implementation of the PDP-11 contained a CPU composed of only four LSI integrated circuits.<ref>{{cite book |title=LSI-11, PDP-11/03 user's manual |date=November 1975 |publisher=[[Digital Equipment Corporation]] |edition=2nd |location=Maynard, Massachusetts |page=4{{hyp}}3 |language=en-us |chapter=LSI-11 Module Descriptions |access-date=2015-02-20 |url=http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdf |archive-url=https://web.archive.org/web/20211010023115/http://www.bitsavers.org/pdf/dec/pdp11/1103/EK-LSI11-TM-002.pdf |archive-date=2021-10-10 |url-status=live}}</ref>

===Microprocessors===
{{main|Microprocessor}}
{{multiple image
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|image1 = 80486dx2-large.jpg
|caption1 = [[Die (integrated circuit)|Die]] of an [[Intel 80486DX2]] microprocessor (actual size: 12 × 6.75&nbsp;mm) in its packaging
|image2 = EBIntel Corei5.JPG
|caption2 = [[Intel]] Core i5 CPU on a [[Sony Vaio E series|Vaio E series]] laptop motherboard (on the right, beneath the [[heat pipe]])
}}
[[File:Laptop-intel-core2duo-t5500.jpg|thumb|Inside of a laptop, with the CPU removed from socket]]
Since microprocessors were first introduced they have almost completely overtaken all other central processing unit implementation methods. The first commercially available microprocessor, made in 1971, was the [[Intel 4004]]. The Intel 4004 was one of the first consumer-facing CPU integrating [[arithmetic logic unit]], [[control unit]], and [[processor register|register unit]] on a chip.<ref>{{Cite web |title=Chip Hall of Fame: Intel 4004 Microprocessor - IEEE Spectrum |url=https://spectrum.ieee.org/chip-hall-of-fame-intel-4004-microprocessor |access-date=2025-08-10 |website=spectrum.ieee.org |language=en}}</ref> The first widely used microprocessor, made in 1974, was the [[Intel 8080]]. Mainframe and minicomputer manufacturers of the time launched proprietary IC development programs to upgrade their older [[computer architecture]]s, and eventually produced [[instruction set architecture|instruction set]] compatible microprocessors that were backward-compatible with their older hardware and software. Combined with the advent and eventual success of the ubiquitous [[personal computer]], the term ''CPU'' is now applied almost exclusively{{Efn|Integrated circuits are now used to implement all CPUs, except for a few machines designed to withstand large electromagnetic pulses, say from a nuclear weapon.}} to microprocessors. Several CPUs (denoted ''cores'') can be combined in a single processing chip.<ref>{{cite web |url=https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |publisher=TechTarget |title=What is a multicore processor and how does it work? |first=Stephen J. |last=Bigelow |date=March 2022 |access-date=July 17, 2022 |archive-date=July 11, 2022 |archive-url=https://web.archive.org/web/20220711210214/https://www.techtarget.com/searchdatacenter/definition/multi-core-processor |url-status=live }}</ref>

{{anchor|DISCRETE-PROCESSOR}}
Previous generations of CPUs were implemented as [[discrete components]] and numerous small [[integrated circuit]]s (ICs) on one or more circuit boards.<ref>{{cite web |author=Birkby |first=Richard |title=A Brief History of the Microprocessor |url=http://www.computermuseum.li/Testpage/MicroprocessorHistory.htm |url-status=dead |archive-url=https://web.archive.org/web/20150923205820/http://www.computermuseum.li/Testpage/MicroprocessorHistory.htm |archive-date=September 23, 2015 |access-date=October 13, 2015 |website=computermuseum.li}}</ref> Microprocessors, on the other hand, are CPUs manufactured on a very small number of ICs; usually just one.<ref name=Osborne80>{{cite book | first=Adam | last=Osborne | title=An Introduction to Microcomputers | volume=1: Basic Concepts | edition=2nd | publisher=Osborne-McGraw Hill | location=Berkeley, California | year=1980 | isbn=978-0-931988-34-9 | url=https://archive.org/details/introductiontomi00adam }}</ref> The overall smaller CPU size, as a result of being implemented on a single die, means faster switching time because of physical factors like decreased gate [[parasitic capacitance]].<ref>{{cite web|last1=Zhislina|first1=Victoria|title=Why has CPU frequency ceased to grow?|url=https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|publisher=Intel|access-date=October 14, 2015|date=2014-02-19|archive-date=2017-06-21|archive-url=https://web.archive.org/web/20170621074555/https://software.intel.com/en-us/blogs/2014/02/19/why-has-cpu-frequency-ceased-to-grow|url-status=live}}</ref><ref>{{cite web |title=MOS Transistor – Electrical Engineering & Computer Science |url=http://www.eecs.berkeley.edu/~tking/theses/bsriram.pdf |url-status=live |archive-url=https://ghostarchive.org/archive/20221009/http://www.eecs.berkeley.edu/~tking/theses/bsriram.pdf |archive-date=2022-10-09 |access-date=October 14, 2015 |publisher=University of California}}</ref> This has allowed synchronous microprocessors to have clock rates ranging from tens of megahertz to several gigahertz. Additionally, the ability to construct exceedingly small transistors on an IC has increased the complexity and number of transistors in a single CPU many fold. This widely observed trend is described by [[Moore's law]], which had proven to be a fairly accurate predictor of the growth of CPU (and other IC) complexity until 2016.<ref>{{Cite news|url=https://www.technologyreview.com/s/601441/moores-law-is-dead-now-what/|title=Moore's Law Is Dead. Now What?|last=Simonite|first=Tom|work=MIT Technology Review|access-date=2018-08-24|language=en|archive-date=2018-08-22|archive-url=https://web.archive.org/web/20180822071655/https://www.technologyreview.com/s/601441/moores-law-is-dead-now-what/|url-status=live}}</ref><ref name="MooresLaw">{{cite interview|title=Excerpts from A Conversation with Gordon Moore: Moore's Law |first=Gordon |last=Moore |author-link=Gordon Moore |publisher=Intel |year=2005 |url=http://download.intel.com/museum/Moores_Law/Video-Transcripts/Excepts_A_Conversation_with_Gordon_Moore.pdf |access-date=2012-07-25 |url-status=dead |archive-url=https://web.archive.org/web/20121029060050/http://download.intel.com/museum/Moores_Law/Video-Transcripts/Excepts_A_Conversation_with_Gordon_Moore.pdf |archive-date=2012-10-29 }}</ref>

While the complexity, size, construction and general form of CPUs have changed enormously since 1950,<ref>{{cite web|title=A detailed history of the processor|url=https://www.techjunkie.com/a-cpu-history/|publisher=Tech Junkie|date=15 December 2016|access-date=14 August 2019|archive-date=14 August 2019|archive-url=https://web.archive.org/web/20190814125742/https://www.techjunkie.com/a-cpu-history/|url-status=live}}</ref> the basic design and function has not changed much at all. Almost all common CPUs today can be very accurately described as von Neumann stored-program machines.<ref>{{cite book |chapter=Von Neumann Computers | first1=Rudolf|last1= Eigenmann |first2= David|last2=Lilja|title=Wiley Encyclopedia of Electrical and Electronics Engineering |s2cid=8197337 |year=1998 |doi=10.1002/047134608X.W1704 |isbn=047134608X }}</ref>{{Efn|The so-called "von Neumann" memo expounded the idea of stored programs,<ref>{{cite magazine|last1=Aspray|first1=William|title=The stored program concept |doi=10.1109/6.58457|magazine=IEEE Spectrum|volume=27|issue=9|date=September 1990|page=51 }}</ref> which for example may be stored on [[punched card]]s, paper tape, or magnetic tape.}} As Moore's law no longer holds, concerns have arisen about the limits of integrated circuit transistor technology. Extreme miniaturization of [[logic gate|electronic gates]] is causing the effects of phenomena like [[electromigration]] and [[subthreshold leakage]] to become much more significant.<ref>{{cite web |last1= Saraswat |first1=Krishna |title=Trends in Integrated Circuits Technology |url=https://web.stanford.edu/class/ee311/NOTES/TrendsSlides.pdf |archive-url=https://web.archive.org/web/20150724091731/https://web.stanford.edu/class/ee311/NOTES/TrendsSlides.pdf |archive-date=2015-07-24 |url-status=dead|access-date=June 15, 2018}}</ref><ref>{{cite web |title=Electromigration |url=http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm |publisher=Middle East Technical University |access-date=June 15, 2018 |archive-date=July 31, 2017 |archive-url=https://web.archive.org/web/20170731070649/http://www.csl.mete.metu.edu.tr/Electromigration/emig.htm |url-status=live }}</ref> These newer concerns are among the many factors causing researchers to investigate new methods of computing such as the [[quantum computer]], as well as to expand the use of [[Parallel computing|parallelism]] and other methods that extend the usefulness of the classical von Neumann model.

==Operation==
The fundamental operation of most CPUs, regardless of the physical form they take, is to execute a sequence of stored [[instruction (computing)|instructions]] that is called a program. The instructions to be executed are kept in some kind of [[Memory (computers)|computer memory]]. Nearly all CPUs follow the fetch, decode and execute steps in their operation, which are collectively known as the [[instruction cycle]].

After the execution of an instruction, the entire process repeats, with the next instruction cycle normally fetching the next-in-sequence instruction because of the incremented value in the [[program counter]]. If a jump instruction was executed, the program counter will be modified to contain the address of the instruction that was jumped to and program execution continues normally. In more complex CPUs, multiple instructions can be fetched, decoded and executed simultaneously. This section describes what is generally referred to as the "[[classic RISC pipeline]]", which is quite common among the simple CPUs used in many electronic devices (often called microcontrollers). It largely ignores the important role of CPU cache, and therefore the access stage of the pipeline.

Some instructions manipulate the program counter rather than producing result data directly; such instructions are generally called "jumps" and facilitate program behavior like [[Control flow#Loops|loops]], conditional program execution (through the use of a conditional jump), and existence of [[Subroutine|functions]].{{Efn|Some early computers, like the Harvard Mark I, did not support any kind of "jump" instruction, effectively limiting the complexity of the programs they could run. It is largely for this reason that these computers are often not considered to contain a proper CPU, despite their close similarity to stored-program computers.}} In some processors, some other instructions change the state of bits in a [[Status register|"flags" register]]. These flags can be used to influence how a program behaves, since they often indicate the outcome of various operations. For example, in such processors a "compare" instruction evaluates two values and sets or clears bits in the flags register to indicate which one is greater or whether they are equal; one of these flags could then be used by a later jump instruction to determine program flow.

===Fetch===
Fetch involves retrieving an [[instruction (computing)|instruction]] (which is represented by a number or sequence of numbers) from program memory. The instruction's location (address) in program memory is determined by the [[program counter]] (PC; called the "instruction pointer" in [[x86|Intel x86 microprocessors]]), which stores a number that identifies the address of the next instruction to be fetched. After an instruction is fetched, the PC is incremented by the length of the instruction so that it will contain the address of the next instruction in the sequence.{{Efn|Since the program counter counts ''memory addresses'' and not ''instructions'', it is incremented by the number of memory units that the instruction word contains. In the case of simple fixed-length instruction word ISAs, this is always the same number. For example, a fixed-length 32-bit instruction word ISA that uses 8-bit memory words would always increment the PC by four (except in the case of jumps). ISAs that use variable-length instruction words increment the PC by the number of memory words corresponding to the last instruction's length.}} Often, the instruction to be fetched must be retrieved from relatively slow memory, causing the CPU to stall while waiting for the instruction to be returned. This issue is largely addressed in modern processors by caches and pipeline architectures (see below).

===Decode===
{{Further|Instruction set architecture#Instruction encoding}}

The instruction that the CPU fetches from memory determines what the CPU will do. In the decode step, performed by [[binary decoder]] circuitry known as the ''instruction decoder'', the instruction is converted into signals that control other parts of the CPU.

The way in which the instruction is interpreted is defined by the CPU's instruction set architecture (ISA).{{Efn|Because the instruction set architecture of a CPU is fundamental to its interface and usage, it is often used as a classification of the "type" of CPU. For example, a "PowerPC CPU" uses some variant of the PowerPC ISA. A CPU of a certain ISA can execute a different ISA by running an emulator.}} Often, one group of bits (that is, a "field") within the instruction, called the [[opcode]], indicates which operation is to be performed, while the remaining fields usually provide supplemental information required for the operation, such as the operands. Those operands may be specified as a constant value (called an immediate value), or as the location of a value that may be a [[processor register]] or a memory address, as determined by some [[addressing mode]].

In some CPU designs, the instruction decoder is implemented as a hardwired, unchangeable binary decoder circuit. In others, a [[microprogram]] is used to translate instructions into sets of CPU configuration signals that are applied sequentially over multiple clock pulses. In some cases the memory that stores the microprogram is rewritable, making it possible to change the way in which the CPU decodes instructions.

===Execute===
After the fetch and decode steps, the execute step is performed. Depending on the CPU architecture, this may consist of a single action or a sequence of actions. During each action, control signals electrically enable or disable various parts of the CPU so they can perform all or part of the desired operation. The action is then completed, typically in response to a clock pulse. Very often the results are written to an internal CPU register for quick access by subsequent instructions. In other cases results may be written to slower, but less expensive and higher capacity [[random-access memory|main memory]].

For example, if an instruction that performs addition is to be executed, registers containing operands (numbers to be summed) are activated, as are the parts of the [[arithmetic logic unit]] (ALU) that perform addition. When the clock pulse occurs, the operands flow from the source registers into the ALU, and the sum appears at its output. On subsequent clock pulses, other components are enabled (and disabled) to move the output (the sum of the operation) to storage (e.g., a register or memory). If the resulting sum is too large (i.e., it is larger than the ALU's output word size), an arithmetic overflow flag will be set, influencing the next operation.

==Structure and implementation==
{{See also|Processor design}}
[[File:ABasicComputer.svg|thumb|upright=1.7|Block diagram of a basic uniprocessor-CPU computer. Black lines indicate data flow, whereas red lines indicate control flow; arrows indicate flow directions.]]

Hardwired into a CPU's circuitry is a set of basic operations it can perform, called an [[instruction set architecture|instruction set]]. Such operations may involve, for example, adding or subtracting two numbers, comparing two numbers, or jumping to a different part of a program. Each instruction is represented by a unique combination of [[bit]]s, known as the machine language [[opcode]]. While processing an instruction, the CPU decodes the opcode (via a [[binary decoder]]) into control signals, which orchestrate the behavior of the CPU. A complete machine language instruction consists of an opcode and, in many cases, additional bits that specify arguments for the operation (for example, the numbers to be summed in the case of an addition operation). Going up the complexity scale, a machine language program is a collection of machine language instructions that the CPU executes.

The actual mathematical operation for each instruction is performed by a [[combinational logic]] circuit within the CPU's processor known as the [[arithmetic–logic unit]] or ALU. In general, a CPU executes an instruction by fetching it from memory, using its ALU to perform an operation, and then storing the result to memory. Besides the instructions for integer mathematics and logic operations, various other machine instructions exist, such as those for loading data from memory and storing it back, branching operations, and mathematical operations on floating-point numbers performed by the CPU's [[floating-point unit]] (FPU).<ref>{{cite web |author=Wienand |first=Ian |date=September 3, 2013 |title=Computer Science from the Bottom Up, Chapter 3. Computer Architecture |url=http://www.bottomupcs.com/csbu.pdf#page=44 |url-status=live |archive-url=https://web.archive.org/web/20160206225834/http://www.bottomupcs.com/csbu.pdf#page=44 |archive-date=February 6, 2016 |access-date=January 7, 2015 |website=bottomupcs.com |format=PDF}}</ref>

===Control unit===
{{main|Control unit}}
The control unit (CU) is a component of the CPU that directs the operation of the processor. It tells the computer's memory, arithmetic and logic unit and input and output devices how to respond to the instructions that have been sent to the processor.

It directs the operation of the other units by providing timing and control signals. Most computer resources are managed by the CU. It directs the flow of data between the CPU and the other devices. [[John von Neumann]] included the control unit as part of the [[von Neumann architecture]]. In modern computer designs, the control unit is typically an internal part of the CPU with its overall role and operation unchanged since its introduction.<ref>{{Cite web|date=2018-09-24|title=Introduction of Control Unit and its Design|url=https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|access-date=2021-01-12|website=GeeksforGeeks|language=en-US|archive-date=2021-01-15|archive-url=https://web.archive.org/web/20210115072904/https://www.geeksforgeeks.org/introduction-of-control-unit-and-its-design/|url-status=live}}</ref>

===Arithmetic logic unit===
{{Main|Arithmetic logic unit}}
[[File:ALU block.gif|thumb|upright=1.3|Symbolic representation of an ALU and its input and output signals]]

The arithmetic logic unit (ALU) is a digital circuit within the processor that performs integer arithmetic and [[bitwise logic]] operations. The inputs to the ALU are the data words to be operated on (called [[operands]]), status information from previous operations, and a code from the control unit indicating which operation to perform. Depending on the instruction being executed, the operands may come from [[processor register|internal CPU registers]], external memory, or constants generated by the ALU itself.

When all input signals have settled and propagated through the ALU circuitry, the result of the performed operation appears at the ALU's outputs. The result consists of both a data word, which may be stored in a register or memory, and status information that is typically stored in a special, internal CPU register reserved for this purpose.

Modern CPUs typically contain more than one ALU to improve performance.

===Address generation unit===
{{Main|Address generation unit}}
The address generation unit (AGU), sometimes also called the address computation unit (ACU),<ref>{{cite web |last1=Van Berkel |first1=Cornelis |last2=Meuwissen |first2=Patrick |date=January 12, 2006 |title=Address generation unit for a processor (US 2006010255 A1 patent application) |url=https://patents.google.com/patent/US20060010255 |url-status=live |archive-url=https://web.archive.org/web/20160418074853/http://www.google.com/patents/US20060010255 |archive-date=April 18, 2016 |access-date=December 8, 2014 |website=google.com}} {{verify source|date=August 2019|reason=This ref was deleted ([[Special:Diff/897932214]]) by a bug in VisualEditor and later restored by a bot from the original cite at [[Special:Permalink/897793086]] cite #1 - please verify the cite's accuracy and remove this {verify source} template. [[User:GreenC bot/Job 18]]}}</ref> is an [[execution unit]] inside the CPU that calculates [[Memory address|addresses]] used by the CPU to access [[main memory]]. By having address calculations handled by separate circuitry that operates in parallel with the rest of the CPU, the number of [[CPU cycle]]s required for executing various [[machine instruction]]s can be reduced, bringing performance improvements.

While performing various operations, CPUs need to calculate memory addresses required for fetching data from the memory; for example, in-memory positions of [[array element]]s must be calculated before the CPU can fetch the data from actual memory locations. Those address-generation calculations involve different [[integer arithmetic operation]]s, such as addition, subtraction, [[modulo operation]]s, or [[bit shift]]s. Often, calculating a memory address involves more than one general-purpose machine instruction, which do not necessarily [[Instruction cycle|decode and execute]] quickly. By incorporating an AGU into a CPU design, together with introducing specialized instructions that use the AGU, various address-generation calculations can be offloaded from the rest of the CPU, and can often be executed quickly in a single CPU cycle.

Capabilities of an AGU depend on a particular CPU and its [[Computer architecture|architecture]]. Thus, some AGUs implement and expose more address-calculation operations, while some also include more advanced specialized instructions that can operate on multiple [[operand]]s at a time. Some CPU architectures include multiple AGUs so more than one address-calculation operation can be executed simultaneously, which brings further performance improvements due to the [[superscalar]] nature of advanced CPU designs. For example, [[Intel]] incorporates multiple AGUs into its [[Sandy Bridge (microarchitecture)|Sandy Bridge]] and [[Haswell (microarchitecture)|Haswell]] [[microarchitecture]]s, which increase bandwidth of the CPU memory subsystem by allowing multiple memory-access instructions to be executed in parallel.

===Memory management unit (MMU)===
{{Main|Memory management unit}}

Many microprocessors (in smartphones and desktop, laptop, server computers) have a memory management unit (MMU), translating logical addresses into physical RAM addresses, providing [[memory protection]] and [[paging]] abilities, useful for [[virtual memory]]. The MMU is usually integrated in the processor but in some cases it is in a separate integrated circuit (IC).<ref>{{Cite web |date=2024-02-13 |title=What is Memory Management Unit(MMU)? |url=https://www.geeksforgeeks.org/computer-organization-architecture/what-is-memory-management-unit/ |access-date=2025-09-25 |website=GeeksforGeeks |language=en-US}}</ref> Simpler processors, especially [[microcontroller]]s, usually do not include an MMU.

===Cache===
A [[CPU cache]] is a memory used by the central processing unit (CPU) of a [[computer]] to reduce the average cost (time or energy) to access [[Data (computing)|data]] from the [[main memory]].<ref>{{cite web |author=Torres |first=Gabriel |date=September 12, 2007 |title=How The Cache Memory Works |url=https://hardwaresecrets.com/how-the-cache-memory-works/ |access-date=January 29, 2023 |website=Hardware Secrets}}</ref> A cache is a smaller, faster memory, closer to a [[processor core]], which stores copies of the data from frequently used main [[memory location]]s. Most CPUs have different independent caches, usually organized as a hierarchy of several cache levels (L1, L2, L3, L4, etc.). Each ascending cache level is typically slower but larger than the preceding level with L1 being the fastest and the closest to the CPU. At the L1 level there are usually separate [[Instruction cache|instruction]] and [[data cache]]s.

Most modern (fast) CPUs (with few specialized exceptions{{efn|A few specialized CPUs, accelerators or microcontrollers do not have a cache. To be fast, if needed/wanted, they still have an on-chip scratchpad memory that has a similar function, while software managed. In e.g. microcontrollers it can be better for hard real-time use, to have that or at least no cache, as with one level of memory latencies of loads are predictable.}}) have multiple levels of CPU caches. The first CPUs that used a cache had only one level of cache; unlike later level 1 caches, it was not split into L1d (for data) and L1i (for instructions). Almost all current CPUs with caches have a split L1 cache. They also have L2 caches and, for larger processors, L3 caches as well. The L2 cache is usually not split and acts as a common repository for the already split L1 cache. Every core of a [[multi-core processor]] has a dedicated L2 cache and is usually not shared between the cores. The L3 cache, and higher-level caches, are shared between the cores and are not split. An L4 cache is currently uncommon, and is generally on [[dynamic random-access memory]] (DRAM), rather than on [[static random-access memory]] (SRAM), on a separate die or chip. That was also the case historically with L1, while bigger chips have allowed integration of it and generally all cache levels, with the possible exception of the last level. Each extra level of cache tends to be bigger and is optimized differently.

Other types of caches exist (that are not counted towards the "cache size" of the most important caches mentioned above), such as the [[translation lookaside buffer]] (TLB) that is part of the [[memory management unit]] (MMU) that most CPUs have.

Caches are generally sized in powers of two: 2, 8, 16 etc. [[Kibibyte|KiB]] or [[Mebibyte|MiB]] (for larger non-L1) sizes, although the [[IBM z13 (microprocessor)|IBM z13]] has a 96 KiB L1 instruction cache.<ref>{{cite web|url=http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.redbooks.ibm.com/redbooks/pdfs/sg248250.pdf |archive-date=2022-10-09 |url-status=live|title=IBM z13 and IBM z13s Technical Introduction|page=20|date=March 2016|publisher=[[IBM]]}}</ref>

===Clock rate===
{{Main|Clock rate}}
Most CPUs are [[synchronous circuit]]s, which means they employ a [[clock signal]] to pace their sequential operations. The clock signal is produced by an external [[Electronic oscillator|oscillator circuit]] that generates a consistent number of pulses each second in the form of a periodic [[Square wave (waveform)|square wave]]. The frequency of the clock pulses determines the rate at which a CPU executes instructions and, consequently, the faster the clock, the more instructions the CPU will execute each second.

To ensure proper operation of the CPU, the clock period is longer than the maximum time needed for all signals to propagate (move) through the CPU. In setting the clock period to a value well above the worst-case [[propagation delay]], it is possible to design the entire CPU and the way it moves data around the "edges" of the rising and falling clock signal. This has the advantage of simplifying the CPU significantly, both from a design perspective and a component-count perspective. However, it also carries the disadvantage that the entire CPU must wait on its slowest elements, even though some portions of it are much faster. This limitation has largely been compensated for by various methods of increasing CPU parallelism (see below).

However, architectural improvements alone do not solve all of the drawbacks of globally synchronous CPUs. For example, a clock signal is subject to the delays of any other electrical signal. Higher clock rates in increasingly complex CPUs make it more difficult to keep the clock signal in phase (synchronized) throughout the entire unit. This has led many modern CPUs to require multiple identical clock signals to be provided to avoid delaying a single signal significantly enough to cause the CPU to malfunction. Another major issue, as clock rates increase dramatically, is the amount of heat that is [[CPU power dissipation|dissipated by the CPU]]. The constantly changing clock causes many components to switch regardless of whether they are being used at that time. In general, a component that is switching uses more energy than an element in a static state. Therefore, as clock rate increases, so does energy consumption, causing the CPU to require more [[heat dissipation]] in the form of [[CPU cooling]] solutions.

One method of dealing with the switching of unneeded components is called [[clock gating]], which involves turning off the clock signal to unneeded components (effectively disabling them). However, this is often regarded as difficult to implement and therefore does not see common usage outside of very low-power designs. One notable CPU design that uses extensive clock gating is the IBM [[PowerPC]]-based [[Xenon (processor)|Xenon]] used in the [[Xbox 360]]; this reduces the power requirements of the Xbox 360.<ref>{{cite web | last = Brown | first = Jeffery | title = Application-customized CPU design | publisher = IBM developerWorks | url = http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw07XBoxDesign | year = 2005 | access-date = 2005-12-17 | archive-url = https://web.archive.org/web/20060212002837/http://www-128.ibm.com/developerworks/power/library/pa-fpfxbox/?ca=dgr-lnxw07XBoxDesign | archive-date = 2006-02-12 | url-status = dead}}</ref>

===Clockless CPUs===
Another method of addressing some of the problems with a global clock signal is the removal of the clock signal altogether. While removing the global clock signal makes the design process considerably more complex in many ways, asynchronous (or clockless) designs carry marked advantages in power consumption and [[heat dissipation]] in comparison with similar synchronous designs. While somewhat uncommon, entire [[Asynchronous circuit#Asynchronous CPU|asynchronous CPUs]] have been built without using a global clock signal. Two notable examples of this are the [[ARM architecture family|ARM]] compliant [[AMULET microprocessor|AMULET]] and the [[MIPS architecture|MIPS]] R3000 compatible MiniMIPS.<ref>{{Cite journal |last1=Martin |first1=A. J. |last2=Nystrom |first2=M. |last3=Wong |first3=C. G. |date=November 2003 |title=Three generations of asynchronous microprocessors |journal=IEEE Design & Test of Computers |volume=20 |issue=6 |pages=9–17 |doi=10.1109/MDT.2003.1246159 |bibcode=2003IDTC...20....9M |issn=0740-7475 |s2cid=15164301 }}</ref>

Rather than totally removing the clock signal, some CPU designs allow certain portions of the device to be asynchronous, such as using asynchronous [[Arithmetic logic unit|ALUs]] in conjunction with superscalar pipelining to achieve some arithmetic performance gains. While it is not altogether clear whether totally asynchronous designs can perform at a comparable or better level than their synchronous counterparts, it is evident that they do at least excel in simpler math operations. This, combined with their excellent power consumption and heat dissipation properties, makes them very suitable for [[embedded computer]]s.<ref>{{cite conference |author1=Garside, J. D. |author2=Furber, S. B. |author3= Chung, S-H | title = AMULET3 Revealed | publisher = [[University of Manchester]] Computer Science Department | year = 1999 | url = http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php |book-title=Proceedings, Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems |doi=10.1109/ASYNC.1999.761522 | archive-url=https://web.archive.org/web/20051210205845/http://www.cs.manchester.ac.uk/apt/publications/papers/async99_A3.php | archive-date=December 10, 2005 | url-status=dead| url-access=subscription }}</ref>

===Voltage regulator module===
{{Main|Voltage regulator module}}
Many modern CPUs have a die-integrated power managing module which regulates on-demand voltage supply to the CPU circuitry allowing it to keep balance between performance and power consumption.

===Integer range===
Every CPU represents numerical values in a specific way. For example, some early digital computers represented numbers as familiar [[decimal]] (base 10) [[numeral system]] values, and others have employed more unusual representations such as [[bi-quinary coded decimal]] (base 2–5) or [[Balanced ternary|ternary]] (base 3). Nearly all modern CPUs represent numbers in [[Binary numeral system|binary]] form, with each digit being represented by some two-valued physical quantity such as a "high" or "low" [[volt]]age.{{Efn|The physical concept of [[voltage]] is an analog one by nature, practically having an infinite range of possible values. For the purpose of physical representation of binary numbers, two specific ranges of voltages are defined, one for logic '0' and another for logic '1'. These ranges are dictated by design considerations such as noise margins and characteristics of the devices used to create the CPU.}}

[[File:Binary Forty.PNG|thumb|left|A six-bit word containing the binary encoded representation of decimal value 40. Most modern CPUs employ word sizes that are a power of two, for example 8, 16, 32 or 64 bits.]]

Related to numeric representation is the size and precision of integer numbers that a CPU can represent. In the case of a binary CPU, this is measured by the number of bits (significant digits of a binary encoded integer) that the CPU can process in one operation, which is commonly called [[Word (data type)|''word size'']], ''bit width'', ''data path width'', ''integer precision'', or ''integer size''. A CPU's integer size determines the range of integer values on which it can directly operate.{{Efn|While a CPU's integer size sets a limit on integer ranges, this can (and often is) overcome using a combination of software and hardware techniques. By using additional memory, software can represent integers many magnitudes larger than the CPU can. Sometimes the CPU's [[instruction set architecture|instruction set]] will even facilitate operations on integers larger than it can natively represent by providing instructions to make large integer arithmetic relatively quick. This method of dealing with large integers is slower than utilizing a CPU with higher integer size, but is a reasonable trade-off in cases where natively supporting the full integer range needed would be cost-prohibitive. See [[Arbitrary-precision arithmetic]] for more details on purely software-supported arbitrary-sized integers.}} For example, an [[8-bit computing|8-bit]] CPU can directly manipulate integers represented by eight bits, which have a range of 256 (2<sup>8</sup>) discrete integer values.

Integer range can also affect the number of memory locations the CPU can directly address (an address is an integer value representing a specific memory location). For example, if a binary CPU uses 32 bits to represent a memory address then it can directly address 2<sup>32</sup> memory locations. To circumvent this limitation and for various other reasons, some CPUs use mechanisms (such as [[memory management unit|memory management]] or [[bank switching]]) that allow additional memory to be addressed.

CPUs with larger word sizes require more circuitry and consequently are physically larger, cost more and consume more power (and therefore generate more heat). As a result, smaller 4- or 8-bit [[microcontroller]]s are commonly used in modern applications even though CPUs with much larger word sizes (such as 16, 32, 64, even 128-bit) are available. When higher performance is required, however, the benefits of a larger word size (larger data ranges and address spaces) may outweigh the disadvantages. A CPU can have internal data paths shorter than the word size to reduce size and cost. For example, even though the [[IBM System/360]] [[instruction set architecture]] was a 32-bit instruction set, the System/360 [[IBM System/360 Model 30|Model 30]] and [[IBM System/360 Model 40|Model 40]] had 8-bit data paths in the arithmetic logical unit, so that a 32-bit add required four cycles, one for each 8 bits of the operands, and, even though the [[Motorola 68000 series]] instruction set was a 32-bit instruction set, the [[Motorola 68000]] and [[Motorola 68010]] had 16-bit data paths in the arithmetic logical unit, so that a 32-bit add required two cycles.

To gain some of the advantages afforded by both lower and higher bit lengths, many [[instruction set architecture|instruction sets]] have different bit widths for integer and floating-point data, allowing CPUs implementing that instruction set to have different bit widths for different portions of the device. For example, the IBM [[System/360]] instruction set was primarily 32 bit, but supported 64-bit [[floating-point arithmetic|floating-point]] values to facilitate greater accuracy and range in floating-point numbers.<ref name="amdahl1964" /> The System/360 Model 65 had an 8-bit adder for decimal and fixed-point binary arithmetic and a 60-bit adder for floating-point arithmetic.<ref>{{cite book|url=http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6884-3_360-65_funcChar.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.bitsavers.org/pdf/ibm/360/functional_characteristics/A22-6884-3_360-65_funcChar.pdf |archive-date=2022-10-09 |url-status=live|title=IBM System/360 Model 65 Functional Characteristics|date=September 1968|publisher=[[IBM]]|pages=8–9|id=A22-6884-3}}</ref> Many later CPU designs use similar mixed bit width, especially when the processor is meant for general-purpose use where a reasonable balance of integer and floating-point capability is required.

===Parallelism===
{{Main|Parallel computing}}
[[File:Nopipeline.png|thumb|upright=2|Model of a subscalar CPU, in which it takes fifteen clock cycles to complete three instructions]]

The description of the basic operation of a CPU offered in the previous section describes the simplest form that a CPU can take. This type of CPU, usually referred to as ''subscalar'', operates on and executes one instruction on one or two pieces of data at a time, that is less than one [[Instructions per cycle|instruction per clock cycle]] ({{nowrap|IPC < 1}}).

This process gives rise to an inherent inefficiency in subscalar CPUs. Since only one instruction is executed at a time, the entire CPU must wait for that instruction to complete before proceeding to the next instruction. As a result, the subscalar CPU gets "hung up" on instructions which take more than one clock cycle to complete execution. Even adding a second [[execution unit]] (see below) does not improve performance much; rather than one pathway being hung up, now two pathways are hung up and the number of unused transistors is increased. This design, wherein the CPU's execution resources can operate on only one instruction at a time, can only possibly reach ''scalar'' performance (one instruction per clock cycle, {{nowrap|1=IPC = 1}}). However, the performance is nearly always subscalar (less than one instruction per clock cycle, {{nowrap|IPC < 1}}).

Attempts to achieve scalar and better performance have resulted in a variety of design methodologies that cause the CPU to behave less linearly and more in parallel. When referring to parallelism in CPUs, two terms are generally used to classify these design techniques:
* ''[[instruction-level parallelism]]'' (ILP), which seeks to increase the rate at which instructions are executed within a CPU (that is, to increase the use of on-die execution resources);
* ''[[task-level parallelism]]'' (TLP), which purposes to increase the number of [[Thread (computing)|threads]] or [[Process (computing)|processes]] that a CPU can execute simultaneously.

Each methodology differs both in the ways in which they are implemented, as well as the relative effectiveness they afford in increasing the CPU's performance for an application.{{Efn|Neither [[Instruction-level parallelism|ILP]] nor [[Task-level parallelism|TLP]] is inherently superior over the other; they are simply different means by which to increase CPU parallelism. As such, they both have advantages and disadvantages, which are often determined by the type of software that the processor is intended to run. High-TLP CPUs are often used in applications that lend themselves well to being split up into numerous smaller applications, so-called "[[embarrassingly parallel]] problems". Frequently, a computational problem that can be solved quickly with high TLP design strategies like [[symmetric multiprocessing]] takes significantly more time on high ILP devices like superscalar CPUs, and vice versa.}}

====Instruction-level parallelism====
{{Main|Instruction-level parallelism}}
[[File:Fivestagespipeline.png|thumb|left|upright=1.5|Basic five-stage pipeline. In the best case scenario, this pipeline can sustain a completion rate of one instruction per clock cycle.]]

One of the simplest methods for increased parallelism is to begin the first steps of instruction fetching and decoding before the prior instruction finishes executing. This is a technique known as [[instruction pipelining]], and is used in almost all modern general-purpose CPUs. Pipelining allows multiple instructions to be executed at a time by breaking the execution pathway into discrete stages. This separation can be compared to an assembly line, in which an instruction is made more complete at each stage until it exits the execution pipeline and is retired.

Pipelining does, however, introduce the possibility for a situation where the result of the previous operation is needed to complete the next operation; a condition often termed data dependency conflict. Therefore, pipelined processors must check for these sorts of conditions and delay a portion of the pipeline if necessary. A pipelined processor can become very nearly scalar, inhibited only by pipeline stalls (an instruction spending more than one clock cycle in a stage).

[[File:Superscalarpipeline.svg|thumb|upright=1.5|A simple superscalar pipeline. By fetching and dispatching two instructions at a time, a maximum of two instructions per clock cycle can be completed.]]

Improvements in instruction pipelining led to further decreases in the idle time of CPU components. Designs that are said to be superscalar include a long instruction pipeline and multiple identical [[execution unit]]s, such as [[load–store unit]]s, [[arithmetic–logic unit]]s, [[floating-point unit]]s and [[address generation unit]]s.<ref>{{cite web |last=Huynh |first=Jack |year=2003 |title=The AMD Athlon XP Processor with 512KB L2 Cache |url=http://courses.ece.uiuc.edu/ece512/Papers/Athlon.pdf |url-status=dead |archive-url=https://web.archive.org/web/20071128061217/http://courses.ece.uiuc.edu/ece512/Papers/Athlon.pdf |archive-date=2007-11-28 |access-date=2007-10-06 |publisher=University of Illinois |pages=6–11 |publication-place=Urbana–Champaign, Illinois}}</ref> In a superscalar pipeline, instructions are read and passed to a dispatcher, which decides whether or not the instructions can be executed in parallel (simultaneously). If so, they are dispatched to execution units, resulting in their simultaneous execution. In general, the number of instructions that a superscalar CPU will complete in a cycle is dependent on the number of instructions it is able to dispatch simultaneously to execution units.

Most of the difficulty in the design of a superscalar CPU architecture lies in creating an effective dispatcher. The dispatcher needs to be able to quickly determine whether instructions can be executed in parallel, as well as dispatch them in such a way as to keep as many execution units busy as possible. This requires that the instruction pipeline is filled as often as possible and requires significant amounts of [[CPU cache]]. It also makes [[Hazard (computer architecture)|hazard]]-avoiding techniques like [[branch prediction]], [[speculative execution]], [[register renaming]], [[out-of-order execution]] and [[transactional memory]] crucial to maintaining high levels of performance. By attempting to predict which branch (or path) a conditional instruction will take, the CPU can minimize the number of times that the entire pipeline must wait until a conditional instruction is completed. Speculative execution often provides modest performance increases by executing portions of code that may not be needed after a conditional operation completes. Out-of-order execution somewhat rearranges the order in which instructions are executed to reduce delays due to data dependencies. Also in case of [[Single instruction, multiple data|single instruction stream, multiple data stream]], a case when a lot of data from the same type has to be processed, modern processors can disable parts of the pipeline so that when a single instruction is executed many times, the CPU skips the fetch and decode phases and thus greatly increases performance on certain occasions, especially in highly monotonous program engines such as video creation software and photo processing.

When a fraction of the CPU is superscalar, the part that is not suffers a performance penalty due to scheduling stalls. The Intel [[P5 (microarchitecture)|P5]] [[Pentium]] had two superscalar ALUs which could accept one instruction per clock cycle each, but its FPU could not. Thus the P5 was integer superscalar but not floating point superscalar. Intel's successor to the P5 architecture, [[P6 (microarchitecture)|P6]], added superscalar abilities to its floating-point features.

Simple pipelining and superscalar design increase a CPU's ILP by allowing it to execute instructions at rates surpassing one instruction per clock cycle. Most modern CPU designs are at least somewhat superscalar, and nearly all general purpose CPUs designed in the last decade are superscalar. In later years some of the emphasis in designing high-ILP computers has been moved out of the CPU's hardware and into its software interface, or [[instruction set architecture]] (ISA). The strategy of the [[very long instruction word]] (VLIW) causes some ILP to become implied directly by the software, reducing the CPU's work in boosting ILP and thereby reducing design complexity.

====Task-level parallelism====
{{Main|Multithreading (computer architecture)|l1=Multithreading|Multi-core processor}}
Another strategy of achieving performance is to execute multiple [[Thread (computing)|threads]] or [[Process (computing)|processes]] in parallel. This area of research is known as [[parallel computing]].<ref>{{cite book |last1=Gottlieb |first1=Allan |url=http://dl.acm.org/citation.cfm?id=160438 |title=Highly parallel computing |last2=Almasi |first2=George S. |publisher=Benjamin/Cummings |year=1989 |isbn=978-0-8053-0177-9 |location=Redwood City, California |language=en-us |access-date=2016-04-25 |archive-url=https://web.archive.org/web/20181107043726/https://dl.acm.org/citation.cfm?id=160438 |archive-date=2018-11-07 |url-status=live}}</ref> In [[Flynn's taxonomy]], this strategy is known as [[Multiple instruction, multiple data|multiple instruction stream, multiple data stream]] (MIMD).<ref>{{Cite journal|last1=Flynn|first1=M. J. |s2cid=18573685 |author-link1=Michael J. Flynn|doi=10.1109/TC.1972.5009071|title=Some Computer Organizations and Their Effectiveness|journal=[[IEEE Transactions on Computers]]|volume=C-21|issue=9| pages=948–960| date=September 1972 |bibcode=1972ITCmp.100..948F }}</ref>

One technology used for this purpose is [[multiprocessing]] (MP).<ref>{{cite journal |last1=Lu |first1=N.-P. |last2=Chung |first2=C.-P. |year=1998 |title=Parallelism exploitation in superscalar multiprocessing |url=https://digital-library.theiet.org/doi/10.1049/ip-cdt%3A19981955 |journal=IEE Proceedings - Computers and Digital Techniques |volume=145 |issue=4 |pages=255 |doi=10.1049/ip-cdt:19981955|doi-broken-date=11 July 2025 |url-access=subscription }}</ref> The initial type of this technology is known as [[symmetric multiprocessing]] (SMP), where a small number of CPUs share a coherent view of their memory system. In this scheme, each CPU has additional hardware to maintain a constantly up-to-date view of memory. By avoiding stale views of memory, the CPUs can cooperate on the same program and programs can migrate from one CPU to another. To increase the number of cooperating CPUs beyond a handful, schemes such as [[non-uniform memory access]] (NUMA) and [[directory-based coherence protocols]] were introduced in the 1990s. SMP systems are limited to a small number of CPUs while NUMA systems have been built with thousands of processors. Initially, multiprocessing was built using multiple discrete CPUs and boards to implement the interconnect between the processors. When the processors and their interconnect are all implemented on a single chip, the technology is known as chip-level multiprocessing (CMP) and the single chip as a [[multi-core processor]].

It was later recognized that finer-grain parallelism existed with a single program. A single program might have several threads (or functions) that could be executed separately or in parallel. Some of the earliest examples of this technology implemented [[input/output]] processing such as [[direct memory access]] as a separate thread from the computation thread. A more general approach to this technology was introduced in the 1970s when systems were designed to run multiple computation threads in parallel. This technology is known as [[Multithreading (computer architecture)|multi-threading]] (MT). The approach is considered more cost-effective than multiprocessing, as only a small number of components within a CPU are replicated to support MT as opposed to the entire CPU in the case of MP. In MT, the execution units and the memory system including the caches are shared among multiple threads. The downside of MT is that the hardware support for multithreading is more visible to software than that of MP and thus supervisor software like operating systems have to undergo larger changes to support MT. One type of MT that was implemented is known as [[temporal multithreading]], where one thread is executed until it is stalled waiting for data to return from external memory. In this scheme, the CPU would then quickly context switch to another thread which is ready to run, the switch often done in one CPU clock cycle, such as the [[UltraSPARC T1]]. Another type of MT is [[simultaneous multithreading]], where instructions from multiple threads are executed in parallel within one CPU clock cycle.

For several decades from the 1970s to early 2000s, the focus in designing high performance general purpose CPUs was largely on achieving high ILP through technologies such as pipelining, caches, superscalar execution, out-of-order execution, etc. This trend culminated in large, power-hungry CPUs such as the Intel [[Pentium 4]]. By the early 2000s, CPU designers were thwarted from achieving higher performance from ILP techniques due to the growing disparity between CPU operating frequencies and main memory operating frequencies as well as escalating CPU power dissipation owing to more esoteric ILP techniques.

CPU designers then borrowed ideas from commercial computing markets such as [[transaction processing]], where the aggregate performance of multiple programs, also known as [[throughput]] computing, was more important than the performance of a single thread or process.

This reversal of emphasis is evidenced by the proliferation of dual and more core processor designs and notably, Intel's newer designs resembling its less superscalar [[P6 (microarchitecture)|P6]] architecture. Late designs in several processor families feature chip-level multiprocessing, including the [[x86-64]] [[Opteron]] and [[Athlon 64 X2]], the [[SPARC]] [[UltraSPARC T1]], IBM [[POWER4]] and [[POWER5]], as well as several [[video game console]] CPUs like the [[Xbox 360]]'s triple-core PowerPC design, and the [[PlayStation 3]]'s 7-core [[Cell (microprocessor)|Cell microprocessor]].

====Data parallelism====
{{Main|Vector processor|SIMD}}
A less common but increasingly important paradigm of processors (and indeed, computing in general) deals with data parallelism. The processors discussed earlier are all referred to as some type of scalar device.{{Efn|Earlier the term ''scalar'' was used to compare the IPC count afforded by various ILP methods. Here the term is used in the strictly mathematical sense to contrast with vectors. See [[scalar (mathematics)]] and [[vector (geometric)]].}} As the name implies, vector processors deal with multiple pieces of data in the context of one instruction. This contrasts with scalar processors, which deal with one piece of data for every instruction. Using [[Flynn's taxonomy]], these two schemes of dealing with data are generally referred to as ''single instruction'' stream, ''multiple data'' stream ([[Single instruction, multiple data|SIMD]]) and ''single instruction'' stream, ''single data'' stream ([[Single instruction, single data|SISD]]), respectively. The great utility in creating processors that deal with vectors of data lies in optimizing tasks that tend to require the same operation (for example, a sum or a [[dot product]]) to be performed on a large set of data. Some classic examples of these types of tasks include [[multimedia]] applications (images, video and sound), as well as many types of [[Scientific computing|scientific]] and engineering tasks. Whereas a scalar processor must complete the entire process of fetching, decoding and executing each instruction and value in a set of data, a vector processor can perform a single operation on a comparatively large set of data with one instruction. This is only possible when the application tends to require many steps which apply one operation to a large set of data.

Most early vector processors, such as the [[Cray-1]], were associated almost exclusively with scientific research and [[cryptography]] applications. However, as multimedia has largely shifted to digital media, the need for some form of SIMD in general-purpose processors has become significant. Shortly after inclusion of [[floating-point unit]]s started to become commonplace in general-purpose processors, specifications for and implementations of SIMD execution units also began to appear for general-purpose processors in the mid-1990s. Some of these early SIMD specifications – like HP's [[Multimedia Acceleration eXtensions]] (MAX) and Intel's [[MMX (instruction set)|MMX]] – were integer-only. This proved to be a significant impediment for some software developers, since many of the applications that benefit from SIMD primarily deal with [[floating-point arithmetic|floating-point]] numbers. Progressively, developers refined and remade these early designs into some of the common modern SIMD specifications, which are usually associated with one [[instruction set architecture]] (ISA). Some notable modern examples include Intel's [[Streaming SIMD Extensions]] (SSE) and the PowerPC-related [[AltiVec]] (also known as VMX).{{Efn|Although SSE/SSE2/SSE3 have superseded MMX in Intel's general-purpose processors, later [[IA-32]] designs still support MMX. This is usually done by providing most of the MMX functionality with the same hardware that supports the much more expansive SSE instruction sets.}}

===Hardware performance counter===
{{Main|Hardware performance counter}}
Many modern architectures (including embedded ones) often include [[hardware performance counter]]s (HPC), which enables low-level (instruction-level) collection, [[Benchmark (computing)|benchmarking]], debugging or analysis of running software metrics.<ref>{{Cite conference|last1=Uhsadel|first1=Leif|last2=Georges|first2=Andy|last3=Verbauwhede|first3=Ingrid|date=August 2008|title=Exploiting Hardware Performance Counters|conference=2008 5th Workshop on Fault Diagnosis and Tolerance in Cryptography|pages=59–67|doi=10.1109/FDTC.2008.19|isbn=978-0-7695-3314-8|s2cid=1897883}}</ref><ref>{{Cite conference|last=Rohou|first=Erven|date=September 2012|title=Tiptop: Hardware Performance Counters for the Masses|conference=2012 41st International Conference on Parallel Processing Workshops|pages=404–413|doi=10.1109/ICPPW.2012.58|isbn=978-1-4673-2509-7|s2cid=16160098}}</ref> HPC may also be used to discover and analyze unusual or suspicious activity of the software, such as [[return-oriented programming]] (ROP) or [[sigreturn-oriented programming]] (SROP) exploits etc.<ref>{{Cite web|last1=Herath|first1=Nishad|last2=Fogh|first2=Anders|date=2015|title=CPU Hardware Performance Counters for Security|url=https://www.blackhat.com/docs/us-15/materials/us-15-Herath-These-Are-Not-Your-Grand-Daddys-CPU-Performance-Counters-CPU-Hardware-Performance-Counters-For-Security.pdf|url-status=live|publisher=Black Hat|location=USA|archive-url=https://web.archive.org/web/20150905090843/https://www.blackhat.com/docs/us-15/materials/us-15-Herath-These-Are-Not-Your-Grand-Daddys-CPU-Performance-Counters-CPU-Hardware-Performance-Counters-For-Security.pdf |archive-date=2015-09-05 }}</ref> This is usually done by software-security teams to assess and find malicious binary programs.<ref>{{Cite book |last=Jøsang |first=Audun |url=https://books.google.com/books?id=-kFmDwAAQBAJ&dq=usually+done+by+software-security+teams+to+assess+and+find+malicious+binary+programs.&pg=PA96 |title=ECCWS 2018 17th European Conference on Cyber Warfare and Security V2 |date=2018-06-21 |publisher=Academic Conferences and publishing limited |isbn=978-1-911218-86-9 |language=en}}</ref>

Many major vendors (such as [[IBM]], [[Intel]], [[AMD]], and [[Arm Holdings|Arm]]) provide software interfaces (usually written in C/C++) that can be used to collect data from the CPU's [[hardware register|register]]s in order to get metrics.<ref>{{Citation|last=DeRose|first=Luiz A.|title=The Hardware Performance Monitor Toolkit|date=2001|url=http://link.springer.com/10.1007/3-540-44681-8_19|work=Euro-Par 2001 Parallel Processing|series=Lecture Notes in Computer Science|volume=2150|pages=122–132|editor-last=Sakellariou|editor-first=Rizos|place=Berlin, Heidelberg|publisher=Springer Berlin Heidelberg|language=en|doi=10.1007/3-540-44681-8_19|isbn=978-3-540-42495-6|access-date=2021-12-30|editor2-last=Gurd|editor2-first=John|editor3-last=Freeman|editor3-first=Len|editor4-last=Keane|editor4-first=John|archive-date=2023-03-01|archive-url=https://web.archive.org/web/20230301143920/https://link.springer.com/chapter/10.1007/3-540-44681-8_19|url-status=live|url-access=subscription}}</ref> Operating system vendors also provide software like <code>[[Perf (Linux)|perf]]</code> (Linux) to record, [[Benchmark (computing)|benchmark]], or [[Tracing (software)|trace]] CPU events running kernels and applications.

Hardware counters provide a low-overhead method for collecting comprehensive performance metrics related to a CPU's core elements (functional units, caches, main memory, etc.) – a significant advantage over software profilers.<ref>{{Cite web |title=TOWARDS A BENCHMARK FOR PERFORMANCE AND POWER CONSUMPTION EVALUATION OF PARALLEL PROGRAMMING INTERFACES |url=https://dspace.unipampa.edu.br/bitstream/riu/4136/1/Adriano%20Marques%20Garcia%20-%202019.pdf |access-date=2024-03-15 |language=vi}}</ref> Additionally, they generally eliminate the need to modify the underlying source code of a program.<ref>{{Cite book |last1=Chawdhury |first1=Tarun Kumar |url=https://books.google.com/books?id=8f34EAAAQBAJ&dq=benefit+of+using+them+is+that+no+source+code+modifications+are+needed+in+general.&pg=PA117 |title=Mastering Secure Java Applications: Navigating security in cloud and microservices for Java |last2=Banerjee |first2=Joyanta |last3=Gupta |first3=Vipul |last4=Poddar |first4=Debopam |date=2024-03-04 |publisher=BPB Publications |isbn=978-93-5551-884-2 |pages=117 |edition=English |language=en}}</ref> Because hardware designs differ between architectures, the specific types and interpretations of hardware counters will also change.

==Privileged modes==
Most modern CPUs have [[Supervisor mode|privileged modes]] to support operating systems and virtualization.

[[Cloud computing]] can use virtualization to provide a '''virtual central processing unit'''<ref>
{{cite book
| last1 = Anjum
| first1 = Bushra
| last2 = Perros
| first2 = Harry G.
| chapter = 1: Partitioning the End-to-End QoS Budget to Domains
| title = Bandwidth Allocation for Video Under Quality of Service Constraints
| chapter-url = https://books.google.com/books?id=3r3eBQAAQBAJ
| series = Focus Series
| publisher = John Wiley & Sons
| date = 2015
| page = 3
| isbn = 9781848217461
| access-date = 2016-09-21
| quote = [...] in cloud computing where multiple software components run in a virtual environment on the same blade, one component per virtual machine (VM). Each VM is allocated a virtual central processing unit [...] which is a fraction of the blade's CPU.
}}
</ref> ('''vCPU''') for separate users;<ref>
{{cite book
| last1 = Fifield
| first1 = Tom
| last2 = Fleming
| first2 = Diane
| last3 = Gentle
| first3 = Anne
| last4 = Hochstein
| first4 = Lorin
| last5 = Proulx
| first5 = Jonathan
| last6 = Toews
| first6 = Everett
| last7 = Topjian
| first7 = Joe
| chapter = Glossary
| title = OpenStack Operations Guide
| chapter-url = https://books.google.com/books?id=jQ5pAwAAQBAJ
| location = Beijing
| publisher = O'Reilly Media, Inc.
| date = 2014
| page = 286
| isbn = 9781491906309
| access-date = 2016-09-20
| quote = Virtual Central Processing Unit (vCPU)[:] Subdivides physical CPUs. Instances can then use those divisions.
}}
</ref>
vCPU is not to be confused with a [[virtual private server]] (VPS).

A host is the virtual equivalent of a physical machine, on which a virtual system is operating.<ref>{{Cite web |date=2006 |title=VMware Infrastructure Architecture Overview – White Paper |url=https://www.vmware.com/pdf/vi_architecture_wp.pdf |url-status=dead |archive-url=https://ghostarchive.org/archive/20221009/https://www.vmware.com/pdf/vi_architecture_wp.pdf |archive-date=2022-10-09 |website=VMware}}</ref> When there are several physical machines operating in tandem and managed as a whole, the grouped computing and memory resources form a [[Computer cluster|cluster]]. In some systems, it is possible to dynamically add and remove from a cluster. Resources available at a host and cluster level can be partitioned into [[Pool (computer science)|resources pools]] with fine [[Granularity (parallel computing)|granularity]].

=={{anchor|PCM}}Performance==
{{further|Computer performance|Benchmark (computing)}}
The ''performance'' or ''speed'' of a processor depends on, among many other factors, the clock rate (generally given in multiples of [[hertz]]) and the instructions per clock (IPC), which together are the factors for the [[instructions per second]] (IPS) that the CPU can perform.<ref name="Freq">{{Cite web
 | title = CPU Frequency
 | work = CPU World Glossary
 | publisher = CPU World
 | date = 25 March 2008
 | url = http://www.cpu-world.com/Glossary/C/CPU_Frequency.html
 | access-date = 1 January 2010
 | archive-date = 9 February 2010
 | archive-url = https://web.archive.org/web/20100209041126/http://www.cpu-world.com/Glossary/C/CPU_Frequency.html
 | url-status = live
 }}</ref>
Many reported IPS values have represented "peak" execution rates on artificial instruction sequences with few branches, whereas realistic workloads consist of a mix of instructions and applications, some of which take longer to execute than others. The performance of the [[memory hierarchy]] also greatly affects processor performance, an issue barely considered in IPS calculations. Because of these problems, various standardized tests, often called [[benchmark (computing)|"benchmarks"]] for this purpose{{snd}} such as [[SPECint]]{{snd}} have been developed to attempt to measure the real effective performance in commonly used applications.

Processing performance of computers is increased by using [[multi-core processor]]s, which essentially is plugging two or more individual processors (called ''cores'' in this sense) into one integrated circuit.<ref name="tt">{{Cite web
 | title = What is (a) multi-core processor?
 | work = Data Center Definitions
 | publisher = SearchDataCenter.com
 | url = http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html
 | access-date = 8 August 2016
 | archive-date = 5 August 2010
 | archive-url = https://web.archive.org/web/20100805052158/http://searchdatacenter.techtarget.com/sDefinition/0,,sid80_gci1015740,00.html
 | url-status = dead
 }}</ref> Ideally, a dual core processor would be nearly twice as powerful as a single core processor. In practice, the performance gain is far smaller, only about 50%, due to imperfect software algorithms and implementation.<ref>{{cite news|url=https://techspirited.com/quad-core-vs-dual-core|title=Quad Core Vs. Dual Core|newspaper=Tech Spirited |date=8 April 2010|access-date=7 November 2019|archive-date=4 July 2019|archive-url=https://web.archive.org/web/20190704093754/https://techspirited.com/quad-core-vs-dual-core|url-status=live |author1=Mlblevins }}</ref> Increasing the number of cores in a processor (i.e. dual-core, quad-core, etc.) increases the workload that can be handled. This means that the processor can now handle numerous asynchronous events, interrupts, etc. which can take a toll on the CPU when overwhelmed. These cores can be thought of as different floors in a processing plant, with each floor handling a different task. Sometimes, these cores will handle the same tasks as cores adjacent to them if a single core is not enough to handle the information. Multi-core CPUs enhance a computer's ability to run several tasks simultaneously by providing additional processing power. However, the increase in speed is not directly proportional to the number of cores added. This is because the cores need to interact through specific channels, and this inter-core communication consumes a portion of the available processing speed.<ref>{{Cite web |last=Marcin |first=Wieclaw |date=12 January 2022 |title=Factors Affecting Multi-Core Processors Performance |url=https://pcsite.co.uk/factors-affecting-multi-core-central-processing-unit-performance/ |website=PcSite}}</ref>

Due to specific capabilities of modern CPUs, such as [[simultaneous multithreading]] and [[uncore]], which involve sharing of actual CPU resources while aiming at increased utilization, monitoring performance levels and hardware use gradually became a more complex task.<ref>{{cite web|last1=Tegtmeier|first1=Martin|title=CPU utilization of multi-threaded architectures explained|url=https://blogs.oracle.com/solaris/post/cpu-utilization-of-multi-threaded-architectures-explained|publisher=Oracle|access-date=July 17, 2022|archive-date=July 18, 2022|archive-url=https://web.archive.org/web/20220718000821/https://blogs.oracle.com/solaris/post/cpu-utilization-of-multi-threaded-architectures-explained|url-status=live}}</ref> As a response, some CPUs implement additional hardware logic that monitors actual use of various parts of a CPU and provides various counters accessible to software; an example is Intel's ''Performance Counter Monitor'' technology.<ref name="intel-pcm">{{cite web |last1=Willhalm |first1=Thomas |last2=Dementiev |first2=Roman |last3=Fay |first3=Patrick |date=December 18, 2014 |title=Intel Performance Counter Monitor – A better way to measure CPU utilization |url=https://software.intel.com/en-us/articles/intel-performance-counter-monitor-a-better-way-to-measure-cpu-utilization |url-status=live |archive-url=https://web.archive.org/web/20170222150312/https://software.intel.com/en-us/articles/intel-performance-counter-monitor-a-better-way-to-measure-cpu-utilization |archive-date=February 22, 2017 |access-date=February 17, 2015 |website=software.intel.com}}</ref>

==Overclocking==
[[File:RTX 4070 Ti SUPER im Vergleich mit anderen RTX 40er-Karten (极客湾Geekerwan) 005.png|thumb|Nvidia-Asus Tuf GPUs that have OG (original) and OC (overclockable) on them]]
{{Main|Overclocking}}
[[Overclocking]] is a process of increasing the [[clock rate|clock speed]] of a CPU (and other components) beyond their rated speeds. Increasing a component's clock rate causes it to perform more operations per second.<ref>{{Cite conference |last1=Thomas |first1=Diljo |last2=Shanmugasundaram |first2=M |title=A Survey on Different Overclocking Methods |date=March 2018 |conference=2018 Second International Conference on Electronics, Communication and Aerospace Technology (ICECA) |pages=1588–1592 |doi=10.1109/ICECA.2018.8474921 |isbn=978-1-5386-0965-1 }}</ref> Overclocking might increase CPU temperature and cause it to [[Overheating (electricity)|overheat]], so most users do not overclock and leave the clock speed unchanged. Some versions of components (such as [[Intel Core|Intel's U version of its CPUs]] or [[Nvidia RTX|Nvidia's OG]] GPUs) do not allow overclocking.

==See also==
{{portal|Technology}}
{{Div col|colwidth=20em}}
* [[Addressing mode]]
* [[AMD Accelerated Processing Unit]]
* [[Complex instruction set computer]]
* [[Bus (computing)|Computer bus]]
* [[Computer engineering]]
* [[CPU core voltage]]
* [[CPU socket]]
* [[Data processing unit]]
* [[Digital signal processor]]
* [[Graphics processing unit]]
* [[Comparison of instruction set architectures]]
* [[Protection ring]]
* [[Reduced instruction set computer]]
* [[Stream processing]]
* [[True Performance Index]]
* [[Tensor Processing Unit]]
* [[Wait state]]
{{Div col end}}

==Notes==
{{notelist|30em}}

==References==
{{reflist|30em}}

==External links==
{{Commons category|Central processing units}}
{{Wikiversity|Introduction to Computers/Processor}}
* {{HowStuffWorks|microprocessor|How Microprocessors Work}}.
* [https://spectrum.ieee.org/25-microchips-that-shook-the-world 25 Microchips that shook the world] – an article by the [[Institute of Electrical and Electronics Engineers]].

{{CPU technologies}}
{{Basic computer components}}
{{Digital systems}}
{{Electronic components}}

[[Category:Central processing unit| ]]
[[Category:Digital electronics]]
[[Category:Electronic design]]
[[Category:Electronic design automation]]