View source for Duron

{{For|the brand of hardboard|Masonite}}
{{about|the microprocessor product line|the painting company|Duron Paint|the municipality|Durón}}
{{no footnotes|date=January 2013}}
{{short description|Series of CPUs by AMD}}
{{Infobox CPU
| name           = Duron
| image          = AMD Duron D600AUT1B.jpg
| caption        = AMD Duron "Spitfire" 600MHz CPU
| produced-start = June 19, 2000
| produced-end   = July 28, 2004
| slowest        = 600
| fastest        = 1.8
| slow-unit      = MHz
| fsb-slowest    = 200
| fsb-fastest    = 266
| fsb-slow-unit  = MT/s
| fsb-fast-unit  = MT/s
| size-from      = 180nm
| size-to        = 130nm
| manuf1         = [[AMD]]
| core1          = Spitfire
| core2          = Morgan
| core3          = Appalbred (aka Applebred)
| sock1          = [[Socket A]]
| arch           = x86
| microarch      = [[Athlon#Athlon Thunderbird|Athlon]]
| predecessor    = [[AMD K6-2|K6-2]]
| successor      = [[Sempron]]
|instructions=[[MMX (instruction set)|MMX]], [[3DNow!]], [[Streaming SIMD Extensions|SSE]] (since Morgan)|core4=Camaro}}

[[Image:AMD Duron Processor Logo.svg|100px|right|Duron logo]]

'''Duron''' is a line of budget [[x86]]-compatible microprocessors manufactured by [[Advanced Micro Devices|AMD]] and released on June 19, 2000. Duron was intended to be a lower-cost offering to complement AMD's then mainstream performance [[Athlon]] processor line, and it also competed with rival chipmaker [[Intel]]'s [[Pentium III]] and [[Celeron]] processor offerings. The Duron brand name was retired in 2004, succeeded by AMD's [[Sempron]] line of processors as their budget offering.

==Performance==
The original Duron processors were derived from AMD's mainstream ''Athlon'' [[Athlon#Athlon Thunderbird|Thunderbird]] processors, the primary difference being a reduction in L2 cache size to 64&nbsp;[[Binary prefix|KB]] from the Athlon's 256&nbsp;KB.<ref>{{Cite web |date=2010-03-28 |title=AMD Duron - (Page 2 of 3) - The Processor Emporium (UK) |url=http://www.zen26266.zen.co.uk/Duron-2.htm |archive-url=https://web.archive.org/web/20100328014838/http://www.zen26266.zen.co.uk/Duron-2.htm |archive-date=2010-03-28 |access-date=2024-10-10 |website=Processor Emporium}}</ref> This was a relatively severe reduction, making it even smaller than the 128&nbsp;KB L2 available on Intel's competing budget [[Celeron]] line. However, the originating Thunderbird architecture already featured one of the largest L1 caches at 128&nbsp;KB (which was not reduced in the Duron) and also introduced AMD's switch to an exclusive cache design which effectively unified the L1 and L2 caches. Because of this, the Duron behaved as if it had a high speed 128&nbsp;KB cache combined with a somewhat slower 64&nbsp;KB segment giving an effective 192&nbsp;KB cache, versus the traditional inclusive cache design where the L2 cache had to store a duplicate of the data stored in the L1 cache. As a comparison the inclusive design of the Celeron effectively reduced the available size of the Level 2 cache by the size of the Level 1, which resulted in an effective size of 96&nbsp;KB (128-32) in contrast to the Duron's exclusive design (128+64=192).

Consequently, the Duron inherited the Thunderbird's reduction in sensitivity to L2 cache size, allowing AMD to make their L2 cache higher latency and lower bandwidth to lessen processor complexity and allow better manufacturing [[Semiconductor device fabrication#Device test|yields]] without incurring a significant performance loss. The net result was that the budget Duron "Spitfire" CPU was roughly only 10% slower than an equivalently clocked (and significantly more expensive) Athlon "Thunderbird".

==Compatibility==
The Duron line was pin-compatible and operated on the same [[motherboard]]s as the Athlon line, requiring only a BIOS update in most cases. The original Duron was introduced with a 100&nbsp;MHz (effectively 200&nbsp;MHz) [[front-side bus]]{{snd}} the same as the then current Socket A Athlons. Later with the introduction of motherboard chipsets offering higher FSB speeds of 133&nbsp;MHz (FSB 266) and AMD's matching introduction of Athlon "C" processors supporting this speed, the Duron initially retained the 100&nbsp;MHz FSB for purposes of [[market segmentation]]. Later Durons were given official support for 133&nbsp;MHz bus operation only after the Athlon XP was used to introduce 166/200&nbsp;MHz FSB (FSB 333/400) speeds.

==Revisions==
The original Duron, using the "Spitfire" core, was manufactured in 2000 and 2001 at speeds ranging from 600 to 950&nbsp;MHz. It was based on the 180&nbsp;nm "[[Athlon#Athlon Thunderbird|Thunderbird]]" Athlon core.

The second-generation Duron, the "Morgan" core, was sold in speed grades between 900 and 1300&nbsp;MHz, and was based on the 180&nbsp;nm "[[Athlon#Palomino|Palomino]]" Athlon XP core. As a result, it featured a few important enhancements, namely full Intel SSE support, enlarged TLBs, hardware data prefetch, and an integrated thermal diode. Like the "Palomino" core, "Morgan" was also expected to reduce heat dissipation; however in "Morgan"'s case this did not happen due to its increased core voltage.

A third-generation Duron, the "Appaloosa" core, was announced in the 2001-2002 AMD Processor Roadmap,<ref>{{cite web
|url=http://www.amd.com/us-en/Corporate/VirtualPressRoom/0%2C%2C51_104_608%2C00.html
|archive-url=https://web.archive.org/web/20011018151805/http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_608,00.html
|title=2001-2002 AMD Processor Roadmap
|author=Advanced Micro Devices
|date=2000
|archive-date=Oct 18, 2001
}}</ref> to enter production in 2002; this was to be manufactured with AMD's upcoming [[130&nbsp;nm process|130 nm process]]. Despite rumors of early limited circulation however, "Appaloosa"-based Durons never reached the market, and by the end of 2001, "Appaloosa" had been removed from the roadmap.<ref>{{cite web
|url=http://www.amd.com/us-en/Corporate/VirtualPressRoom/0%2C%2C51_104_608%2C00.html
|archive-url=https://web.archive.org/web/20021011050816/http://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_608,00.html
|title=2002-2003 AMD Processor Roadmap
|author=Advanced Micro Devices
|date=2001
|archive-date=Oct 11, 2002
}}</ref>

Instead of the canceled "Appaloosa" core, the Duron line eventually saw a final generation in 2003, in the form of the "Appalbred" core (later typically misspelled as "Applebred"), which was a 130&nbsp;nm [[Athlon#Thoroughbred|"Thoroughbred" Athlon XP]] with only 64&nbsp;KiB (¼) of L2 cache enabled. The name "Appalbred" was a [[portmanteau]] of "Appaloosa" and "Thoroughbred", much like the contemporary "Thorton" Athlon XP, a "Barton" with only 256&nbsp;KiB (½) of L2 cache enabled, was a portmanteau of "Thoroughbred" and "Barton". Neither "Appalbred" nor "Thorton" ever appeared on an official AMD processor roadmap.

In the years following its introduction and the withdrawal of the Duron line from the market, the spelling "Appalbred" gradually became replaced by the phonetically similar "Applebred", as "Appaloosa" and the etymology of "Appalbred" were mostly forgotten.

==Enthusiasts==
Duron was often a favorite of computer builders looking for performance while on a tight budget. In 2003, the "Appalbred" Duron was available in 1.4&nbsp;GHz, 1.6&nbsp;GHz and 1.8&nbsp;GHz grades, all on a 133&nbsp;MHz (FSB 266) bus. Enthusiast groups quickly discovered these Durons to be rebadged "Thoroughbred B" cores with 192&nbsp;KiB (¾) of L2 cache disabled and possibly defective. With a basic CPU OPGA package configuration modification, it was found that "Appalbred" Durons could be turned into "Thoroughbred B" Athlon XPs, with full 256&nbsp;KiB cache, with a very high success rate. However, this was only possible for a period of approximately 4 weeks, as shortly after "Appalbred" was released, AMD made changes to the OPGA package that made these configuration modifications ineffective.

==Features==
{{expand section|date=March 2023}}

==Duron core data==

===Spitfire (Model 3, 180 nm)===
[[File:KL AMD Duron Spitfire.jpg|thumb|right|"Spitfire" Duron, 600&nbsp;MHz]]
[[File:AMD@180nm@K7@Spitfire@Duron@D800AUT1B AKCA0041RPBW Stack-DSC03069-DSC03096 - ZS-retouched (26306172034).jpg|thumb|Die shot of a Spitfire Duron]]
* [[L1 cache]]: 64 + 64 [[kilobyte|KB]] (Data + Instructions)
* [[L2 cache]]: 64 KB, full speed
* [[MMX (instruction set)|MMX]], Extended MMX, [[3DNow!]], [[3DNow!|Extended 3DNow!]]
* [[Socket A]] (EV6)
* [[Front-side bus]]: 100&nbsp;MHz (200 MT/s)
* VCore: 1.50 [[Volts|V]] – 1.60 V
* First release: June 19, 2000
* [[Clock rate]]: 600–950&nbsp;MHz

===Morgan (Model 7, 180 nm)===
[[File:KL AMD Duron Morgan.jpg|thumb|right|"Morgan" Duron, 1.3&nbsp;GHz]]
[[File:AMD@180nm@K7@Morgan@Duron@DHD1200AMT1B AHLCA0151VPDW Stack-DSC05722-DSC05758 - ZS-DMap (27363293340).jpg|thumb|Die shot of a Morgan Duron]]
* [[L1 cache]]: 64 + 64 [[kilobyte|KB]] (Data + Instructions)
* [[L2 cache]]: 64 KB, full speed
* [[MMX (instruction set)|MMX]], Extended MMX, [[3DNow!]], [[3DNow!|Extended 3DNow!]], [[Streaming SIMD Extensions|SSE]]
* [[Socket A]] (EV6)
* [[Front-side bus]]: 100&nbsp;MHz (200 MT/s)
* VCore: 1.7-1.75 V
* First release: August 20, 2001
* [[Clock rate]]: 900–1300&nbsp;MHz

=== Camaro (Model 7, 180 nm) ===
* [[L1 cache]]: 64 + 64 [[kilobyte|KB]] (Data + Instructions)
* [[L2 cache]]: 64 KB, full speed
* [[MMX (instruction set)|MMX]], Extended MMX, [[3DNow!]], [[3DNow!|Extended 3DNow!]], [[Streaming SIMD Extensions|SSE]]
* [[Socket A]] (EV6)
* [[Front-side bus]]: 100&nbsp;MHz (200 MT/s)
* VCore: 1.50V
* First release: May 14, 2001
* [[Clock rate]]: 800–1300&nbsp;MHz

[[File:Mobile duron 850.jpg|alt="Camaro" Mobile Duron, 850MHz|thumb|"Camaro" Mobile Duron, 850MHz]]

===Appalbred aka Applebred (Model 8, 130 nm)===
[[File:Duron 1600 Applebred model A Front.jpg|thumb|right|"Appalbred" Duron, "A"-model, 1.6&nbsp;GHz]]
* [[L1 cache]]: 64 + 64 [[kilobyte|KB]] (Data + Instructions)
* [[L2 cache]]: 64 KB, full speed
* [[MMX (instruction set)|MMX]], Extended MMX, [[3DNow!]], [[3DNow!|Extended 3DNow!]], [[Streaming SIMD Extensions|SSE]]
* [[Socket A]] (EV6)
* [[Front-side bus]]: 133&nbsp;MHz (266 MT/s)
* VCore: 1.50 V
* First release: August 21, 2003
* [[Clock rate]]: 1400, 1600 or 1800&nbsp;MHz

==See also==
* [[List of AMD Duron microprocessors]]

==References==
<references />

== Further reading ==
* [http://cpu-museum.de/forum/viewtopic.php?p=4303#4303 "''cpu-museum.de'' New additions to the museum (Appalbred)"], by Christian "Grampa", January 7, 2004, retrieved January 9, 2006, {{webarchive |url=https://web.archive.org/web/20110718215204/http://cpu-museum.de/forum/viewtopic.php?p=4303#4303 |date=July 18, 2011 |title=Archived }}
* [https://web.archive.org/web/19991013102053/http://sandpile.org/impl/k7.htm "IA-32 implementation AMD K7 (inclusive on Slot A)"] by Sandpile.org, retrieved January 9, 2006
* [http://www.pcstats.com/releaseview.cfm?releaseID=237 "Press Release: AMD Athlon Processor Performance-Enhancing Cache Memory"] {{Webarchive|url=https://web.archive.org/web/20181110080419/http://www.pcstats.com/releaseview.cfm?releaseID=237 |date=2018-11-10 }} by AMD, June 4, 2000, retrieved January 13, 2006

==External links==
* [https://web.archive.org/web/20040818172809/http://www.anandtech.com/cpuchipsets/showdoc.aspx?i=1927 Budget CPU Shootout]{{snd}} Popular hardware review website Anandtech compares low priced CPUs
* [http://www.cpu-collection.de/?tn=0&l0=co&l1=AMD&l2=Duron cpu-collection.de] AMD Duron processor images and descriptions
* [https://web.archive.org/web/20110913013721/http://www.anandtech.com/show/1446/3 Updated CPU Cheatsheet - Seven Years of Covert CPU Operations]

{{AMD processors}}

[[Category:AMD x86 microprocessors]]
[[Category:Computer-related introductions in 2000]]