View source for GE 645

{{Short description|1960's Mainframe Computer}}
[[File:GE-645-mainframe-1968.png|thumb|GE-645 idealized configuration]]

The '''GE 645''' [[mainframe computer]] was a development of the [[GE 635]] for use in the [[Multics]] project. This was the first computer that implemented a configurable hardware protected memory system. It was designed to satisfy the requirements of [[Project MAC]] to develop a platform that would host their proposed next generation [[time-sharing]] operating system ([[Multics]]) and to meet the requirements of a theorized [[computer utility]].<ref name="Corbató">{{cite conference |last1=Corbató |first1=F. J. |last2=Vyssotsky |first2=V. A. |book-title=Proceedings of the November 30--December 1, 1965, fall joint computer conference, Part I on XX - AFIPS '65 (Fall, part I) |title=Introduction and overview of the multics system |date=30 November 1965 |pages=185–196 |doi=10.1145/1463891.1463912 |url=https://dl.acm.org/doi/10.1145/1463891.1463912 |publisher=Association for Computing Machinery|isbn=9781450378857 |s2cid=11197018 |url-access=subscription }}</ref> The system was the first truly [[symmetric multiprocessing]] machine to use [[virtual memory]], and it was also among the first machines to implement what is now known as a [[translation lookaside buffer]],<ref>{{cite journal|author=John Couleur|title=The Core of the Black Canyon Computer Corporation|journal=IEEE Annals of the History of Computing|volume=17|issue=4|pages=56–60|date=Winter 1995|doi=10.1109/85.477436|url=http://www.bitsavers.org/pdf/ge/history/Couleur_-_The_Core_of_the_Black_Canyon_Computer_Corporation_1995.pdf}}</ref><ref name=Glaser /><ref name=LSB0468 /> the foundational patent for which was granted to [[John Couleur]] and Edward Glaser.<ref>{{cite patent |country=US |number=3412382 |status=patent |title=Shared-access data processing system |invent1=COULEUR JOHN F|invent2=GLASER EDWARD L|assign1=Massachusetts Institute of Technology}}</ref> 

[[General Electric]] initially publicly announced the GE 645 at the [[Joint Computer Conference|Fall Joint Computer Conference]]<ref name="Corbató" /><ref name=Glaser /> in November 1965. At a subsequent press conference in December<ref>{{cite news |last1=Smith |first1=William D. |title=A New Computer Developed at G.E. |url=https://www.nytimes.com/1965/12/02/archives/a-new-computer-developed-at-ge-designed-to-enable-many-to-use-it-at.html |access-date=20 October 2023 |work=The New York Times |date=2 December 1965}}</ref><ref name="NAVYDCN">{{Cite journal |title=GE-645 Timesharing System |url=https://books.google.com/books?id=FdvcNdNZ8DgC&pg=RA1-PA5 |journal=Digital Computer Journal | date=1966 |publisher=Office of Naval Research - Mathematics Science Division |volume=18 |issue=2 |pages=5–6}}</ref> of that year it was announced that they would be working towards "broad commercial availability"<ref name="DOJ" /> of the system. However they would subsequently withdraw it from active marketing at the end of 1966.<ref name="DOJ">{{cite web |title=US vs IBM_Exhibit 14971 - Historical Narrative The 1960's |url=http://www.bitsavers.org/pdf/charlesRiverAssoc/US_vs_IBM_Exhibit_14971_part_2_Jul80.pdf |access-date=21 October 2023 |pages=434,510 }}</ref> In total at least 6 sites ran GE 645 systems in the period from 1967 to 1975.<ref name="sites">{{cite web |title=Multics Site Timeline |url=https://multicians.org/site-timeline.html |website=multicians.org |access-date=21 October 2023}}</ref>

==System configuration==
The basic system configuration consisted of a combination of 4 basic modules<ref name=LSB0468 /><ref>Kaisler (2020), ''op. cit., p.'' 274</ref> these were:
* Processor
* System Controller
* Generalized I/O Controller (GIOC)
* Extended Memory Unit (EMU)
[[File:US3525080-GE-645-01.png|thumb|right|US3525080 Patent showing GE-645]]

The System Controller Modules (SCM) effectively acted as the heart of the system. These were passive devices which was connected to each active device (Processor, GIOC, EMU) and provided the following:<ref name=LSB0468 /><ref>Kaisler (2020), ''op. cit., p.'' 275</ref>
* Core Memory - 1 microsecond memory in size capacities of 32K, 64K or 128K of 36-bit words. 
* Centralized point for forwarding control signals from one active module to another
* System Clock and the ability to issue interrupts to the processors.

Compared to the rest of the 600 series the 645 did not use the standard IOC's (input/output controllers) for I/O. Nor did it use the [[DATANET-30]] front end processor for communications. Instead both sets of functionality was combined into one unit called a GIOC (Generalized I/O Controller) which provided dedicated channels for both Peripheral (Disc/Tape) and Terminal I/O.<ref name="LSB0468" /><ref name="Ossanna">{{cite conference |last1=Ossanna |first1=J. F. |author-link1=Joe Ossanna |last2=Mikus |first2=L. E. |last3=Dunten |first3=S. D. |book-title=Proceedings of the November 30--December 1, 1965, fall joint computer conference, Part I on XX - AFIPS '65 (Fall, part I) |title=Communications and input/Output switching in a multiplex computing system |date=30 November 1965 |pages=231–241 |doi=10.1145/1463891.1463916 |url=https://doi.org/10.1145/1463891.1463916 |publisher=Association for Computing Machinery|s2cid=15847853 |url-access=subscription }}</ref> The GIOC acted as an Active Device and was directly connected to memory via dedicated links to each System Controller that was present in a specific configuration.

The Extended Memory Unit, though termed a [[Drum memory|drum]], was in reality a large fixed-head hard disk with one head per track,<ref name="LBP">{{cite web |last1=Van Vleck |first1=Tom |title=Low Bottle Pressure |url=https://multicians.org/low-bottle-pressure.html |website=multicians.org |access-date=29 October 2023}}</ref> this was a OEM product from [[Librascope]].<ref name="LBP" /><ref>{{cite web |title=The Librazette Vol. 10 No. 9 |url=https://librascopememories.com/1960_-_1969_files/6508_RayHandOCR.pdf |archive-url=https://web.archive.org/web/20220519225513mp_/https://librascopememories.com/1960_-_1969_files/6508_RayHandOCR.pdf |archive-date=19 May 2022 |url-status=dead}}</ref> The EMU consisted of 4,096 tracks providing 4MW (megawords) of storage (equivalent to 16MB). Each track had a dedicated read/write head, these were organised into groups of 16 "track sets" which are used to read/write a sector. A sector is the default unit of data allocation in the EMU and is made up of 80 words, of which 64 words are data and the remaining 16 were used as a guard band.<ref name="LSB0468" /> The average transfer rate between the EMU and memory was 470,000 words per second, all transfers were 72-bits (two words) wide, with it taking 6.7μs to transfer 4 words.<ref name="LSB0468" /> The unit had a rotational speed of 1,725 rpm, which ensured an average latency of 17.4 milliseconds.<ref name="LSB0468" />

{| class="wikitable sortable" 
|+ GE 645 System Configurations<ref name="LSB0468" />
|-
! Component !! Small !! Typical !! Large
|-
| '''System Configuration Console'''|| 1 || 1 || 2
|-
| '''Processor'''|| 1 || 2 || 4
|-
| '''GIOC'''|| 1 || 2 || 3
|-
| '''System Controllers'''
<small>Total Capacity (Words)</small>
|| 2
128K
| 4
256K
| 8
1024K
|-
| '''Extended Memory Unit'''
<small>Total capacity (Words)</small>
|| 1
4096K
| 1
4096K
| 1
4096K
|-
| '''Fixed disc (Words)'''|| 33M || 67M || 134M
|-
| '''Magnetic Cards (Words)'''|| -- || 113M || 226M
|-
| '''Magnetic tape handlers'''|| 4 || 16 || 32
|-
| '''Printers'''|| 2 || 4 || 6
|-
| '''Card Readers'''|| 1 || 2 || 3
|-
| '''Card Punches'''|| 1 || 2 || 2
|-
| '''Perforated Tape'''|| -- || 1 || 2
|-
| '''Channels for TTY's'''|| 64 || 192 || 384
|-
| '''Channels for voice-grade communication lines''' 
'''for remote terminals such as such as''' 

'''DATANET-760 / GE-115'''
| -- || 12 || 18
|}

==Architecture==
=== Processor Modes ===
The GE-645 has two modes of Instruction Execution (Master and Slave) inherited from the GE-635, however it also adds another dimension by having two modes of memory addressing (Absolute and Appending). When the process is executing in Absolute Mode addressing is limited to 2<sup>18</sup> words of memory and any instructions are executed in Master mode. In comparison Append Mode calculates the address using "Appending Words" with an address space of 2<sup>24</sup> words and with instruction execution occurring in either Master or Slave modes.<ref name="AH82-00" /> 
==== Slave Mode ====
By default this is normal mode that the processor should be executing in at any point in time. Nearly all instructions will run in this mode aside from a small set of privileged instructions which cannot execute in this mode. Execution of such instructions will trigger an illegal procedure fault, also the ability to inhibit interrupts (bit 28 of instruction word) is forbidden. Format of instruction addresses is via the Appending Process.
==== Master Mode ====
In this mode the processor can execute all instructions and is able to inhibit interrupts while doing so. Like in Slave mode the default form of address formation is via the Appending Process.
==== Absolute Mode ====
All instructions can be executed in this mode and full access is given to any privileged features of the hardware. Interrupts can be inhibited and instruction fetching is limited to a 2<sup>18</sup> (18-bit) absolute address thus restricting the processor to only been able to access the lower 256 KW of physical core memory. The processor will switch to this mode in the event of a fault or interrupt and will remain in it until it executes transfer instruction whose operand address has been obtained via the appending process.

==== Appending Mode ====
By default this is normal mode of Memory addressing, both Master and Slave modes normally operate in this mode. Indirect words and operands are accessed via Appending Mechanism via the process of placing a 1 in bit 29 of the executed instruction. Effective addresses are thus either added to a [[base address]], or the offset is linked to the base address. 
 
{| class="wikitable"
!Functions
! colspan="3" |Mode
|-
|
|Slave
|Master
|Absolute
|-
|Privileged instructions
|No
|Yes
|Yes
|-
|Interrupt inhibit (bit 28 of instruction word)
|No
|Yes
|Yes
|-
|Address for Instruction fetch
|Appending
|Appending
|Absolute
|-
|Address for Operand fetch
|Appending
|Appending
|Controlled by Bit 29 of instruction word
|-
|Restriction of access to other segments or pages
|Some
|Some (less restrictive than slave)
|N/A
|}

=== Functional Units ===
[[File:Ge645-processor.png|thumb|330x330px|GE 645 processor Functional Units]]The 645 processor was divided into four major functional units these were:<ref name="AH82-00" />

* '''Appending Unit:''' 
** Controls data I/O from memory
** Controls memory selection and interleave
** Carries out Memory appending
** Control fault recognition
** Does power on/off sequencing
* '''Associative Memory Unit:'''
** Consists of Associative Memory made up of 16 x 60-bit Registers<ref name="Schroeder">{{cite conference |last1=Schroeder |first1=Michael D. |book-title=Proceedings of the SIGOPS workshop on System performance evaluation|title=Performance of the GE-645 Associative Memory While Multics is in Operation |date=1971 |pages=227–245 |doi=10.1145/800024.808361 |url=https://dl.acm.org/doi/abs/10.1145/800024.808361 |publisher=Association for Computing Machinery|isbn=9781450373821 |s2cid=44850627 |url-access=subscription }}</ref>
** Registers point to most recently used segment (Segment Descriptor Word) or most recently used Page (Page Table)
** Performs the function of what would now be classed as a TLB.
* '''Control Unit:'''
** Performs all control functions
** Performs Address modification
** Controls the [[CPU modes|processor mode]] (master, slave, absolute)
** Interrupt recognition/handling
** Opcode decoding
* '''Operations Unit:'''
** Performs fractional and integer divisions and multiplications.
** Performs automatic alignment of floating-point numbers for addition and subtraction.
** Performs inverted divisions on floating-point numbers.
** Performs automatic normalization of floating-point resultants.
** Performs shifts.
** Performs indicator register loading and storing.
** Performs timer register loading and decrementing.

One of the key differences from the GE 635 was the addition of "appending unit" (APU) which was used to implement a hybrid "Paged Segmentation" model of [[virtual memory]]. The APU was also used to implement a [[single-level store]] which is one of the fundamental abstraction that Multics is built around. The instruction format was also extended with the previously unused bit 29 controlling whether the operand address of an instruction used an 18-bit format (bit 29 = 0) or one that was made up of a 3-bit Base Register address with a 15-bit offset (bit 29 = 1).<ref name="LSB0468">{{cite web |title=GE-645 System Manual |url=http://bitsavers.org/pdf/ge/GE-645/LSB0468_GE-645_System_Manual_Jan1968.pdf |publisher=General Electric |access-date=26 September 2023 |ref=LSB0468 |date=January 1968}}</ref>{{rp|pages=18,22}}<ref name="AH82-00">{{cite web |date=May 1972 |title=MODEL 645 PROCESSOR REFERENCE MANUAL |url=http://people.csail.mit.edu/saltzer/Multics/MHP-Saltzer-060508/bookcases/Manuals/AH82-00.ocr.pdf |access-date=26 September 2023 |publisher=Honeywell Information Systems Inc. |ref=AH82-00}}</ref>

The instruction format with bit 29 set to 1 is:
<pre>
                          1 1       2 2 2 2 3    3
        0 2 3             7 8       6 7 8 9 0    5
       +---+---------------+---------+-+-+-+------+
       |BR |       Y       |  OP     |0|I|1| Tag  |
       +---+---------------+---------+-+-+-+------+
</pre>
* '''B''' is the base register field
* '''Y''' is the address field (15 bits), addressing 32KW
* '''OP''' is the opcode (9 bits), the additional bit 27 is the ''opcode extension bit''.
* '''I''' is the interrupt inhibit bit.
* '''Tag''' indicates the type of address modification to be performed; some additional tags are supported by the GE 645.<ref name="LSB0468" />{{rp|pages=19-20}}
=== Address base registers ===
The GE 645 had 8 Address Base Registers (abr's),<ref>Organick (1972), ''op. cit., p.'' 18</ref> these could operate in either "paired" or "unpaired" modes.<ref name="Green">{{cite web |last1=Green |first1=Paul |title=Multics Virtual Memory - Tutorial and Reflections |url=https://multicians.org/pg/mvm.html |website=multicians.org |access-date=20 December 2023}}</ref> The later Honeywell 6180 changed these to 8 pointer registers. Each abr was 24-bits wide consisting of 18 bits for an address and 6 bits for control functions.<ref name=abr>Organick (1972), ''op. cit., p.'' 19</ref>

One bit of the control functions field indicates where an abr is "internal" or "external".  If an abr is internal, another 3-bit subfield of the control functions field specifies another abr with which this abr is paired; that other abr is external, with the external abr containing a segment number in the address field and the internal abr containing an offset within the segment specified by the external abr.<ref name="AH82-00" />{{rp|4{{hyp}}4}}  If an instruction or an indirect word refers to an external abr, the address field in the instruction or indirect word is used as an offset in the segment specified by the external abr.  If it refers to an internal abr, the address field in the instruction or indirect word is added to the offset in the abr, and the resulting value is used as an offset in the segment specified by the external abr with which the internal abr is paired.<ref name="AH82-00" />{{rp|6{{hyp}}26}}

The registers have the following formats depending on how bit 21 is set.<ref name="abr" />

Format as an "external" base, with bit 21 set:

<pre>
                         1 1 2 2 22 
        0                7 8 0 1 23 
       +------------------+---+-+--+
       |     PDW          |\\\|1|\\|
       +------------------+---+-+--+
</pre>

Format as a component to the effective "internal" address with a pointer to an "external" base, with bit 21 clear:

<pre>
                         1 1 2 2 22 
        0                7 8 0 1 23 
       +------------------+---+-+--+
       |     PY           |PB |0|\\|
       +------------------+---+-+--+
                                         
</pre>
* '''PDW''' is the Pointer to a descriptor word 
* '''PY''' is the component P of the effective internal address 'Y'
* '''PB''' is pointer to another base register whose bit 21 = 1


In Multics, an even-numbered abr and the following odd-numbered abr were paired. When writing in Assembly (EPLBSA/ALM)<ref group=NB>EPL BootStrap Assember / Assembly Language for Multics</ref> the standard Multics practice was to label these registers as follows:<ref>Organick (1972), ''op. cit., p.'' 20-21</ref>
* '''ap''' for abr 0
* '''ab''' for abr 1
* '''bp''' for abr 2
* '''bb''' for abr 3
* '''lp''' for abr 4
* '''lb''' for abr 5
* '''sp''' for abr 6
* '''sb''' for abr 7

The naming scheme is based around the following:<ref>Organick (1972), ''op. cit., p.'' 22-23</ref>
* '''a''' for argument-list pointer
* '''b''' for general base
* '''l''' for linkage-segment pointer
* '''s''' for stack-segment pointer

The 8 pointer registers in the Honeywell 6180 and its successors served the same purpose as the 4 paired base registers in the GE-645, referring to an offset within a segment.

==History==
[[Compatible Time-Sharing System|CTSS]] had originated in the [[MIT Computation Center]] using a [[IBM 709]] and was first demonstrated in November 1961,<ref>Pugh (1991), ''op. cit., p.'' 356</ref> it was subsequently upgraded to a [[IBM 7090|7090]] in 1962,<ref name="ctss">{{cite conference |last1=Corbató |first1=Fernando J. |last2=Merwin Daggett |first2=Marjorie |last3=Daley |first3=Robert C. |book-title=Proceedings of the May 1-3, 1962, spring joint computer conference (AIEE-IRE '62 (Spring)). |title=An Experimental Time-Sharing System |date=May 3, 1962 |pages=335–344 |doi=10.1145/1460833.1460871 |publisher=Association for Computing Machiner |isbn=9781450378758 |s2cid=234039583|doi-access=free }}</ref> and finally to a [[IBM_7090#IBM_7094|7094]] in 1963.<ref name="ctss-7094">{{cite web |last1=Van Vleck |first1=Tom |title=The IBM 7094 and CTSS |url=https://www.multicians.org/thvv/7094.html |website=www.multicians.org |access-date=30 October 2023 |language=en}}</ref> This required modification to these standard systems via the addition of a number of [[Request price quotation|RPQ's]] which among others added two banks of memory and bank-switching between user and supervisor mode, i.e. programs running in the A-core memory bank had access to instructions that programs running in the B-core bank did not.<ref name="ctsspg69">{{cite web |url=http://www.bitsavers.org/pdf/mit/ctss/CTSS_ProgrammersGuide_Dec69.pdf |title=The Compatible Time-Sharing System, A Programmer's Guide |editor-last=Crisman |editor-first=P.A. |date=December 31, 1969 |publisher=The M.I.T Computation Center |access-date=March 10, 2022}}</ref>

[[MIT_Computer_Science_and_Artificial_Intelligence_Laboratory#Project_MAC|Project MAC]] formally began with signing of contract with ARPA on the 1st of July 1963. By October 1963 they had received a dedicated 7094 to run CTSS under, this was termed the "Red Machine" due to it having red side panels.<ref name="ctss-7094" /> This would provide a time-sharing environment for Project MAC, and would subsequently be heavily used for the development of Multics. During this period exploratory work was carried out into what a replacement for CTSS would look like and what type of hardware it would require to run on. A committee was formed consisting of [[Fernando J. Corbató]], Ted Glaser, [[Jack Dennis]] and [[Robert M. Graham (computer scientist)|Robert Graham]] with responsibility to visit computer manufacturers to gauge level of interest in the industry to tender for the hardware platform.<ref name="dennis">{{cite web |last1=Dennis |first1=Jack B. (Jack Bonnell) |last2=O'Neill |first2=Judy E. |title=Oral history interview with Jack Bonnell Dennis |url=https://conservancy.umn.edu/handle/11299/107244 |access-date=31 October 2023 |date=31 October 1989|hdl=11299/107244 }}</ref><ref name="Corbató-hist">{{cite web |last1=Corbató |first1=F. J. |title=Oral history interview with Fernando J. Corbató |url=https://conservancy.umn.edu/handle/11299/107230 |access-date=31 October 2023 |date=14 November 1990|hdl=11299/107230 }}</ref> It was made clear that Project MAC was looking for a development partner given the considerable hardware modifications that would be required to meet their requirements, which were specified as:<ref name="Fano">Fano (1979), ''op. cit., p.'' 348</ref>
# User Programs having read/write protection.
# That privileged instructions would not be accessible to end user programs
# At least the ability to address 256KW of memory directly.
# Native multiprocessing capability with all processors been of equivalent functional level
# Effective support for telecommunications which could handle both conventional telephone lines as well as high speed data links that could run graphic display terminals such as the MIT-developed Kludge<ref name="kludge">{{cite web |title=Collection: Massachusetts Institute of Technology, Laboratory for Computer Science research records {{!}} MIT ArchivesSpace |url=https://archivesspace.mit.edu/repositories/2/resources/240 |website=archivesspace.mit.edu}}</ref> graphical terminal.
# Mass storage units, including a fast drum that could be used as a paging device.
# Hardware support for both segmentation and paging with support for a content addressable memory (CAM) so as to reduce virtual memory overhead.

They proceeded to visit among others [[Burroughs Corporation|Burroughs]], [[Control Data Corporation|CDC]], [[Digital Equipment Corporation|DEC]], [[General Electric]], [[IBM]] and [[UNIVAC|Sperry Univac]]. Of these GE and IBM showed the strongest interest.<ref name="dennis" /> By the summer of 1964 proposals was received from DEC, IBM and GE, after evaluations by the Technical Committee a unanimous decision was made to accept the GE proposal for the GE 645 which was a design based on the GE 635 but modified to meet the requirements outlined above.<ref name="Fano" />

While the GE 645 hardware was being designed and debugged in Phoenix, a system was put in place where a GE 635 could be used to run a simulator known as the 6.36,<ref>{{cite web |title=The GE-635s at Project MAC and BTL |url=https://multicians.org/ge635.html |website=multicians.org |access-date=19 October 2023}}</ref> so that development and checkout of Multics could occur in parallel. This process involved creating a tape on the CTSS system which would be inputted to GECOS on the 635 system in MIT so that it would run under the 6.36 simulator; the resulting output would be carried back via tape to CTSS for debugging/analysis.<ref>{{cite web| title=Project MAC Progress Report III, 1966-67 |url=http://www.dtic.mil/dtic/tr/fulltext/u2/648346.pdf | url-status=dead |archive-url=https://web.archive.org/web/20160604032507/http://www.dtic.mil/dtic/tr/fulltext/u2/648346.pdf |archive-date=June 4, 2016}}</ref> This simulated environment was replaced by the first 645 hardware in 1967. The [[General Comprehensive Operating System|GECOS]] operating system was fully replaced by Multics in 1969 with the Multics supervisor<ref name=Glaser>{{cite conference |last1=Glaser |first1=E. L. |last2=Couleur |first2=J. F. |last3=Oliver |first3=G. A. |book-title=Proceedings of the November 30--December 1, 1965, fall joint computer conference, Part I on XX - AFIPS '65 (Fall, part I) |title=System Design of a Computer for Time Sharing Applications|date=30 November 1965 |pages=197–202 |doi=10.1145/1463891.1463913 |url=https://dl.acm.org/doi/10.1145/1463891.1463913 |publisher=Association for Computing Machinery|isbn=9781450378857 |s2cid=15819355 |url-access=subscription }}</ref> separated by [[protection ring]]s with "gates" allowing access from user mode.<ref>{{cite web| title=Project MAC Progress Report V, 1966-68|url=http://www.dtic.mil/dtic/tr/fulltext/u2/687770.pdf | url-status=dead|archive-url=https://web.archive.org/web/20160604032837/http://www.dtic.mil/dtic/tr/fulltext/u2/687770.pdf |archive-date=June 4, 2016}}</ref>

A later generation in the form of the 645F (F for follow-on) wasn't completed by the time the division was sold to [[Honeywell#Honeywell Information Systems|Honeywell]], and became known as the [[Honeywell 6180]]. The original access control mechanism of the GE/Honeywell 645 were found inadequate for high speed trapping of access instructions and the re-implementation in the 6180 solved those problems.<ref>{{cite web|title=A Hardware Architecture for Implementing Protection Rings|author=Michael D. Schroeder and Jerome H. Saltzer|url=http://www.multicians.org/protection.html|access-date=27 September 2012}}</ref> The bulk of these computers running [[time-sharing]] on Multics were installed at the NSA and similar governmental sites. Their usage was limited by the extreme security measures and had limited impact on subsequent systems, other than the protection ring.<ref>{{cite book|title=Mechanizing Proof: Computing, Risk and Trust|author=Donald A. MacKenzie|date=2001 |publisher=The MIT Press|isbn=0-262-13393-8|url-access=registration|url=https://archive.org/details/mechanizingproof0000mack}}</ref>

The hardware protection introduced on this computer and modified on the 6180 was later implemented in the [[Intel 80286|Intel 286]] computer processor as a four-layer protection ring, but four rings was found to be too cumbersome to program and too slow to operate. Protection ring architecture is now used only to protect kernel mode from user mode code just as it was in the original use of the 645.<ref name=Glaser />

==See also==
* [[GE-600 series]]
* [[Honeywell 6000 series]]
* [[Multics]]
* [[Mainframe computer]]
* [[Time-sharing]]
* [[IBM System/360 Model 67]]

==Further reading==
* {{cite book |last1=Organick |first1=Elliott Irving |title=The Multics system; an examination of its structure |date=1972 |publisher=Cambridge, MIT Press |isbn=978-0-262-15012-5 |url=https://archive.org/details/multicssystemex00orga/ |language=en |access-date=22 October 2023}}
* {{cite book |last1=Watson |first1=Richard W. |title=Timesharing system design concepts |date=1970 |publisher=McGraw-Hill |location=New York [usw], Düsseldorf |isbn=978-0070684652 |url=https://archive.org/details/timesharingsyste00wats/ |language=en |access-date=22 October 2023}}
* {{cite book |last1=Donovan |first1=John J. |title=Systems programming |date=1972 |publisher=McGraw-Hill |isbn=978-0-07-017603-4 |url=https://archive.org/details/systemsprogrammi00don_xk6/ |language=en |access-date=22 October 2023}}
* {{cite book |last1=Fano |first1=Robert M. |editor1-last=Belzer |editor1-first=Jack |editor2-last=Holzman |editor2-first=Albert G. |editor3-last=Kent |editor3-first=Allen |title=Encyclopedia of Computer Science and Technology: Volume 12 - Pattern Recognition: Structural Description Languages to Reliability of Computer Systems |date=1979 |publisher=CRC Press |location=New York |isbn=978-0-8247-2262-3 |pages=339–360 |url=https://books.google.com/books?id=IFmaqTI9-KsC |ref=enc |chapter=Project Mac |language=en |access-date=2 November 2023}}
* {{cite book |last1=Pugh |first1=Emerson W. |last2=Johnson |first2=Lyle R. |last3=Palmer |first3=John H. |title=IBM's 360 and early 370 systems |date=1991 |publisher=MIT Press |location=Cambridge, Mass. |isbn=9780262161237 |url=https://archive.org/details/ibms360early370s0000pugh/ |language=en |access-date=31 October 2023}}
*{{cite book |last1=Oldfield |first1=Homer R. |title=King of the Seven Dwarfs : General Electric's ambiguous challenge to the computer industry |date=1996 |publisher=Los Alamitos, Calif. : IEEE Computer Society Press |location=Los Alamitos, Calif. |isbn=978-0-8186-7383-2 |url=https://archive.org/details/kingofsevendwarf0000oldf/page/n3/mode/2up |access-date=5 November 2023}}
*{{cite web |last1=McGee |first1=Russell C. |title=My Adventures with Dwarfs: A Personal History in Mainframe Computers |date=2002 |url=https://drive.google.com/file/d/1Xidu_1CPLpOeSQjGA0xziTYN9hfW8jUr/view |website=Google Docs |access-date=5 November 2023}}
* {{cite book |last1=Kaisler |first1=Stephen H. |title=Mainframe Computer Systems: The General Electric Corporation |date=2020 |publisher=Cambridge Scholars Publishing |isbn=978-1-5275-6116-8 |url=https://books.google.com/books?id=mGMOEAAAQBAJ |language=en |access-date=22 October 2023}}

==Notes==
{{Reflist|group=NB}}

==References==
{{reflist}}

==External links==
*[http://www.multicians.org/645-board.html GE-645 Circuit Board]
*[https://multicians.org/645artist.html 645 System: Artist's Conception]
*[https://multicians.org/phase-one.html Multics Phase One (includes photo of GE-645)]
*[http://www.feb-patrimoine.com/projet/multics/multics.htm Installing the GE-645 in Paris (includes photo of part of a GE-645)]

[[Category:General Electric mainframe computers|600]]
[[Category:Transistorized computers]]
[[Category:36-bit computers]]
[[Category:Computer-related introductions in 1967]]
[[Category:Time-sharing]]