View source for Intel 8080

{{Short description|8-bit microprocessor}}
{{Distinguish|text=the numbered minor planet [[8080 Intel]]}}
{{Use mdy dates|date=October 2011}}
{{Infobox CPU
|name = Intel 8080
|image = Intel 8080 open-closed.jpg
|caption = Closed and open Intel 8080 processor
|produced-start = {{Start date and age|1974|04}}
|produced-end = {{Start date and age|1990}}<ref>{{cite web |title=CPU History – The CPU Museum – Life Cycle of the CPU |url=http://www.cpushack.com/life-cycle-of-cpu.html |archive-url=https://web.archive.org/web/20100116143420/http://www.cpushack.net/life-cycle-of-cpu.html |archive-date=January 16, 2010}}</ref> 
|slowest = 2 |slow-unit = MHz
|fastest = 3.125 |fast-unit = MHz 
|fsb-slowest = 
|fsb-fastest = 
|fsb-slow-unit = 
|fsb-fast-unit = 
|hypertransport-slowest = 
|hypertransport-fastest = 
|hypertransport-slow-unit = 
|hypertransport-fast-unit = 
|qpi-slowest = 
|qpi-fastest = 
|qpi-slow-unit = 
|qpi-fast-unit = 
|dmi-slowest = 
|dmi-fastest = 
|dmi-slow-unit = 
|dmi-fast-unit = 
|size-from = [[6 μm process|6 μm]]
|size-to = 
|soldby = [[Intel]]
|designfirm = Intel
|manuf1 = Intel
|core1 = 
|sock1 = [[Dual in-line package|DIP40]]
|pack1 = 40-pin [[Dual in-line package|DIP]]
|brand1 = 
|arch = 8080
|microarch = 
|instructions =
|transistors = 4,500 or 6,000<ref>Lewnes, Ann, "The Intel386 Architecture Here to Stay", Intel Corporation, Microcomputer Solutions, July/August 1989, page 2</ref>
|extensions =
|data-width = [[8-bit computing|8 bits]]
|address-width = 16 bits
|virtual-width =
|cpuid = 
|code = 
|numcores = 1
|l1cache = 
|application = 
|predecessor = [[Intel 8008]]
|successor = [[Intel 8085]]
|variant =
|pcode =

| support status = Unsupported

}}

The '''Intel 8080''' is [[Intel]]'s second [[8-bit computing|8-bit]] microprocessor. Introduced in April 1974, the 8080 was an enhanced non-[[Binary-code compatibility|binary compatible]] successor to the earlier [[Intel 8008]] microprocessor.<ref name="ENews-04-1974">{{cite news |author=<!--Unstated--> |title=From CPU to software, the 8080 Microcomputer is here |newspaper=Electronic News |location=New York |pages=44–45 |publisher=Fairchild Publications |date=April 15, 1974}}'' Electronic News'' was a weekly trade newspaper. The same advertisement appeared in the [[:File:Intel 8080 Advertisement May 1974.jpg|May 2, 1974, issue of ''Electronics'' magazine]].</ref> Originally intended for use in [[Embedded system|embedded systems]] such as [[calculator]]s, [[cash register]]s, [[computer terminal]]s, and [[industrial robot]]s,<ref>The [[Intel 8008|8008]] (1972) was used for interpolation and control in ASEA's (now ABB) first line of general industrial robots, introduced October 1973.</ref> its performance soon led to adoption in a broader range of systems, ultimately launching the [[microcomputer]] industry.

Several key design choices contributed to the 8080’s success. Its 40‑pin package simplified interfacing compared to the 8008’s 18‑pin design, enabling a more efficient [[data bus]]. The transition to [[NMOS logic|NMOS]] technology provided faster transistor speeds than the 8008's [[PMOS logic|PMOS]], also making it [[transistor–transistor logic|TTL]] compatible. An expanded [[Instruction set architecture|instruction set]] and a full [[16-bit computing|16-bit]] address bus allowed the 8080 to access up to 64&nbsp;KB of memory, quadrupling the capacity of its predecessor. A broader selection of support chips further enhanced its functionality. Many of these improvements stemmed from customer feedback, as designer [[Federico Faggin]] and others at Intel heard from industry about shortcomings in the 8008 architecture.

The 8080 found its way into early [[personal computers]] such as the [[Altair 8800]] and subsequent [[S-100 bus]] systems, and it served as the original target CPU for the [[CP/M]] operating system. It directly influenced the later [[x86 architecture]] which was designed so that its [[assembly language]] closely resembled that of the 8080, permitting many instructions to map directly from one to the other.<ref>{{cite journal |last1=Mazor |first1=Stanley |title=The Intel 8086 Microprocessor: a 16-bit Evolution of the 8080 |journal=IEEE Computer |date=June 1978 |volume=11 |issue=6 |pages=18–27 |doi=10.1109/C-M.1978.218219 |s2cid=16962774 }}</ref>

Originally operating at a [[clock rate]] of 2&nbsp;[[Megahertz|MHz]], with common instructions taking between 4 and 11 clock cycles, the 8080 was capable of executing several hundred thousand [[instructions per second]]. Later, two faster variants, the 8080A-1 and 8080A-2, offered improved clock speeds of 3.125&nbsp;MHz and 2.63&nbsp;MHz, respectively.<ref>{{cite web |title=8080A/8080A-1/8080A-2 8-Bit N Channel Microprocessor |url=http://www.elektronikjk.com/technika_komputerowa/CPU/Intel_8080A.pdf |publisher=Intel |access-date=November 16, 2021 |archive-date=November 15, 2021 |archive-url=https://web.archive.org/web/20211115165927/http://www.elektronikjk.com/technika_komputerowa/CPU/Intel_8080A.pdf |url-status=live }}</ref> In most applications, the processor was paired with two support chips, the 8224 clock generator/driver and the 8228 bus controller, to manage its timing and data flow.

==History==
Microprocessor customers were reluctant to adopt the 8008 because of limitations such as the single addressing mode, low clock speed, low pin count, and small on-chip stack, which restricted the scale and complexity of software. There were several proposed designs for the 8080, ranging from simply adding stack instructions to the 8008 to a complete departure from all previous Intel architectures.<ref name="8080 DEV">{{cite web |last1=Miller |first1=Michael |title=Creating the 8080: The Processor That Started the PC Revolution |url=https://www.pcmag.com/news/creating-the-8080-the-processor-that-started-the-pc-revolution |website=PCMag |date=December 18, 2014 |publisher=Zaff Davis |access-date=14 November 2021 |archive-date=November 14, 2021 |archive-url=https://web.archive.org/web/20211114174610/https://www.pcmag.com/news/creating-the-8080-the-processor-that-started-the-pc-revolution |url-status=live }}</ref> The final design was a compromise between the proposals.

The conception of the 8080 began in the summer of 1971, when [[Intel]] wrapped up development of the [[Intel 4004|4004]] and were still working on the [[Intel 8008|8008]]. After rumors about the "CPU on a chip" came out, Intel started to see interest in the microprocessor from all sorts of customers. At the same time, [[Federico Faggin]] – who led the design of the 4004 and became the primary architect of  the 8080 – was giving some technical seminars on both of the aforementioned microprocessors and visiting customers. He found that they were complaining about the architecture and performance of said microprocessors, especially the 8008 – as its speed at 0.5 MHz was "not adequate."<ref name="8080 DEV"/>

Faggin later proposed the chip to Intel's management and pushed for its implementation in the spring of 1972, as development of the 8008 was wrapping up. However, much to his surprise and frustration, Intel didn't approve the project. Faggin says that Intel wanted to see how the market would react to the 4004 and 8008 first, while others noted the problems Intel was having getting its latest generation of memory chips out the door and wanted to focus on that. As a result, Intel didn't approve of the project until fall of that year.<ref name="8080 DEV"/> Faggin hired [[Masatoshi Shima]], who helped design the logic of the 4004 with him, from Japan in November 1972. Shima did the detailed design under Faggin's direction,<ref>{{cite web |last1=Faggin |first1=Federico |title=8008 and 8080 Q&A |url=https://sites.google.com/site/microprocessorintel4004/8008-8080-q-a |website=Microprocessor Intel 4004 |access-date=15 November 2021 |archive-date=November 15, 2021 |archive-url=https://web.archive.org/web/20211115233233/https://sites.google.com/site/microprocessorintel4004/8008-8080-q-a |url-status=live }}</ref> using the design methodology for random logic with silicon gate that Faggin had created for the 4000 family and the 8008. 

The 8080 was explicitly designed to be a general-purpose microprocessor for a larger number of customers. Much of the development effort was spent trying to integrate the functionalities of the 8008's supplemental chips into one package. It was decided early in development that the 8080 was not to be binary-compatible with the 8008, instead opting for source compatibility once run through a transpiler, to allow new software to not be subject to the same restrictions as the 8008. For the same reason, as well as to expand the capabilities of stack-based routines and interrupts, the stack was moved to external memory. 

Noting the specialized use of general-purpose registers by programmers in mainframe systems, Faggin with Shima and [[Stanley Mazor]] decided the 8080's registers would be specialized, with register pairs having a different set of uses.<ref>{{cite journal |last1=Mazor |first1=Stanley |title=Intel 8080 CPU Chip Development |journal=IEEE Annals of the History of Computing |date=April–June 2007 |volume=29 |issue=2 |pages=70–73 |doi=10.1109/MAHC.2007.25|bibcode=2007IAHC...29b..70M |s2cid=14755544 }}</ref> This also allowed the engineers to more effectively use transistors for other purposes. 

Shima finished the layout in August 1973. Production of the chip later began in December of that year.<ref name="8080 DEV"/> After the development of [[NMOS logic]] fabrication, a prototype of the 8080 was completed in January 1974. It had a flaw, in that driving with standard TTL devices increased the ground voltage because high current flowed into the narrow line. Intel had already produced 40,000 units of the 8080 at the direction of the sales section before Shima characterized the prototype. After working out some typical last-minute issues, Intel introduced the product in March 1974.<ref name="8080 DEV"/> It was released a month later as requiring Low-power Schottky TTL (LS TTL) devices. The 8080A fixed this flaw.<ref>{{Cite journal|last1=Shima|first1=Masatoshi|author-link=Masatoshi Shima|last2=Nishimura|first2=Hirohiko|last3=Ishida|first3=Haruhisa|year=1979|title=座談会 マイクロコンピュータの誕生 開発者 嶋 正利氏に聞く|journal=Bit|language=ja|publisher=共立出版|volume=11|issue=11|pages=4–12|issn=0385-6984}}</ref>

{{anchor|INTERP}}Intel offered an [[instruction set simulator]] for the 8080 named INTERP/80 to run compiled [[PL/M]] programs. It was written<!-- in 1972 or 1973, exact date not known yet --> in [[FORTRAN IV]] by [[Gary Kildall]] while he worked as a consultant for Intel.<ref name="Kildall_1974">{{cite magazine |title=High-level language simplifies microcomputer programming |author-last=Kildall |author-first=Gary Arlen |author-link=Gary Arlen Kildall |website=[[Electronics (magazine)|Electronics]] |publisher=[[McGraw-Hill Education]] |date=1974-06-27 |pages=103–109 [108] |url=https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |access-date=2021-11-14 |url-status=live |archive-url=https://web.archive.org/web/20211114174610/https://www.retrotechnology.com/dri/kildall_highlevel_1974.pdf |archive-date=2021-11-14}}</ref><ref name="Intel_1975">{{cite web |title=8080 Simulator INTERP/80 |series=Microcomputer Software |publisher=[[Intel Corporation]] |date=March 1975 |id=Product Code 98-119A. MCS-516-0375/27.5K |url=https://mark-ogden.uk/files/intel/publications/98-119A%208080%20Simulator%20Interp_80-Mar75.pdf |access-date=2023-11-25 |url-status=live |archive-url=https://web.archive.org/web/20231125172836/https://mark-ogden.uk/files/intel/publications/98-119A%208080%20Simulator%20Interp_80-Mar75.pdf |archive-date=2023-11-25}} (2 pages)</ref>

There is only one patent on the 8080 with the following names: Federico Faggin, Masatoshi Shima, Stanley Mazor.

==Description==

===Programming model===
[[File:Intel 8080 arch.svg|right|thumb|i8080 microarchitecture]]
{| class="infobox" style="font-size:88%;width:34em;"
|+ Intel 8080 registers
|-
| style="text-align:center;"| <sup>1</sup><sub>5</sub>
| style="text-align:center;"| <sup>1</sup><sub>4</sub>
| style="text-align:center;"| <sup>1</sup><sub>3</sub>
| style="text-align:center;"| <sup>1</sup><sub>2</sub>
| style="text-align:center;"| <sup>1</sup><sub>1</sub>
| style="text-align:center;"| <sup>1</sup><sub>0</sub>
| style="text-align:center;"| <sup>0</sup><sub>9</sub>
| style="text-align:center;"| <sup>0</sup><sub>8</sub>
| style="text-align:center;"| <sup>0</sup><sub>7</sub>
| style="text-align:center;"| <sup>0</sup><sub>6</sub>
| style="text-align:center;"| <sup>0</sup><sub>5</sub>
| style="text-align:center;"| <sup>0</sup><sub>4</sub>
| style="text-align:center;"| <sup>0</sup><sub>3</sub>
| style="text-align:center;"| <sup>0</sup><sub>2</sub>
| style="text-align:center;"| <sup>0</sup><sub>1</sub>
| style="text-align:center;"| <sup>0</sup><sub>0</sub>
| ''(bit position)''
|- 16
|colspan="17" | '''Main registers''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| A
| style="text-align:center;background:#DDD" colspan="8"| Flags
| style="width:auto; background:white; color:black;"| '''P'''rogram '''S'''tatus '''W'''ord
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| B
| style="text-align:center;" colspan="8"| C
| style="background:white; color:black;"| '''B'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| D
| style="text-align:center;" colspan="8"| E
| style="background:white; color:black;"| '''D'''
|- style="background:silver;color:black"
| style="text-align:center;" colspan="8"| H
| style="text-align:center;" colspan="8"| L
| style="background:white; color:black;"| '''H''' (indirect address)
|- 
|colspan="17" | '''Index registers''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| SP
| style="background:white; color:black;"| '''S'''tack '''P'''ointer
|- 
|colspan="17" | '''Program counter''' <br/>
|- style="background:silver;color:black"
| style="text-align:center;" colspan="16"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|- 
|colspan="17" | '''Status register'''
|- style="background:silver;color:black"
| style="text-align:center; background:white" colspan="8" | &nbsp;
| style="text-align:center;"| [[Sign flag|S]]
| style="text-align:center;"| [[Zero flag|Z]]
| style="text-align:center;"| 0
| style="text-align:center;"| [[Half-carry flag|<sup>A</sup><sub>C</sub>]]
| style="text-align:center;"| 0
| style="text-align:center;"| [[Parity flag|P]]
| style="text-align:center;"| 1
| style="text-align:center;"| [[Carry flag|C]]
| style="background:white; color:black" | Flags <ref name="AssyLang">{{cite book |title=8080 Assembly Language Programming Manual |date=1975 |publisher=Intel |page=22 |edition=Rev B |url=https://archive.org/download/intel-8080-assembly-language-programming-manual-1975/Intel%208080%20Assembly%20Language%20Programming%20Manual%20%281975%29.pdf |access-date=29 February 2024}}</ref>
|}

The Intel 8080 is the successor to the [[Intel 8008|8008]]. It uses the same basic [[instruction set]] and [[Processor register|register]] model as the 8008, although it is neither [[Source-code compatibility|source code compatible]] nor [[Binary-code compatibility|binary code compatible]] with its predecessor. Every instruction in the 8008 has an equivalent instruction in the 8080. The 8080 also adds 16-bit operations in its instruction set. Whereas the 8008 required the use of the HL register pair to indirectly access its 14-bit memory space, the 8080 has addressing modes to directly access its full 16-bit memory space. The internal 7-level push-down [[call stack]] of the 8008 was replaced by a dedicated 16-bit stack-pointer (SP) register. The 8080's 40-pin [[Dual in-line package|DIP packaging]] provides a 16-bit [[address bus]] and an 8-bit [[Bus (computing)|data bus]] which more efficiently access 64&nbsp;[[Kibibyte|KiB]] (2<sup>16</sup> bytes) of memory.

====Registers====
The processor has seven 8-bit [[processor register|registers]] (A, B, C, D, E, H, and L), where A is the primary 8-bit accumulator. The other six registers can be used as either individual 8-bit registers or in three 16-bit register pairs (BC, DE, and HL, referred to as B, D and H in Intel documents) depending on the particular instruction. Some instructions can also use the HL register pair as a (limited) 16-bit accumulator. A pseudo-register M, which refers to the dereferenced memory location pointed to by HL, can be used almost anywhere other registers can be used. The 8080 has a 16-bit [[Stack-based memory allocation|stack pointer]] to memory, replacing the 8008's internal [[stack (data structure)|stack]], and a 16-bit [[program counter]].

====Flags====
The processor maintains internal [[flag word|flag bits]] (a [[status register]]), which indicate the results of arithmetic and logical instructions. Only certain instructions affect the flags. The flags are:
* [[Sign flag|Sign]] (S), set if the result is negative.
* [[Zero flag|Zero]] (Z), set if the result is zero.
* [[Parity flag|Parity]] (P), set if the number of 1 bits in the result is even.
* [[Carry flag|Carry]] (C), set if the last addition operation resulted in a carry or if the last subtraction operation required a borrow.
* [[Half-carry flag|Auxiliary carry]] (AC or H), used for [[binary-coded decimal]] arithmetic (BCD).

The carry bit can be set or complemented by specific instructions. Conditional-branch instructions test the various flag status bits. The accumulator and the flags together are called the PSW, or program status word. PSW can be pushed to or popped from the stack.

====Commands, instructions====
As with many other 8-bit processors, all instructions are encoded in one byte (including register numbers, but excluding immediate data), for simplicity. Some can be followed by one or two bytes of data, which can be an immediate operand, a memory address, or a port number. Like more advanced processors, it has automatic CALL and RET instructions for multi-level procedure calls and returns (which can even be conditionally executed, like jumps) and instructions to save and restore any 16-bit register pair on the machine stack. Eight one-byte call instructions ({{code|RST}}) for subroutines exist at the fixed addresses 00h, 08h, 10h, ..., 38h. These are intended to be supplied by external hardware in order to invoke a corresponding [[interrupt service routine]], but are also often employed as fast [[system call]]s. The slowest instruction is {{code|XTHL}}, which exchanges the register pair HL with the last item pushed on the stack.

=====8-bit instructions=====
All 8-bit operations with two operands can only be performed on the 8-bit [[Accumulator (computing)|accumulator]] (the A register). The other operand can be either an immediate value, another 8-bit register, or a memory byte addressed by the 16-bit register pair HL. Increments and decrements can be performed on any 8 bit register or an HL-addressed memory byte. Direct copying is supported between any two 8-bit registers and between any 8-bit register and an HL-addressed memory byte. Due to the regular encoding of the {{code|MOV}} instruction (using a quarter of available opcode space), there are redundant codes to copy a register into itself ({{code|MOV B,B}}, for instance), which are of little use, except for delays. However, the systematic opcode for {{code|MOV M,M}} is instead used to encode the halt ([[HLT (x86 instruction)|{{code|HLT}}]]) instruction, halting execution until an external reset or interrupt occurs.

=====16-bit operations=====
Although the 8080 is generally an 8-bit processor, it has limited abilities to perform 16-bit operations. Any of the three 16-bit register pairs (BC, DE, or HL, referred to as B, D, H in Intel documents) or SP can be loaded with an immediate 16-bit value (using {{code|LXI}}), incremented or decremented (using {{code|INX}} and {{code|DCX}}), or added to HL (using {{code|DAD}}). By adding HL to itself, it is possible to achieve the same result as a 16-bit arithmetical left shift with one instruction. The only 16-bit instructions that affect any flag is {{code|DAD}}, which sets the CY (carry) flag in order to allow for programmed 24-bit or 32-bit [[arithmetic]] (or larger), needed to implement [[floating-point arithmetic]]. BC, DE, HL, or PSW can be copied to and from the stack using {{code|PUSH}} and {{code|POP}}. A stack frame can be allocated using {{code|DAD SP}} and {{code|SPHL}}. A branch to a computed pointer can be executed with {{code|PCHL}}. {{code|LHLD}} loads HL from directly addressed memory and {{code|SHLD}} stores HL likewise. The {{code|XCHG}}<ref>[http://www.classiccmp.org/dunfield/r/8080.txt 8080 instruction encoding] {{Webarchive|url=https://web.archive.org/web/20180305170555/http://www.classiccmp.org/dunfield/r/8080.txt |date=March 5, 2018 }}. ClassicCMP.org. Retrieved on October 23, 2011.</ref> instruction exchanges the values of the HL and DE register pairs. {{code|XTHL}}exchanges last item pushed on stack with HL. None of these 16-bit operations were supported on the earlier Intel 8008.

=====Instruction set=====
{{see also|Intel 8008#Instruction set|Intel 8085#Instruction set}}
{|class="wikitable mw-collapsible" style="text-align:center"
!colspan=8| Opcode ||colspan=2| Operands ||rowspan=2| Mnemonic || rowspan=2| Clocks ||rowspan=2| Description
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3
|-
| 0 || 0 || 0 || 0 || 0 || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| NOP || 4 ||align=left| No operation
|-
| 0 || 0 ||colspan=2|RP || 0 || 0 || 0 || 1 || ''datlo'' || ''dathi'' ||align=left| LXI ''rp,data'' || 10 ||align=left| RP ← ''data''
|-
| 0 || 0 ||colspan=2|RP || 0 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| STAX ''rp'' || 7 ||align=left| (RP) ← A [BC or DE only]
|-
| 0 || 0 ||colspan=2|RP || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| INX ''rp'' || 5 ||align=left| RP ← RP + 1
|-
| 0 || 0 ||colspan=3|DDD || 1 || 0 || 0 || &mdash; || &mdash; ||align=left| INR ''ddd'' || 5/10 ||align=left| DDD ← DDD + 1
|-
| 0 || 0 ||colspan=3|DDD || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| DCR ''ddd'' || 5/10 ||align=left| DDD ← DDD - 1
|-
| 0 || 0 ||colspan=3|DDD || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| MVI ''ddd,data'' || 7/10 ||align=left| DDD ← data
|-
| 0 || 0 ||colspan=2|RP || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| DAD ''rp'' || 10 ||align=left| HL ← HL + RP
|-
| 0 || 0 ||colspan=2|RP || 1 || 0 || 1 || 0 || &mdash; || &mdash; ||align=left| LDAX ''rp'' || 7 ||align=left| A ← (RP) [BC or DE only]
|-
| 0 || 0 ||colspan=2|RP || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| DCX ''rp'' || 5 ||align=left| RP ← RP - 1
|-
| 0 || 0 || 0 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RLC || 4 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; A<sub>0</sub> ← Cy ← A<sub>7</sub>
|-
| 0 || 0 || 0 || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RRC || 4 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; A<sub>7</sub> ← Cy ← A<sub>0</sub>
|-
| 0 || 0 || 0 || 1 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RAL || 4 ||align=left| A<sub>1-7</sub> ← A<sub>0-6</sub>; Cy ← A<sub>7</sub>; A<sub>0</sub> ← Cy
|-
| 0 || 0 || 0 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RAR || 4 ||align=left| A<sub>0-6</sub> ← A<sub>1-7</sub>; Cy ← A<sub>0</sub>; A<sub>7</sub> ← Cy
|-
| 0 || 0 || 1 || 0 || 0 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| SHLD ''add'' || 16 ||align=left| (add) ← HL
|-
| 0 || 0 || 1 || 0 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| DAA || 4 ||align=left| If A<sub>0-3</sub> > 9 OR AC = 1 then A ← A + 6;
then if A<sub>4-7</sub> > 9 OR Cy = 1 then A ← A + 0x60
|-
| 0 || 0 || 1 || 0 || 1 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| LHLD ''add'' || 16 ||align=left| HL ← (add)
|-
| 0 || 0 || 1 || 0 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| CMA || 4 ||align=left| A ← ¬A
|-
| 0 || 0 || 1 || 1 || 0 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| STA ''add'' || 13 ||align=left| (add) ← A
|-
| 0 || 0 || 1 || 1 || 0 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| STC || 4 ||align=left| Cy ← 1
|-
| 0 || 0 || 1 || 1 || 1 || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| LDA ''add'' || 13 ||align=left| A ← (add)
|-
| 0 || 0 || 1 || 1 || 1 || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| CMC || 4 ||align=left| Cy ← ¬Cy
|-
| 0 || 1 ||colspan=3|DDD ||colspan=3|SSS || &mdash; || &mdash; ||align=left| MOV ''ddd,sss'' ||5/7 ||align=left| DDD ← SSS
|-
| 0 || 1 || 1 || 1 || 0 || 1|| 1 || 0 || &mdash; || &mdash; ||align=left| HLT || 7 ||align=left| Halt
|-
| 1 || 0 ||colspan=3|ALU ||colspan=3|SSS || &mdash; || &mdash; ||align=left| ADD ADC SUB SBB ANA XRA ORA CMP ''sss'' || 4/7 ||align=left| A ← A [ALU operation] SSS
|-
| 1 || 1 ||colspan=3|CC || 0 || 0 || 0 || &mdash; || &mdash; ||align=left| Rcc (RET conditional) || 5/11 ||align=left| If cc true, PC ← (SP), SP ← SP + 2
|-
| 1 || 1 ||colspan=2|RP || 0 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| POP ''rp'' || 10 ||align=left| RP ← (SP), SP ← SP + 2
|-
| 1 || 1 ||colspan=3|CC || 0 || 1 || 0 || ''addlo'' || ''addhi'' ||align=left| Jcc ''add'' (JMP conditional) || 10 ||align=left| If cc true, PC ← add
|-
| 1 || 1 || 0 || 0 || 0 || 0 || 1 || 1 || ''addlo'' || ''addhi'' ||align=left| JMP ''add'' || 10 ||align=left| PC ← add
|-
| 1 || 1 ||colspan=3|CC || 1 || 0 || 0 || ''addlo'' || ''addhi'' ||align=left| Ccc ''add'' (CALL conditional) || 11/17 ||align=left| If cc true, SP ← SP - 2, (SP) ← PC, PC ← add
|-
| 1 || 1 ||colspan=2|RP || 0 || 1 || 0 || 1 || &mdash; || &mdash; ||align=left| PUSH ''rp'' || 11 ||align=left| SP ← SP - 2, (SP) ← RP
|-
| 1 || 1 ||colspan=3|ALU || 1 || 1 || 0 || ''data'' || &mdash; ||align=left| ADI ACI SUI SBI ANI XRI ORI CPI ''data'' || 7 ||align=left| A ← A [ALU operation] data
|-
| 1 || 1 ||colspan=3|N || 1 || 1 || 1 || &mdash; || &mdash; ||align=left| RST ''n'' || 11 ||align=left| SP ← SP - 2, (SP) ← PC, PC ← N x 8
|-
| 1 || 1 || 0 || 0 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| RET || 10 ||align=left| PC ← (SP), SP ← SP + 2
|-
| 1 || 1 || 0 || 0 || 1 || 1 || 0 || 1 || ''addlo'' || ''addhi'' ||align=left| CALL ''add'' || 17 ||align=left| SP ← SP - 2, (SP) ← PC, PC ← add
|-
| 1 || 1 || 0 || 1 || 0 || 0 || 1 || 1 || ''port'' || &mdash; ||align=left| OUT ''port'' || 10 ||align=left| Port ← A
|-
| 1 || 1 || 0 || 1 || 1 || 0 || 1 || 1 || ''port'' || &mdash; ||align=left| IN ''port'' || 10 ||align=left| A ← Port
|-
| 1 || 1 || 1 || 0 || 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| XTHL || 18 ||align=left| HL ↔ (SP)
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| PCHL || 5 ||align=left| PC ← HL
|-
| 1 || 1 || 1 || 0 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| XCHG || 4 ||align=left| HL ↔ DE
|-
| 1 || 1 || 1 || 1|| 0 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| DI || 4 ||align=left| Disable interrupts
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 0 || 1 || &mdash; || &mdash; ||align=left| SPHL || 5 ||align=left| SP ← HL
|-
| 1 || 1 || 1 || 1 || 1 || 0 || 1 || 1 || &mdash; || &mdash; ||align=left| EI || 4 ||align=left| Enable interrupts
|-
! 7 || 6 || 5 || 4 || 3 || 2 || 1 || 0 || b2 || b3 || Mnemonic || Clocks || Description
|-
!colspan=13|
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU||RP||
|-
|colspan=5| B || 0 || 0 || 0 ||colspan=2|NZ ||align=left|ADD ADI (A ← A + arg)|| BC
|-
|colspan=5| C || 0 || 0 || 1||colspan=2|Z||align=left|ADC ACI (A ← A + arg + Cy)|| DE
|-
|colspan=5| D || 0 || 1 || 0||colspan=2|NC ||align=left|SUB SUI (A ← A - arg)|| HL
|-
|colspan=5| E || 0 || 1 || 1||colspan=2|C ||align=left|SBB SBI (A ← A - arg - Cy)|| SP or PSW
|-
|colspan=5| H || 1 || 0 || 0||colspan=2|PO ||align=left|ANA ANI (A ← A ∧ arg)
|-
|colspan=5| L || 1 || 0 || 1||colspan=2|PE ||align=left|XRA XRI (A ← A ⊻ arg)
|-
|colspan=5| M || 1 || 1 || 0||colspan=2|P ||align=left|ORA ORI (A ← A ∨ arg)
|-
|colspan=5| A || 1 || 1 || 1||colspan=2|N||align=left|CMP CPI (A - arg)
|-
!colspan=5|SSS DDD|| 2 || 1 || 0 ||colspan=2|CC ||ALU||colspan=2|
|}

===Input/output scheme===

====Input output port space====
The 8080 supports 256 [[input/output]] (I/O) ports,<ref>Note: Some Intel datasheets from the 1970s advertise 512 I/O ports, because they count input and output ports separately.</ref> accessed via dedicated I/O instructions taking port addresses as operands.<ref>{{cite book |title=Computer Architecture and Organization |last1=HAYES
  |first1=JOHN P. |isbn=0-07-027363-4 |year=1978 |publisher= McGraw-Hill|pages=420–423 }}</ref> This I/O mapping scheme is regarded as an advantage, as it frees up the processor's limited address space. Many CPU architectures instead use so-called [[memory-mapped I/O]] (MMIO), in which a common address space is used for both RAM and peripheral chips. This removes the need for dedicated I/O instructions, although a drawback in such designs may be that special hardware must be used to insert wait states, as peripherals are often slower than memory. However, in some simple 8080 computers, I/O is indeed addressed as if they were memory cells, "memory-mapped", leaving the I/O commands unused. I/O addressing can also sometimes employ the fact that the processor outputs the same 8-bit port address to both the lower and the higher address byte (i.e., {{code|IN 05h}} would put the address 0505h on the 16-bit address bus). Similar I/O-port schemes are used in the backward-compatible Zilog Z80 and Intel 8085, and the closely related x86 microprocessor families.

====Separate stack space====
One of the bits in the processor state word (see below) indicates that the processor is accessing data from the stack. Using this signal, it is possible to implement a separate stack memory space. This feature is seldom used.

===Status word===
For more advanced systems, during the beginning of each machine cycle, the processor places an eight bit status word on the data bus. This byte contains flags that determine whether the memory or I/O port is accessed and whether it is necessary to handle an interrupt.

The interrupt system state (enabled or disabled) is also output on a separate pin. For simple systems, where the interrupts are not used, it is possible to find cases where this pin is used as an additional single-bit output port (the popular [[Radio-86RK]] computer made in the [[Soviet Union]], for instance).

===Interrupts===
Hardware [[interrupt]]s are initiated by asserting the interrupt request (INT) pin. At the next opcode fetch cycle (M<sub>1</sub>), the interrupt will be acknowledged with the INTA state code. At this time, an instruction is "jammed" (Intel's word) by external hardware on the data bus. This can be a one-byte <code>RST</code> instruction, or if using an [[Intel 8259]], a <code>CALL</code> instruction. Interrupts may be enabled and disabled with <code>EI</code> and <code>DI</code> instructions, respectively. Interrupts are disabled after an INTA; they must be re-enabled explicitly by the [[interrupt service routine]]. The 8080 does not support [[non-maskable interrupt]]s.

===Example code===
The following 8080/8085 [[assembly language|assembler]] source code is for a subroutine named {{code|memcpy}} that copies a block of data bytes of a given size from one location to another. The data block is copied one byte at a time, and the data movement and looping logic utilizes 16-bit operations.

<!--This code is not intended to be optimized, but to illustrate the variety of instructions available on the CPU. Still, it must be correct.-->
{|
|
<pre>
 
 
 
 
 
 
 
 
 
 
 
1000
1000
1000  1A
1001  77
1002  13
1003  23
1004  0B
1005  78
1006  B1
1007  C2 00 10
100A  C9
</pre>
|
<syntaxhighlight lang="nasm">
; memcpy --
; Copy a block of memory from one location to another.
;
; Entry registers
;       BC - Number of bytes to copy
;       DE - Address of source data block
;       HL - Address of target data block
;
; Return registers
;       BC - Zero

            org     1000h       ;Origin at 1000h
memcpy      public
loop:       ldax    d           ;Load A from the address pointed by DE
            mov     m,a         ;Store A into the address pointed by HL
            inx     d           ;Increment DE
            inx     h           ;Increment HL
            dcx     b           ;Decrement BC   (does not affect Flags)
            mov     a,b         ;Copy B to A    (so as to compare BC with zero)
            ora     c           ;A = A | C      (are both B and C zero?)
            jnz     loop        ;Jump to 'loop:' if the zero-flag is not set.   
            ret                 ;Return
</syntaxhighlight>
|}

===Pin use===
[[File:Intel 8080 Microprocessor.png|thumb|300px|8080 [[pinout]]]]

The address bus has its own 16 pins, and the data bus has 8 pins that are usable without any multiplexing. Using the two additional pins (read and write signals), it is possible to assemble simple microprocessor devices very easily. Only the separate IO space, interrupts, and DMA need added chips to decode the processor pin signals. However, the pin load capacity is limited; even simple computers often require bus amplifiers.

The processor needs three power sources (−5, +5, and +12&nbsp;V) and two non-overlapping high-amplitude synchronizing signals. However, at least the late Soviet version КР580ВМ80А was able to work with a single +5&nbsp;V power source, the +12&nbsp;V pin being connected to +5&nbsp;V and the −5&nbsp;V pin to ground.

The pin-out table, from the chip's accompanying documentation, describes the pins as follows:

{| class="wikitable"
 ! Pin number
 ! Signal
 ! Type
 ! Comment
 |-
 | 1 || A10
 | Output || Address bus 10
 |-
 | 2 || GND
 | — || Ground
 |-
 | 3 || D4
 | rowspan="8" | Bidirectional
 | rowspan="8" | Bidirectional data bus. The processor also momentarily transmits the "processor state" during SYNC^φ1, providing information about what the processor is currently doing:
*D0 (INTA) reading interrupt command. In response to the interrupt signal, the processor is reading and executing a single arbitrary command with this flag raised. Normally the supporting chips provide the subroutine call command (CALL or RST), transferring control to the interrupt handling code.
*D1 (WO-) low true. Write to memory or output to port
*D2 (STACK) accessing stack (probably a separate stack memory space was initially planned)
*D3 (HLTA) doing nothing, has been halted by the [[HLT (x86 instruction)|HLT]] instruction
*D4 (OUT) writing data to an output port
*D5 (M<sub>1</sub>) reading the first byte of an instruction
*D6 (IN) reading data from an input port
*D7 (MEMR) reading data from memory
 |-
 | 4 || D5
 |-
 | 5 || D6
 |-
 | 6 || D7
 |-
 | 7 || D3
 |-
 | 8 || D2
 |-
 | 9 || D1
 |-
 | 10 || D0
 |-
 | 11 || −5 V
 | — || The −5 V power supply. This must be the first power source connected and the last disconnected, otherwise the processor will be damaged.
 |-
 | 12 || RESET
 | Input || Reset. This active low signal forces execution of commands located at address 0000. The content of other processor registers is not modified.
 |-
 | 13 || HOLD
 | Input || Direct memory access request. The processor is requested to switch the data and address bus to the high impedance ("disconnected") state.
 |-
 | 14 || INT
 | Input || Interrupt request
 |-
 | 15 || φ2
 | Input || The second phase of the clock generator signal
 |-
 | 16 || INTE
 | Output || The processor has two commands for setting 0 or 1 level on this pin. The pin normally is supposed to be used for interrupt control. However, in simple computers it was sometimes used as a single bit output port for various purposes.
 |-
 | 17 || DBIN
 | Output || Read (the processor reads from memory or input port)
 |-
 | 18 || WR-
 | Output || Write (the processor writes to memory or output port). This is an active low output.
 |-
 | 19 || SYNC
 | Output || Active level indicates that the processor has put the "state word" on the data bus. The various bits of this state word provide added information to support the separate address and memory spaces, interrupts, and direct memory access. This signal is required to pass through additional logic before it can be used to write the processor state word from the data bus into some external register, e.g., [http://www.datasheets360.com/pdf/-4828066515233335508 8238] {{Webarchive|url=https://web.archive.org/web/20230918030959/https://www.datasheets360.com/pdf/-4828066515233335508 |date=September 18, 2023 }}-System Controller and Bus Driver.
 |-
 | 20 || +5 V || — || The + 5&nbsp;V power supply
 |-
 | 21 || HLDA
 | Output || Direct memory access confirmation. The processor switches data and address pins into the high impedance state, allowing another device to manipulate the bus
 |-
 | 22 || φ1
 | Input || The first phase of the clock generator signal
 |-
 | 23 || READY
 | Input || Wait. With this signal it is possible to suspend the processor's work. It is also used to support the hardware-based step-by step debugging mode.
 |-
 | 24 || WAIT
 | Output || Wait (indicates that the processor is in the waiting state)
 |-
 | 25 || A0
 | rowspan="3" | Output
 | rowspan="3" | Address bus
 |-
 | 26 || A1
 |-
 | 27 || A2
 |-
 | 28 || 12 V
 | — || The +12 V power supply. This must be the ''last'' connected and first disconnected power source.
 |-
 | 29 || A3
 | rowspan="12" | Output
 | rowspan="12" | The address bus; can switch into high impedance state on demand
 |-
 | 30 || A4
 |-
 | 31 || A5
 |-
 | 32 || A6
 |-
 | 33 || A7
 |-
 | 34 || A8
 |-
 | 35 || A9
 |-
 | 36 || A15
 |-
 | 37 || A12
 |-
 | 38 || A13
 |-
 | 39 || A14
 |-
 | 40 || A11
 |}

== Support chips ==
A key factor in the success of the 8080 was the broad range of support chips available, providing serial communications, counter/timing, input/output, direct memory access, and programmable interrupt control amongst other functions:
* 8214 - Priority Interrupt Control Unit<ref>[http://www.bitsavers.org/components/intel/MCS80/98-153B_Intel_8080_Microcomputer_Systems_Users_Manual_197509.pdf Intel Corporation, "8214 Priorty Interrupt Control Unit", Intel 8080 Microcomputer Systems User's Manual, September 1975, page 5-153] {{Webarchive|url=https://web.archive.org/web/20240528085204/http://bitsavers.org/components/intel/MCS80/98-153B_Intel_8080_Microcomputer_Systems_Users_Manual_197509.pdf |date=May 28, 2024 }} from bitsaver.org in PDF</ref>
* 8224 – [[Clock generator]]
* 8228/8238 – System controller and bus driver
* [[Intel 8251|8251]] – Communication controller
* [[Intel 8253|8253]] – [[Programmable interval timer]]
* [[Intel 8255|8255]] – Programmable peripheral interface
* [[Intel 8257|8257]] – [[Direct memory access|DMA controller]]
* [[Intel 8259|8259]] – [[Programmable interrupt controller]]

==Physical implementation==
The 8080 [[integrated circuit]] has an [[NMOS logic|NMOS]] design, which employed non‑saturated [[Depletion and enhancement modes|enhancement mode]] transistors as loads,<ref>similar to ''[[Pull-up resistor|pull-up resistors]]''</ref><ref>{{cite book |last=Tohya |first=Hirokazu |url=https://books.google.com/books?id=ILceDgAAQBAJ&q=8080+non-saturated+enhancement&pg=PA4 |title=Switching Mode Circuit Analysis and Design: Innovative Methodology by Novel Solitary Electromagnetic Wave Theory |date=2013 |publisher=Bentham Science Publishers |isbn=9781608054497 |page=4 |language=en |access-date=November 28, 2020 |archive-url=https://web.archive.org/web/20211115163542/https://books.google.com/books?id=ILceDgAAQBAJ&q=8080+non-saturated+enhancement&pg=PA4 |archive-date=November 15, 2021 |url-status=live}}</ref> which demanded supplementary voltage levels (+12&nbsp;[[Volt|V]] and −5&nbsp;V) alongside the standard [[Transistor–transistor logic|TTL]] compatible +5&nbsp;V.

It was manufactured in a [[silicon gate]] process using a minimal feature size of 6&nbsp;μm. A single layer of metal is used to [[Electrical connection|interconnect]] the approximately 4,500 transistors<ref>{{cite web |title=Intel Chips timeline |url=https://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/history-intel-chips-timeline-poster.pdf |website=Intel |publisher=Intel Corporation |access-date=14 November 2021 |archive-date=November 14, 2021 |archive-url=https://web.archive.org/web/20211114170816/https://www.intel.com/content/dam/www/public/us/en/documents/corporate-information/history-intel-chips-timeline-poster.pdf |url-status=live }}</ref> in the design, but the higher [[Electrical resistance|resistance]] [[Polycrystalline silicon|polysilicon]] layer, which required higher voltage for some interconnects, is implemented with transistor gates. The [[Die preparation|die]] size is approximately 20&nbsp;mm<sup>2</sup>.

==Commercial impact==

===Applications and successors===
{{anchor|8080 CPU family}}
The 8080 was used in many early microcomputers, such as the MITS [[Altair 8800]] Computer, [[Processor Technology]] [[SOL-20]] Terminal Computer and [[IMSAI 8080]] Microcomputer, forming the basis for machines running the [[CP/M]] operating system (the later, almost fully compatible and more able, [[Zilog Z80]] processor would capitalize on this, with Z80 and CP/M becoming the dominant CPU and OS combination of the period {{circa|1976}} to 1983 much like [[x86]] and [[MS-DOS]] a decade later).

In 1979, even after the introduction of the Z80 and 8085 processors, five manufacturers of the 8080 were selling an estimated 500,000 units per month at a price around $3 to $4 each.<ref>{{cite news |last=Libes |first=Sol |title=Byte News |periodical=[[Byte (magazine)|Byte]] |issn=0360-5280 |volume=4 |series=11 |date=November 1979 |page=82}}</ref>

The first [[single-board computer|single-board microcomputer]]s, such as [[MYCRO-1]] and the ''dyna-micro'' / MMD-1 (see: [[Single-board computer]]) were based on the Intel 8080. One of the early uses of the 8080 was made in the late 1970s by Cubic-Western Data of San Diego, California, in its Automated Fare Collection Systems custom designed for mass transit systems around the world. An early industrial use of the 8080 is as the "brain" of the DatagraphiX Auto-COM (Computer Output Microfiche) line of products which takes large amounts of user data from reel-to-reel tape and images it onto microfiche. The Auto-COM instruments also include an entire automated film cutting, processing, washing, and drying sub-system.

Several early [[arcade video game]]s were built around the 8080 microprocessor. The first commercially available arcade video game to incorporate a microprocessor was ''[[Gun Fight]]'', [[Midway Games]]' 8080-based reimplementation of [[Taito]]'s discrete-logic ''[[Western Gun]]'', which was released in November 1975.<ref name="stackexchange_1st_micro_coin-op">{{cite web|title=What was the first arcade game to use a microprocessor instead of discrete logic?|url=https://retrocomputing.stackexchange.com/questions/613/what-was-the-first-arcade-game-to-use-a-microprocessor-instead-of-discrete-logic|access-date=2023-04-11|archive-date=April 11, 2023|archive-url=https://web.archive.org/web/20230411143158/https://retrocomputing.stackexchange.com/questions/613/what-was-the-first-arcade-game-to-use-a-microprocessor-instead-of-discrete-logic|url-status=live}}</ref><ref name="Kent_8080_Gun_Fight">[[Steve L. Kent]] (2001), ''[[The ultimate history of video games: from Pong to Pokémon and beyond : the story behind the craze that touched our lives and changed the world]]'', p. 64, Prima, {{ISBN|0-7615-3643-4}}</ref><ref name=Akagi_Gun_Fight>{{cite book |last1=Akagi |first1=Masumi |title=アーケードTVゲームリスト国内•海外編(1971–2005) |trans-title=Arcade TV Game List: Domestic • Overseas Edition (1971–2005) |date=13 October 2006 |publisher=Amusement News Agency |lang=ja |location=Japan |isbn=978-4990251215 |page=124 |url=https://archive.org/details/ArcadeGameList1971-2005/page/n125}}</ref><ref name="Demolition_Derby_game">{{cite web|title=Dave Needle and Jerry Lawson - Two Early Independent Video Game Designers|date=July 29, 2013 |url=http://allincolorforaquarter.blogspot.com/2013/07/dave-needle-and-jerry-lawon-two-early.html|access-date=2023-04-11|archive-date=April 11, 2023|archive-url=https://web.archive.org/web/20230411143158/http://allincolorforaquarter.blogspot.com/2013/07/dave-needle-and-jerry-lawon-two-early.html|url-status=live}}</ref> (A pinball machine which incorporated a [[Motorola]] [[Motorola 6800|6800]] processor, ''[[The Spirit of '76 (pinball)|The Spirit of '76]]'', had already been released the previous month.<ref>{{cite web|url=http://www.ipdb.org/machine.cgi?id=2294|title=Internet Pinball Machine Database: Mirco Games, Inc. 'Spirit of 76'|website=www.ipdb.org|access-date=2023-04-11|archive-date=April 16, 2023|archive-url=https://web.archive.org/web/20230416224750/https://www.ipdb.org/machine.cgi?id=2294|url-status=live}}</ref><ref>{{cite web|last1=wayout440|url=https://pinside.com/pinball/forum/topic/mirco-spirit-of-76-for-sale-the-first-solid-state-pin|title=Mirco Spirit of 76 for sale – THE first solid state pin?|website=Pinside.com|access-date=2023-04-11|archive-date=April 11, 2023|archive-url=https://web.archive.org/web/20230411143207/https://pinside.com/pinball/forum/topic/mirco-spirit-of-76-for-sale-the-first-solid-state-pin|url-status=live}}</ref>) The 8080 was then used in later Midway arcade video games<ref name="Midway_8080_board">{{cite web|title=Midway 8080 System Boards|url=https://arcarc.xmission.com/Web%20Archives/Users.Erols.Com-mowerman%20(Aug-24-2003)/midway.htm|access-date=2023-04-11|archive-date=April 11, 2023|archive-url=https://web.archive.org/web/20230411145527/https://arcarc.xmission.com/Web%20Archives/Users.Erols.Com-mowerman%20(Aug-24-2003)/midway.htm|url-status=live}}</ref> and in Taito's 1978 ''[[Space Invaders]]'', one of the most successful and well-known of all arcade video games.<ref name="KLOV_Space_Invaders">{{cite web |url=http://www.klov.com/game_detail.php?game_id=9662 |title=Space Invaders Videogame by Bally Midway (1978) |publisher=[[Killer List of Videogames]] |access-date=April 11, 2023 |archive-date=November 25, 2010 |archive-url=https://web.archive.org/web/20101125042142/http://www.arcade-museum.com/game_detail.php?game_id=9662 |url-status=live }}</ref><ref name="1UP_Space_Invaders">{{cite web |url=http://www.1up.com/do/feature?cId=3168373 |archive-url=https://web.archive.org/web/20090226064943/http://www.1up.com/do/feature?cId=3168373 |url-status=dead |archive-date=February 26, 2009 |title=Ten Things Everyone Should Know About Space Invaders |website=[[1UP.com]] |author=Edwards, Benj|access-date=2023-04-11}}</ref>

[[Zilog]] introduced the [[Zilog Z80|Z80]], which has a compatible [[Machine code|machine language]] instruction set and initially used the same assembly language as the 8080, but for legal reasons, Zilog developed a syntactically-different (but code compatible) alternative [[Z80 instruction set|assembly language for the Z80.]] At Intel, the 8080 was followed by the compatible and electrically more elegant [[Intel 8085|8085]].

Later, Intel issued the assembly-language compatible (but not binary-compatible) 16-bit [[Intel 8086|8086]] and then the 8/16-bit [[Intel 8088|8088]], which was selected by [[IBM]] for its new [[IBM PC|PC]] to be launched in 1981. Later [[NEC]] made the [[NEC V20]] (an 8088 clone with [[Intel 80186]] instruction set compatibility) which also supports an 8080 emulation mode. This is also supported by NEC's [[NEC V30|V30]] (a similarly enhanced 8086 clone). Thus, the 8080, via its [[instruction set architecture]] (ISA), made a lasting impact on computer history.

A number of processors compatible with the Intel 8080A were manufactured in the [[Eastern Bloc]]: the [[KR580VM80A]] (initially marked as КР580ИК80) in the [[Soviet Union]], the MCY7880<ref>[http://www.cpu-world.com/CPUs/8080/Poland-MCY7880.html MCY7880—a Polish-made clone of 8080] {{Webarchive|url=https://web.archive.org/web/20160817083511/http://www.cpu-world.com/CPUs/8080/Poland-MCY7880.html |date=August 17, 2016 }}. CPU World. Retrieved on October 23, 2011.</ref> made by Unitra CEMI in [[Poland]], the MHB8080A<ref name=cpuworld>[http://www.cpu-world.com/info/exUSSR-chips.html Soviet chips and their western analogs] {{Webarchive|url=https://web.archive.org/web/20170209223725/http://www.cpu-world.com/info/exUSSR-chips.html |date=February 9, 2017 }}. CPU-world. Retrieved on October 23, 2011.</ref> made by [[Tesla (Czechoslovak company)|TESLA]] in [[Czechoslovakia]], the 8080APC<ref name=cpuworld/> made by [[Tungsram]] / MEV in [[Hungary]], and the MMN8080<ref name=cpuworld/> made by [[Electronics industry in the Socialist Republic of Romania|Microelectronica Bucharest]] in [[Romania]].

{{asof|2017}}, the 8080 is still in production at Lansdale Semiconductors.<ref>{{cite web |title=Intel – Microprocessor 8080A Family & 828X Series |url=http://lansdale.com/parts_reference.php?manufacturer=Intel&series=Microprocessor+8080A+Family+%26+828X+Series |author=<!--Unstated--> |publisher=Lansdale Semiconductor Inc. |access-date=20 June 2017 |archive-date=October 14, 2015 |archive-url=https://web.archive.org/web/20151014132249/http://www.lansdale.com/parts_reference.php?manufacturer=Intel&series=Microprocessor+8080A+Family+%26+828X+Series |url-status=live }}</ref>

<gallery mode="packed" heights="150" caption="Intel 8080 [[second source]]s">
File:AMD C8080A.jpg|[[AMD Am9080]]
File:Poland MCY7880 1.jpg|CEMI MCY7880 (Poland)
File:580IK80.jpg|Kvazar Kyiv [[KR580VM80A|K580IK80]] (Ukrainian SSR)
File:Mitsubishi M5L8080AP 1.jpg|[[Mitsubishi Electric]] M5L8080
File:NatSem INS8080AJ 1.jpg|[[National Semiconductor]] INS8080
File:NEC 8080AF 1.jpg|[[NEC μPD8080AF]]
File:OKI MSM8080A 1.jpg|[[Oki Electric Industry|OKI]] MSM8080
File:Siemens SAB8080A 1.jpg|[[Siemens]] SAB8080
File:Signetics MP8080AI 1.jpg|[[Signetics]] MP8080
File:KL Tesla MHB8080.jpg|[[Tesla (Czechoslovak company)|Tesla]] MHB8080
File:TI TMS8080JL 1.jpg|[[Texas Instruments]] TMS8080
File:5G8080.jpg|5G8080 (PR China)
</gallery>

===Industry change===
{{OR section|date=August 2017}}

The 8080 also changed how computers were created. When the 8080 was introduced, computer systems were usually created by computer manufacturers such as [[Digital Equipment Corporation]], [[Hewlett-Packard]], or [[IBM]]. A manufacturer would produce the whole computer, including processor, terminals, and system software such as compilers and operating system. The 8080 was designed for almost any application ''except'' a complete computer system. Hewlett-Packard developed the [[HP 2640]] series of smart terminals around the 8080. The [[HP 2647]] is a terminal which runs the programming language [[BASIC]] on the 8080. [[Microsoft]]'s founding product, [[Microsoft BASIC]], was originally programmed for the 8080.

The 8080 and [[Intel 8085|8085]] gave rise to the 8086, which was designed as a [[Source-code compatibility|source code compatible]], albeit not [[Binary-code compatibility|binary compatible]], extension of the 8080.<ref>{{cite journal |last1=Morse |first1=Stephen |last2=Ravenel |first2=Bruce |last3=Mazor |first3=Stanley |last4=Pohlman |first4=William |title=Intel Microprocessors: 8008 to 8086 |journal=IEEE Computer |date=October 1980 |volume=13 |issue=10 |pages=42–60 |doi=10.1109/MC.1980.1653375 |s2cid=206445851 |url=https://stevemorse.org/8086history/8086history.pdf |access-date=November 5, 2021 |archive-date=September 14, 2021 |archive-url=https://web.archive.org/web/20210914205011/https://stevemorse.org/8086history/8086history.pdf |url-status=live }}</ref> This design, in turn, later spawned the [[x86]] family of chips, which continue to be Intel's primary line of processors. Many of the 8080's core machine instructions and concepts survive in the widespread x86 platform. Examples include the registers named ''A'', ''B'', ''C'', and ''D'' and many of the flags used to control conditional jumps. 8080 assembly code can still be directly translated into x86 instructions,{{vague|date=November 2021|reason=Does this mean 8080 instructions can be translated into IA-32 and AMD64-specific instructions?}} since all of its core elements are still present.

===US Patent===
{{US patent reference|number=4010449|issue-date=March 1, 1977|inventor=[[Federico Faggin]], [[Masatoshi Shima]], Stanley Mazor|title=MOS computer employing a plurality of separate chips}}. This patent contains three claims. The first two relate to the [[Intel 8080#Status word|status word]] multiplexed onto the data bus. The third claim is for the {{code|RST 7}} instruction which can be invoked by pulling the data bus high. The [[prior art]] 8008 {{code|RST 7}} required more complicated instruction jamming circuitry.

==Cultural impact==
* [[Asteroid]] [[8080 Intel]] is named as a pun in recognition of the role that Intel and its 8080 played in the PC revolution, which had a significant impact on the field of astronomy.<ref>{{cite web |title=(8080) Intel = 1958 QC = 1987 WU2 = 1989 AS5 |url=https://minorplanetcenter.net/db_search/show_object?object_id=8080 |website=Minor Planet Center |publisher=International Astronomical Union |access-date=14 November 2021 |archive-date=September 25, 2019 |archive-url=https://web.archive.org/web/20190925141642/https://minorplanetcenter.net/db_search/show_object?object_id=8080 |url-status=live }}</ref>
* Microsoft's published phone number, 425-882-8080, was chosen because much early work was on this chip.
* Many of Intel's main phone numbers also take a similar form: xxx-xxx-8080

==See also==
* [[CP/M]] – operating system
* [[S-100 bus]]
* [[MPT8080]]
* [[Intellec 8 Mod 80]]

==References==
{{reflist}}

==Further reading==
* {{cite book|title=8080A/8085 Assembly Language Programming |edition=1st |first1=Lance |last1=Leventhal |publisher= [[Osborne/McGraw-Hill]] |year=1978 |url=https://archive.org/details/8080a80850000leva }}; 495 pages
* {{cite book|title=8080/Z80 Assembly Language – Techniques for Improved Programming |edition=1st |first=Alan |last=Miller |publisher=[[John Wiley & Sons]] |year=1981 |isbn=978-0471081241 |url=https://archive.org/details/8080_and_Z-80_Assembly_Language_Techniques_1981_John_Wiley_and_Sons/ }}; 332 pages
* {{cite book|title=Microprocessor Interfacing Techniques |edition=3rd |first1=Rodnay |last1=Zaks |first2=Austin |last2=Lesea |publisher=[[Sybex]] |year=1979 |isbn=978-0-89588-029-1|url=https://archive.org/details/MicroprocessorInterfacingTechniques_3rd_ed/ }}; 466 pages
* {{cite book| title=Z80 and 8080 Assembly Language Programming |edition=1st |first1=Kathe |last1=Spracklen|publisher=[[Hayden Publishing|Hayden]] |year=1979 |isbn=978-0810451674 |url=https://archive.org/details/z808080assemblyl00kath/ }}; 180 pages

==External links==
* [http://www.cpu-collection.de/?tn=0&l0=cl&l1=8080 Intel and other manufacturers' 8080 CPU images and descriptions at cpu-collection.de] {{Webarchive|url=https://web.archive.org/web/20061011123653/http://www.cpu-collection.de/?tn=0&l0=cl&l1=8080 |date=October 11, 2006 }}
* [https://web.archive.org/web/20070928060215/http://www.datasheetarchive.com/search.php?q=8080 Scan of the Intel 8080 data book at DataSheetArchive.com]
* [http://donbot.com/MicrocomputerDesign/SE/M001.html Microcomputer Design, Second Edition, 1976] {{Webarchive|url=https://web.archive.org/web/20120311032333/http://donbot.com/MicrocomputerDesign/SE/M001.html |date=March 11, 2012 }}
* [http://www.bluishcoder.co.nz/js8080/ 8080 Emulator written in JavaScript] {{Webarchive|url=https://web.archive.org/web/20100317080605/http://www.bluishcoder.co.nz/js8080/ |date=March 17, 2010 }}
* [https://github.com/begoon/i8080-js/ Intel 8080/KR580VM80A emulator in JavaScript] {{Webarchive|url=https://web.archive.org/web/20180611025338/https://github.com/begoon/i8080-js |date=June 11, 2018 }}
* [http://www.nj7p.info/Manuals/PDFs/Intel/9800153B.pdf Intel 8080 Microcomputer Systems User's Manual (September 1975, 262 pages)] {{Webarchive|url=https://web.archive.org/web/20180310201916/http://www.nj7p.info/Manuals/PDFs/Intel/9800153B.pdf |date=March 10, 2018 }}
* [http://www.elenota.pl/datasheet-pdf/133557/Intel/8080 Intel 8080 Microcomputer Systems User's Manual (September 1975, 234 pages)] {{Webarchive|url=https://web.archive.org/web/20130226005332/http://www.elenota.pl/datasheet-pdf/133557/Intel/8080 |date=February 26, 2013 }}
* [https://sbc-85.com/download/8085-reference-card-hex/ Intel 8080/8085 Instruction Reference Card] {{Webarchive|url=https://web.archive.org/web/20210810014546/https://sbc-85.com/download/8085-reference-card-hex/ |date=August 10, 2021 }}

{{Intel processors|discontinued}}

{{Authority control}}

[[Category:Intel microprocessors|8080]]
[[Category:8-bit microprocessors]]
[[Category:Computer-related introductions in 1974]]