View source for LEON

{{Short description|32-bit CPU microprocessor core originally designed by the European Space Agency}}
{{About|the family of microprocessors|other uses|Leon (disambiguation)}}
{{primary sources|date=November 2012}}
{{Infobox CPU
| name           = LEON
| image          = 
| image_size     = 
| caption        = 
| produced-start = {{Start date and age|1997}}
| produced-end   = 
| slowest        = 150
| fastest        = 1500
| slow-unit      = MHz<ref name="eval-board">{{cite web|url=http://microelectronics.esa.int/gr740/NGFP-BPROD-0017-i1r0.pdf|title=Quad-Core LEON4 Next-Generation Microprocessor Evaluation Board GR-CPCI-LEON4-N2X|publisher=Aeroflex Gaisler AB}}</ref>
| fast-unit      = MHz<ref name="gaisler-leon4">{{cite web|url=https://www.gaisler.com/index.php/products/processors/leon4|title=LEON4 Processor|publisher=Cobham Gaisler Plc.|access-date=2021-01-12|quote=Up to 150 MHz in FPGA and 1500 MHz on 32 nm ASIC}}</ref>
| fsb-slowest    = 
| fsb-fastest    = 
| fsb-slow-unit  = 
| fsb-fast-unit  = 
| size-from      = 
| size-to        = 
| soldby         = [[Airbus Defence and Space]]
| designfirm     = [[Sun Microsystems]] (acquired by [[Oracle Corporation]])<br><small>([[instruction set]], original design{{Clarify|reason=Original instruction set design, or original processor design?|date=March 2020}})</small><br>[[European Space Agency]] (ESA)<br>[[Gaisler Research]]<br><small>(processor, design derivative{{Clarify|reason=Instruction set is derived from SPARC V8, with changes, or processor design is derived from some chip design by Sun?|date=March 2020}})</small>
| manuf1         = [[Atmel]] (acquired by [[Microchip Technology]])
| core1          = 
| sock1          = 
| pack1          =
| arch           = [[SPARC]] V8
| microarch      = 
| numcores       = 1
| predecessor    = [[ERC32]]
}}
'''LEON''' (from {{langx|es|león}} meaning [[lion]]) is a [[radiation hardening|radiation-tolerant]] [[32-bit computing|32-bit]] [[central processing unit]] (CPU) [[microprocessor]] core that implements the [[SPARC]] V8 [[instruction set architecture]] (ISA) developed by [[Sun Microsystems]]. It was originally designed by the [[European Space Research and Technology Centre]] (ESTEC), part of the [[European Space Agency]] (ESA), without any involvement by Sun. Later versions have been designed by [[Gaisler Research]], under a variety of owners. It is described in synthesizable VHSIC Hardware Description Language ([[VHDL]]). LEON has a dual license model: An [[GNU Lesser General Public License]] (LGPL) and [[GNU General Public License]] (GPL) [[free and open-source software]] (FOSS) license that can be used without licensing fee, or a proprietary license that can be purchased for integration in a proprietary product.<ref>{{cite news |last=Clarke |first=Peter |date=2000-03-06 |url=https://www.eetimes.com/european-space-agency-launches-free-sparc-like-core/ |title=European Space Agency launches free SPARC-like core |website=[[EE Times]]}}</ref><ref>{{cite news |last=Clarke |first=Peter |date=2005-02-24 |url=https://www.eetimes.com/free-sparc-processor-developer-goes-commercial/ |title=Free SPARC processor developer goes "commercial" |website=EE Times}}</ref>
The core is configurable through VHDL generics, and is used in [[system on a chip]] (SOC) designs both in research and commercial settings.<ref>{{cite news |last=Staunton |first=Declan |date=<!-- Undated --> |url=https://www.design-reuse.com/articles/12145/successful-use-of-an-open-source-processor-in-a-commercial-asic.html |title=Successful Use of an Open Source Processor in a Commercial ASIC |website=Design & Reuse}}</ref>

==History==
The LEON project was begun by the European Space Agency (ESA) in late 1997 to study and develop a high-performance processor to be used in European space projects.<ref>{{cite conference |last1=Andersson |first1=J. |last2=Gaisler |first2=J. |last3=Weigand |first3=R. |year=2010 |title=Next Generation Multipurpose Microprocessor |conference=DAta Systems In Aerospace 2010 (DASIA2010) |url=http://microelectronics.esa.int/gr740/NGMP-DASIA10-Paper.pdf |access-date=2020-03-17}}</ref>
The objectives for the project were to provide an open, portable and non-proprietary processor design, capable to meet future requirements for performance, software compatibility and low system cost. Another objective was to be able to manufacture in a [[single-event upset]] (SEU) tolerant sensitive semiconductor process. To maintain correct operation in the presence of SEUs, extensive error detection and error handling functions were needed. The goals have been to detect and tolerate one error in any register without software intervention, and to suppress effects from Single Event Transient (SET) errors in combinational logic.

The LEON family includes the first LEON1 VHSIC Hardware Description Language (VHDL) design that was used in the LEONExpress test chip developed in 0.25 μm technology to prove the fault-tolerance concept. The second LEON2 VHDL design was used in the processor device AT697 from Atmel (F) and various system-on-chip devices. These two LEON implementations were developed by ESA. Gaisler Research, now part of Frontgrade (previously Aeroflex and [[Cobham plc|Cobham]]), developed the third LEON3 design and has announced the availability of the fourth generation LEON, the LEON4 processor.<ref name="gaisler1">{{cite press release|publisher=Aeroflex Gaisler|url=https://www.gaisler.com/index.php/newsevents/news-2010/337-27th-january-2010|title=Aeroflex Gaisler announces the next generation LEON processor|date=2010-01-27}}</ref>

==LEON processor models and distributions==
A LEON processor can be implemented in [[programmable logic device|programmable logic]] such as a [[field-programmable gate array]] (FPGA) or manufactured into an [[application-specific integrated circuit]] (ASIC). This section and the subsequent subsections focus on the LEON processors as soft [[IP core]]s and summarise the main features of each processor version and the infrastructure with which the processor is packaged, referred to as a LEON ''distribution''.

All processors in the LEON series use the SPARC V8 [[reduced instruction set computer]] (RISC) ISA. LEON2(-FT) has a five-stage [[Pipeline (computing)|pipeline]] while later versions have a seven-stage pipeline. LEON2 and LEON2-FT are distributed as a system-on-chip design that can be modified using a graphical configuration tool. While the LEON2(-FT) design can be extended and re-used in other designs, its structure does not emphasise re-using parts of the design as building blocks or enable designers to easily incorporate new IP cores in the design.

The standard LEON2(-FT) distribution includes the following support cores:<ref name="leon2-ft">{{cite web|website=European Space Agency|url=http://www.esa.int/TEC/Microelectronics/SEMUD70CYTE_0.html|title=LEON2-FT}}</ref>
* [[Interrupt controller]]
* Debug support unit with trace buffer
* Two [[24-bit computing|24-bit]] [[timer]]s
* Two [[universal asynchronous receiver-transmitter]]s (UARTs)
* [[16-bit computing|16-bit]] [[memory-mapped I/O|I/O port]]
* [[Memory controller]].

The LEON3, LEON3FT, and LEON4 cores are typically used together with the GRLIB IP Library. While the LEON2 distributions contain one design that can be used on several target technologies, GRLIB contains several template designs, both for [[FPGA]] development boards and for [[Application-specific integrated circuit|ASIC]] targets that can be modified using a graphical configuration tool similar to the one in the LEON2 distribution. The LEON/GRLIB package contains a larger number of cores compared to the LEON2 distributions and also include a [[plug and play]] (PnP) extension to the on-chip [[Advanced Microcontroller Bus Architecture]] (AMBA) bus. IP cores available in GRLIB also include:<ref>{{cite web |url=https://www.gaisler.com/index.php/products/ipcores/soclibrary |title=GRLIB IP Library |website=Cobham Gaisler |access-date=2020-03-17}}</ref>

* 32-bit PC133 [[synchronous dynamic random-access memory]] (SDRAM) controller
* 32-bit [[Peripheral Component Interconnect]] (PCI) bridge with [[direct memory access]] (DMA)
* 10/100/1000 Mbit [[Ethernet]] media access control address ([[MAC address]])
* 8/16/32-bit [[programmable read-only memory]] (PROM) and [[static random-access memory]] (SRAM) controller
* 16/32/64-bit DDR/DDR2 controllers
* Universal Serial Bus ([[USB]]) 2.0 host and device controllers
* [[Controller area network]] (CAN) controller
* [[JTAG|JTAG TAP]] controller
* [[Serial Peripheral Interface]] (SPI) controller
* Inter-Integrated Circuit ([[I²C]]) controller
* [[Universal asynchronous receiver-transmitter]] (UART) with first in, first out ([[FIFO (computing and electronics)|FIFO]])
* Modular timer unit
* Interrupt controller
* 32-bit [[general-purpose I/O]] (GPIO) port

===FPGA design flow===
Design flow documentation for the LEON into FPGA are available from the manufacturer<ref>{{cite web |website=Cobham Gaisler |url=https://www.gaisler.com/products/grlib/grlib.pdf |title=GRLIB IP Library User's Manual |date=November 2019}}</ref> and from third party resources.<ref>{{cite web |last=Buttelmann |first=Lutz |url=http://www.buttelmann.de/Leon/leon3_simulation_guide_0_2.pdf |title=How to setup LEON3 VHDL simulation with Modelsim |archive-url=https://web.archive.org/web/20160304063320/http://www.buttelmann.de/Leon/leon3_simulation_guide_0_2.pdf |archive-date=2016-03-04}}</ref>

===Terminology===
The term LEON2/LEON2-FT often refer to the LEON2 system-on-chip design, which is the LEON2 processor core together with the standard set of peripherals available in the LEON2(-FT) distribution. Later processors in the LEON series are used in a wide range of designs and are therefore not as tightly coupled with a standard set of peripherals. With LEON3 and LEON4 the name typically refers to only the processor core, while LEON/GRLIB is used to refer to the complete system-on-chip design.

===LEON2 processor core===
LEON2 has the following characteristics:

* The [[GNU Lesser General Public License|GNU LGPL]] allows a high degree of freedom of intervention on the freely available source code.
* Configurability is a key feature of the project,<ref>{{cite web|website=ESA Microelectronics|url=http://microelectronics.esa.int/soc/soc.htm|title=System-On-Chip (SOC) Development}}</ref> and is achieved through the usage of VHDL generics.<ref>{{cite web|website=Gaisler Research|url=http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=13&Itemid=53|title=Leon3 processor|archive-url=https://web.archive.org/web/20070628170808/http://www.gaisler.com/cms/index.php?option=com_content&task=view&id=13&Itemid=53|archive-date=2007-06-28}}</ref>
* It offers all basic functions of a pipelined in-order processor.
* It is a fairly sized VHDL project (about 90 files, for the complete LEON2 distribution, including peripheral IP cores)

===LEON2-FT processor core===
The LEON2-FT processor is the [[single-event upset]] [[fault tolerant]] (FT) version of the LEON2 processor. Flip-flops are protected by [[triple modular redundancy]] and all internal and external memories are protected by [[Error detection and correction#Error-correcting memory|EDAC]] or [[parity bit]]s. Special licence restrictions apply to this IP (distributed by the European Space Agency<ref name="leon2-ft"/>). Among other satellites, the processor was used in ESA's [[Intermediate eXperimental Vehicle]] (IXV) in 2015<ref>{{cite web|url=https://www.spacedaily.com/reports/LEON_the_space_chip_that_Europe_built_999.html|title=LEON: the space chip that Europe built|website=SpaceDaily|date=2013-01-10}}</ref> and China's [[Chang'e 4]] lunar lander.<ref>{{Cite web|url=http://www.esa.int/spaceinimages/Images/2019/07/Chang_e-4_lander|title=Chang'e-4 lander|website=European Space Agency|language=en-GB|access-date=2019-07-18}}</ref>

===LEON3 processor core===
The LEON3 is a synthesisable VHDL  model of a 32-bit  processor compliant with the SPARC V8 architecture. The model is highly configurable, and particularly suitable for system-on-a-chip ([[System-on-a-chip|SoC]])  designs. The full source code is available under the GNU GPL license, allowing use for any purpose without licensing fee. LEON3 is also available  under a proprietary license, allowing it to be used in proprietary applications.

There are several differences between the two LEON2 processor models and the LEON3. LEON3 includes [[Symmetric multiprocessing|SMP]] support and a seven-stage pipeline, while LEON2 does not support SMP and has a five-stage pipeline.

===LEON3FT processor core===
The LEON3FT is a fault-tolerant version of the standard LEON3 SPARC V8 Processor. It has been designed for operation in the harsh space environment, and includes functionality to detect and correct [[single-event upset]] (SEU) errors in all on-chip RAM memories. The LEON3FT processor supports most of the functionality in the standard LEON3 processor, and adds the following features:

* [[Register file]] SEU error-correction of up to 4 errors per 32-bit word
* [[Cache memory]] error-correction of up to 4 errors per tag or 32-bit word
* Autonomous and software transparent error handling
* No timing impact due to error detection or correction

The following features of the standard LEON3 processor are not supported by LEON3FT

* Local [[scratchpad RAM]] (neither for instruction nor for data)
* [[Cache locking]]
* LRR (least recently replaced) [[Cache algorithms|cache replacement algorithm]]

The LEON3FT core is distributed together with a special FT version of the GRLIP IP library. Only netlist distribution is possible.

An FPGA implementation called [https://gaisler.com/index.php/products/components/84-components/196-leon3ft-rtax7 LEON3FT-RTAX] was proposed for critical space applications.,<ref>{{cite web|website=Frontgrade Gaisler|url=https://gaisler.com/index.php/products/components/84-components/196-leon3ft-rtax7|title=LEON3FT-RTAX Fault-tolerant Processor|access-date=2023-06-01}}</ref> but it has been discontinued.

===LEON4 processor core===
In January 2010, the fourth version of the LEON processor was released.<ref name="gaisler1"/> This release has the following new features:
* Static [[branch prediction]] added to pipeline
* Optional level-2 cache
* 64-bit or 128-bit path to [[AMBA High-performance Bus#Advanced High-performance Bus .28AHB.29|AMBA AHB]] interface
* Higher performance possible (claimed by manufacturer: 1.7 [[DMIPS]]/MHz as opposed to 1.4 DMIPS/MHz of LEON3)
* Rad hardened.<ref name="eval-board"/>

===LEON5 processor core===

== Real-time OS support ==
The [[Real-time operating system]]s that support the LEON core are currently [[RTLinux]], [[PikeOS]], [[eCos]], [[RTEMS]], Nucleus, [[ThreadX]], [[OpenComRTOS]], [[VxWorks]] (a port by Gaisler Research), [[LynxOS]] (also a port by Gaisler Research), POK<ref>{{cite web|url=https://pok-kernel.github.io|title=POK, a real-time kernel for secure embedded systems}}</ref> (a free [[ARINC 653|ARINC653]] implementation released under the BSD licence) and ORK+,<ref>{{cite web|url=http://www.dit.upm.es/~ork/index.html/|title=ORK+|website=STRAST group|access-date=2014-11-13|archive-date=2022-04-07|archive-url=https://web.archive.org/web/20220407082551/http://www.dit.upm.es/~ork/index.html/|url-status=dead}}</ref> an open-source real-time kernel for high-integrity real-time applications with the [[Ravenscar profile|Ravenscar Profile]], Embox<ref>{{cite web|url=http://embox.github.io|title=Embox {{!}} Real-time operating system}}</ref> an open-source configurable real-time OS which allows using Linux software without Linux.

==See also==
{{Portal|Free and open-source software}}
*[[OpenSPARC]]
*[[S1 Core]]
*[[OpenRISC]]
*[[ERC32]]
*[[FeiTeng-1000]]
*[[Soft microprocessor]]
*[[Schiaparelli EDM lander]]

==References==
{{Reflist|30em}}

==External links==
*[http://www.gaisler.com/ Cobham Gaisler]
*[http://microelectronics.esa.int/gr740/ GR740]: The ESA Next Generation Microprocessor (NGMP)
*[https://www.cobhamaes.com/products/radiation-hardened-solutions-high-reliability-components Cobham: Radiation Hardened Solutions and High Reliability Components] {{Webarchive|url=https://web.archive.org/web/20210303024235/https://www.cobhamaes.com/products/radiation-hardened-solutions-high-reliability-components |date=2021-03-03 }}
*[http://www.rte.se/blog/blogg-modesty-corex/leon3-soft-processor LEON3 tutorial]
*[http://tldp.org/HOWTO/html_single/SPARC-HOWTO/#ss2.6 GNU/Linux on the SPARC architecture with original port on LEON]

{{Soft microprocessors}}
{{RISC architectures}}
{{Programmable logic}}

{{DEFAULTSORT:Leon}}
[[Category:Embedded microprocessors]]
[[Category:European Space Agency]]
[[Category:Radiation-hardened microprocessors]]
[[Category:Open microprocessors]]
[[Category:Soft microprocessors]]
[[Category:SPARC microprocessors]]