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{{More footnotes needed|date=June 2013}}
{{Use dmy dates|date=October 2018}}
{{Infobox company
 |name = Meiko Scientific Ltd.
 |logo = Meiko Scientific logo.svg
 |type = [[Private company|Private]]
 |industry = [[Computer hardware]]
 |founders = Miles Chesney<br/>David Alden<br/>Gerry Talbot<br/>Roy Bottomley<br/>Eric Barton<br/>James Cownie
 |founded = {{Start date and age|1985|03}}
 |hq_location_city = [[Bristol]]
 |hq_location_country = [[United Kingdom]]
 |key_people = Miles Chesney, [[Chief executive officer|Managing Director]]<br/>David Alden, [[Chief Financial Officer|Finance Director]]<br/>Gerry Talbot<br/>Roy Bottomley<br/>Eric Barton<br/>James Cownie
 |products = 
 |website = {{URL|www.meiko.com}}
}}

'''Meiko Scientific Ltd.''' was a British [[supercomputer]] company based in [[Bristol]], founded by members of the design team working on the [[Inmos]] [[transputer]] [[microprocessor]].

==History==
In 1985, when Inmos management suggested the release of the transputer be delayed, Miles Chesney, David Alden, Eric Barton, Roy Bottomley, James Cownie, and Gerry Talbot resigned and formed Meiko ([[Japanese language|Japanese]] for "well-engineered") to start work on [[massively parallel]] machines based on the processor. Nine weeks later in July 1985, they demonstrated a transputer system based on experimental [[16-bit computing|16-bit]] transputers at the [[SIGGRAPH]] in San Francisco.

In 1986, a system based on [[32-bit computing|32-bit]] T414 transputers was launched as the ''Meiko Computing Surface''. By 1990, Meiko had sold more than 300 systems and grown to 125 employees. In 1993, Meiko launched the second-generation ''Meiko CS-2'' system, but the company ran into financial difficulties in the mid-1990s. The technical team and technology was transferred to a joint venture company named [[Quadrics (company)|Quadrics Supercomputers World Ltd.]] (QSW), formed by [[Thales Alenia Space|Alenia Spazio]] of [[Italy]] in mid-1996. At Quadrics, the CS-2 interconnect technology was developed into [[QsNet]].

{{As of|2021}}, a vestigial Meiko website still exists.<ref>{{Cite web |url=http://www.meiko.com/ |title=Meiko website}}</ref>

==Computing Surface==
The Meiko Computing Surface (sometimes retrospectively referred to as the CS-1) was a [[massively parallel]] [[supercomputer]]. The system was based on the [[Inmos]] [[transputer]] [[microprocessor]], later also using [[SPARC]] and [[Intel i860]] processors.<ref>{{Citation |url=http://www.textfiles.com/bitsavers/pdf/meiko/brochures/In-Sun_Computing_Surface_Brochure_1989.pdf |archive-url=https://web.archive.org/web/20141209165934/http://www.textfiles.com/bitsavers/pdf/meiko/brochures/In-Sun_Computing_Surface_Brochure_1989.pdf |archive-date=2014-12-09 |url-status=live |title=Computing Surface Brochure |publisher=Meiko |year=1989}}</ref><ref>{{Cite book |editor1-last=Trew |editor1-first=Arthur |editor2-last=Wilson |editor2-first=Greg |year=1991 |title=Past, Present, Parallel: A Survey of Available Parallel Computing Systems |place=New York |publisher=Springer-Verlag |isbn=0-387-19664-1}}</ref>

The Computing Surface architecture comprised multiple boards containing transputers connected together by their communications links via Meiko-designed link switch chips. A variety of different boards were produced with different transputer variants, [[random-access memory]] (RAM) capacities and peripherals.

The initial software environments provided for the Computing Surface was ''[[Occam (programming language)|Occam]] Programming System'' (OPS), Meiko's version of Inmos's D700 Transputer Development System. This was soon superseded by a [[multi-user]] version, ''MultiOPS''. Later, Meiko introduced ''Meiko Multiple Virtual Computing Surfaces'' (M²VCS), a multi-user resource management system let the processors of a Computing Surface be partitioned into several ''domains'' of different sizes. These domains were allocated by M²VCS to individual users, thus allowing several simultaneous users access to their own virtual Computing Surfaces. M²VCS was used in conjunction with either OPS or ''MeikOS'', a [[Unix-like]] single-processor [[operating system]].

In 1988, Meiko launched the In-Sun Computing Surface, which repackaged the Computing Surface into [[VMEbus]] boards (designated the MK200 series) suitable for installation in larger [[Sun-3]] or [[Sun-4]] systems. The Sun acted as ''front-end'' host system for managing the transputers, running development tools and providing mass storage. A version of M²VCS running as a [[SunOS]] [[Daemon (computing)|daemon]] named ''Sun Virtual Computing Surfaces'' (SVCS) provided access between the transputer network and the Sun host.

As the performance of the transputer became less competitive toward the end of the 1980s (the follow-on T9000 transputer being beset with delays), Meiko added the ability to supplement the transputers with Intel i860 processors. Each i860 board (MK086 or MK096) contained two i860s with up to 32&nbsp;MB of RAM each, and two T800s providing inter-processor communication. Sometimes known as the Concerto or simply the i860 Computing Surface, these systems had limited success.

Meiko also produced a SPARC processor board, the MK083, which allowed the integration of the [[SunOS]] operating system into the Computing Surface architecture, similarly to the In-Sun Computing Surface. These were usually used as front-end host processors for transputer or i860 Computing Surfaces. SVCS, or an improved version, called simply ''VCS'' was used to manage the transputer resources. Computing Surface configurations with multiple MK083 boards were also possible.

A major drawback of the Computing Surface architecture was poor [[Input/Output|I/O]] [[Bandwidth (computing)|bandwidth]] for general data shuffling. Although aggregate bandwidth for special case data shuffling could be very high, the general case has very poor performance relative to the compute bandwidth. This made the Meiko Computing Surface uneconomic for many applications.

===MeikOS===
{{Infobox OS
| name = MeikOS
| logo = <!-- Filename only: no wikilink, Image: or File: -->
| logo caption = 
| logo alt = 
| screenshot = <!-- Filename only: no wikilink, Image: or File: -->
| caption = 
| screenshot_alt = 
| developer = Meiko Scientific
| family = [[Unix-like]]
| working state = Discontinued
| source model = [[Closed-source]]
| released = {{Start date and age|1987}}<!-- If known, add |mm|dd|df=yes -->
| discontinued = Yes
| latest release version = 3.06
| latest release date = {{Start date and age|1991}}<!-- If known, add |mm|dd|df=yes -->
| marketing target = Research
| programmed in = 
| language = English
| update model = Compile from [[source code]]
| supported platforms = [[Transputer]]
| kernel type = [[Microkernel]]
| userland = 
| ui = [[Command line interface]]
| license = 
| preceded by = [[MINIX]]
| succeeded by = 
| website = <!-- {{URL|www.example.org}} -->
| other articles = 
}}
MeikOS (also written as ''Meikos'' or ''MEiKOS'') is a [[Unix-like]] transputer [[operating system]] developed for the Computing Surface during the late 1980s.

MeikOS was derived from an early version of [[Minix]], extensively modified for the Computing Surface architecture. Unlike [[HeliOS]], another Unix-like transputer operating system, MeikOS is essentially a single-processor operating system with a distributed [[file system]]. MeikOS was intended for use with the ''Meiko Multiple Virtual Computing Surfaces'' (M²VCS) resource management software, which partitions the processors of a Computing Surface into ''domains'', manages user access to these domains, and provides inter-domain communication.

MeikOS has ''[[diskless]]'' and ''fileserver'' variants, the former running on the seat processor of an M²VCS domain, providing a [[command line]] user interface for a given user; the latter running on processors with attached [[SCSI]] hard disks, providing a remote file service (named ''Surface File System'' (SFS)) to instances of diskless MeikOS. The two can communicate via M²VCS.

MeikOS was made obsolete by the introduction of the In-Sun Computing Surface and the Meiko MK083 [[SPARC]] processor board, which allow [[SunOS]] and ''Sun Virtual Computing Surfaces'' (SVCS), later developed as ''VCS'' to take over the roles of MeikOS and M²VCS respectively. The last MeikOS release was MeikOS 3.06, in early 1991.

===CS-1 Interconnect===
This was based on the [[transputer]] link protocol. Meiko developed its own switch silicon on and European Silicon Systems, ES2 [[gate array]]. This [[application-specific integrated circuit]] (ASIC) provided static connectivity and limited dynamic connectivity and was designed by Moray McLaren.

==CS-2==
The CS-2<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/brochures/CS-2_Product_Description.pdf CS-2 Product Description] Meiko; 1993</ref><ref>[https://web.archive.org/web/20010709110330/http://www.top500.org/ORSC/1998/cs-2.html Top500 description of the CS-2] Top500.org; 1998</ref><ref>''CS-2: Predatory Computing Performance'', Meiko Limited; 1992</ref> was launched in 1993 and was Meiko's second-generation system architecture, superseding the earlier Computing Surface.

The CS-2 was an all-new modular architecture based around [[SPARC|SuperSPARC]] or [[hyperSPARC]] processors<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/cs-2/CS-2_Hardware_Reference_Manuals_1995.pdf CS-2_Hardware_Reference_Manuals] Meiko; 1995</ref> and, optionally, [[Fujitsu]] μVP [[vector processor]]s.<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/cs-2/MK403.pdf MK403 Manual] Meiko; 1993</ref> These implemented an instruction set similar to the [[Fujitsu VP2000]] vector supercomputer and had a nominal performance of 200 [[megaflops]] on [[double precision]] arithmetic and double that on [[single precision]]. The SuperSPARC processors ran at 40&nbsp;MHz initially, later increased to 50&nbsp;MHz. Subsequently, hyperSPARC processors were introduced at 66, 90 or 100&nbsp;MHz. The CS-2 was intended to scale up to 1024 processors. The largest CS-2 system built was a 224-processor system<ref>{{cite web
|url=http://www.top500.org/system/1607
|title=CS-2/224 at Lawrence Livermore National Laboratory
}}</ref> installed at [[Lawrence Livermore National Laboratory]].

The CS-2 ran a customized version of Sun's operating system [[Solaris (operating system)|Solaris]], initially Solaris 2.1, later 2.3 and 2.5.1.

===Elan-Elite Interconnect===
The processors in a CS-2 were connected by a Meiko-designed multi-stage packet-switched ''[[fat tree]]'' network implemented in custom silicon.<ref>[http://portal.acm.org/citation.cfm?id=196892 Meiko CS-2 Interconnect Elan-Elite design] Jon Beecroft, Fred Homewood, Moray McLaren; Journal Parallel Computing; Volume 20 Issue 10-11, November 1994</ref><ref>[http://dl.acm.org/citation.cfm?id=196892 Meiko CS-2 Interconnect Elan-Elite design] Fred Homewood, Moray McLaren; Hot Interconnects Conference, Stanford; August 1993</ref><ref>[http://www.netlib.org/utk/people/JackDongarra/journals/088_1997_message-passing-performance-of-various-computers.pdf Message Passing Performance] Jack Dongarra and Tom Dunigan; Concurrancy: Practice and Experience; October 1997</ref>

This project, codenamed Elan-Elite, was started in 1990, as a speculative project to compete with the T9000 [[Transputer]] from [[Inmos]], which Meiko intended to use as an interconnect technology. The [[Transputer|T9000]] began to suffer massive delays, such that the internal project became the only viable interconnect choice for the CS-2.

This interconnect comprised two devices, code-named ''Elan'' ([[Network interface controller|adapter]]) and ''Elite'' ([[Network switch|switch]]). Each processing element included an Elan chip, a communications co-processor based on the [[SPARC]] architecture, accessed via a [[MBus (SPARC)|Sun MBus]] [[cache coherence|cache coherent]] interface and providing two 50&nbsp;MB/s bi-directional links. The Elite chip was an 8-way link [[crossbar switch]], used to form the [[packet-switched network]]. The switch had limited adaption based on load and priority.<ref>[http://bitsavers.informatik.uni-stuttgart.de/pdf/meiko/cs-2/S1002-10M105.05_Communications_Network_Overview_1993.pdf Communications Network Overview] Meiko Limited; 1993</ref>

Both ASICs were fabbed in complementary metal–oxide–semiconductor ([[CMOS]]) gate arrays by [[GEC Plessey Telecommunications|GEC Plessey]] in their [[Roborough, South Hams|Roborough]], [[Plymouth]] semi-conductor fab in 1993.

After the Meiko technology was acquired by [[Quadrics (company)|Quadrics]], the Elan/Elite interconnect technology was developed into [[QsNet]].

==Meiko SPARC FPU==
Meiko had hired Fred (Mark) Homewood and Moray McLaren both of whom had been instrumental in the design of the [[Transputer#T8: floating point|T800]]. Together, they designed and developed an improved, higher performance [[Floating-point unit|FPU]] core, owned by Meiko. This was initially targeted at the [[Intel]] [[80387]] instruction set. An ongoing legal battle between Intel, [[AMD]] and others over the 80387 made it clear this project was a commercial non-starter. A chance discussion between McLaren and [[Andy Bechtolsheim]] while visiting [[Sun Microsystems]] to discuss licensing [[Solaris (operating system)|Solaris]] caused Meiko to re-target the design for [[SPARC]]. Meiko was able to turn around the core [[Floating-point unit|FPU]] design in a short time and [[LSI Corporation|LSI Logic]] fabbed a device for the [[SPARCstation 1]].

A major difference over the T800 FPU was that it fully implemented the [[IEEE floating point|IEEE 754 standard]] for computer arithmetic. This including all rounding modes, denormalised numbers and square root in hardware without taking any [[Exception handling|hardware exceptions]] to complete computation.

A [[SPARCstation 2]] design was also developed together with a combined part targeting the SPARCstation 2 ASIC pinout. LSI fabbed and manufactured the separate FPU L64814, as part of their SparKIT chipset.<ref>[http://www.hotchips.org/wp-content/uploads/hc_archives/hc03/2_Mon/HC3.S4/HC3.4.2.pdf SparKIT] HOTCHIPS 03, Stanford; August 1991</ref>

The Meiko design was eventually fully licensed to Sun which went on to use it in the [[MicroSPARC]] family of ASICs for several generations<ref>Sun Taps LSI For Low Cost SPARC design and fab; ''Computer Business Review''; 12 March 1997;</ref> in return for a one-off payment and full Solaris source license.

== References ==
{{Reflist}}

==External links==
* [https://web.archive.org/web/20001005071237/http://www.meiko.com/info/CorporateOverview.html Meiko corporate overview (via Internet Archive)]
* [https://web.archive.org/web/20021201043305/http://www.npac.syr.edu/nse/hpccsurvey/orgs/meiko/meiko.html Meiko (Survey of High Performance Computing Systems)]
*[https://web.archive.org/web/20070724093305/http://gpmimd2.web.cern.ch/GPMIMD2/papers/hepix96/hepix.html E. McIntosh and B. Panzer-Steindel. ''Parallel Processing at CERN''. Presented at HEPiX96 Caspur Rome, October 1996.]
*[http://bitsavers.org/pdf/meiko Meiko documentation] at bitsavers.org

{{Unix-like}}
{{Microkernel}}
{{Operating systems}}

[[Category:Supercomputers]]
[[Category:Massively parallel computers]]
[[Category:Defunct computer companies of the United Kingdom]]
[[Category:British companies established in 1985]]
[[Category:Companies disestablished in 1996]]
[[Category:Microkernel-based operating systems]]
[[Category:Microkernels]]
[[Category:Defunct computer hardware companies]]