View source for Moore's law

{{Short description|Observation on the growth of integrated circuit capacity}}
{{use mdy dates |date=July 2023}}
[[File:Moore's Law Transistor Count 1970-2020.png|thumb|upright=2.6|A [[semi-log plot]] of [[transistor count]]s for [[microprocessor]]s against dates of introduction, nearly doubling every two years |alt=refer to caption]]
{{Semiconductor manufacturing processes}}
{{Futures studies}}

'''Moore's law''' is the observation that the [[Transistor count|number of transistors]] in an [[integrated circuit]] (IC) doubles about every two years. Moore's law is an [[observation]] and [[Forecasting|projection]] of a historical trend. Rather than a [[law of physics]], it is an [[empirical relationship]]. It is an [[experience curve effect]], a type of observation quantifying efficiency gains from learned experience in production.

The observation is named after [[Gordon Moore]], the co-founder of [[Fairchild Semiconductor]] and [[Intel]] and former Chief Executive Officer of the latter, who in 1965 noted that the number of components per integrated circuit had been [[exponential growth|doubling every year]],{{efn|The trend begins with the invention of the integrated circuit in 1958. See the graph on the bottom of page&nbsp;3 of Moore's original presentation of the idea.<ref name="Moore 1965"/>}} and projected this rate of growth would continue for at least another decade. In 1975, looking forward to the next decade, he revised the forecast to doubling every two years, a [[compound annual growth rate]] (CAGR) of 41%. Moore's empirical evidence did not directly imply that the historical trend would continue; nevertheless, his prediction has held since 1975 and has since become known as a ''law''.

Moore's prediction has been used in the [[semiconductor industry]] to guide long-term planning and to set targets for [[research and development]] (R&D). Advancements in [[digital electronics]], such as the reduction in [[Price index#Quality change|quality-adjusted prices]] of [[microprocessor]]s, the increase in [[Computer memory|memory capacity]] ([[RAM|Random Access Memory]] and [[flash memory|flash]]), the improvement of [[digital sensor|sensors]], and even the number and size of [[pixel]]s in [[digital camera]]s, are strongly linked to Moore's law. These ongoing changes in digital electronics have been a driving force of technological and social change, [[productivity]], and economic growth.

Industry experts have not reached a consensus on exactly when Moore's law will cease to apply. Microprocessor architects report that semiconductor advancement has slowed industry-wide since around 2010, slightly below the pace predicted by Moore's law. In September 2022, [[Nvidia]] CEO [[Jensen Huang]] considered Moore's law dead,<ref name="nvidia" /> while Intel's then CEO [[Pat Gelsinger]] had the opposite view.<ref name="intel" />

== History ==
In 1959, [[Douglas Engelbart]] studied the projected downscaling of integrated circuit (IC) size, publishing his results in the article "Microelectronics, and the Art of Similitude".<ref name=engelbart>{{cite book|last=Engelbart|first=Douglas C.|title=1960 IEEE International Solid-State Circuits Conference. Digest of Technical Papers |chapter=Microelectronics and the art of similitude |author-link=Douglas Engelbart|publisher=IEEE|date=Feb 12, 1960|volume=III |pages=76–77 |doi=10.1109/ISSCC.1960.1157297 }}</ref><ref name=markoff>{{cite news|last=Markoff|first=John|author-link=John Markoff|title=It's Moore's Law But Another Had The Idea First|url=https://www.nytimes.com/2005/04/18/technology/18moore.html|access-date=October 4, 2011|newspaper=The New York Times|date=April 18, 2005|archive-url=https://web.archive.org/web/20120304111901/http://www.nytimes.com/2005/04/18/technology/18moore.html|archive-date=March 4, 2012}}</ref><ref>{{cite news |url=https://www.nytimes.com/2009/09/01/science/01trans.html?ref=science |title=After the Transistor, a Leap into the Microcosm |newspaper=The New York Times |date=August 31, 2009 |access-date=2009-08-31 |first=John |last=Markoff|author-link=John Markoff}}</ref> Engelbart presented his findings at the 1960 [[International Solid-State Circuits Conference]], where Moore was present in the audience.<ref>{{cite news|last=Markoff|first=John|author-link=John Markoff|title=Smaller, Faster, Cheaper, Over: The Future of Computer Chips|url=https://www.nytimes.com/2015/09/27/technology/smaller-faster-cheaper-over-the-future-of-computer-chips.html|access-date=September 28, 2015|newspaper=The New York Times|date=September 27, 2015}}</ref>

In 1965, Gordon Moore, who at the time was working as the director of research and development at [[Fairchild Semiconductor]], was asked to contribute to the thirty-fifth-anniversary issue of ''[[Electronics (magazine)|Electronics]]'' magazine with a prediction on the future of the semiconductor components industry over the next ten years.<ref>{{cite book |last=Kovacich |first=Gerald L. |title=The Information Systems Security Officer's Guide: Establishing and Managing a Cyber Security Program |publisher=Butterworth-Heinemann |year=2016 |isbn=978-0-12-802190-3 |edition=3rd |location=Oxford |page=72 |language=en}}</ref> His response was a brief article entitled "Cramming more components onto integrated circuits".<ref name="Moore 1965" /><ref>{{cite web| year =2005| url =ftp://download.intel.com/museum/Moores_Law/Video-Transcripts/Excepts_A_Conversation_with_Gordon_Moore.pdf| title =Excerpts from a conversation with Gordon Moore: Moore's Law| page =1| publisher =[[Intel Corporation]]| archive-url =https://web.archive.org/web/20080218225540/http://download.intel.com/museum/Moores_Law/Video-Transcripts/Excepts_A_Conversation_with_Gordon_Moore.pdf| archive-date =2008-02-18| access-date =2020-04-01}}</ref>{{efn|In April 2005, Intel offered US$10,000 to purchase a copy of the original ''Electronics'' issue in which Moore's article appeared.<ref>{{cite web|url=https://www.zdnet.com/article/intel-offers-10000-for-moores-law-magazine/|title=Intel offers $10,000 for Moore's Law magazine|last=Kanellos|first=Michael|date=2005-04-11|publisher=ZDNET News.com|access-date=2013-06-21}}</ref> An engineer living in the United Kingdom was the first to find a copy and offer it to Intel.<ref>{{cite news|url=https://news.bbc.co.uk/2/hi/technology/4472549.stm|title=Moore's Law original issue found|date=2005-04-22|access-date=2012-08-26|work=[[BBC News|BBC News Online]]}}</ref>}} Within his editorial, he speculated that by 1975 it would be possible to contain as many as {{val|65,000}} components on a single quarter-square-inch (~&nbsp;{{val|1.6|u=cm2}}) semiconductor.

<blockquote>The complexity for minimum component costs has increased at a rate of roughly a factor of two per year. Certainly over the short term this rate can be expected to continue, if not to increase. Over the longer term, the rate of increase is a bit more uncertain, although there is no reason to believe it will not remain nearly constant for at least 10 years.<ref name="Moore 1965"/></blockquote>
[[File:The Moore's Law Update — for 128 years - 54181414828.jpg|center|thumb|upright=2.2|This graph demonstrates how Moore's law has largely held since about 1965 and how progress prior to 1965 was slower.]]
Moore posited a log–linear relationship between device complexity (higher circuit density at reduced cost) and time.<ref name=schaller>{{cite web|last1=Schaller|first1=Bob|title=The Origin, Nature, and Implications of 'MOORE'S LAW'|date=September 26, 1996|url=http://research.microsoft.com/en-us/um/people/gray/moore_law.html|access-date=September 10, 2014|publisher=Microsoft}}</ref><ref name="Tuomi2002">{{cite journal | doi = 10.5210/fm.v7i11.1000| title = The Lives and Death of Moore's Law| journal = First Monday| volume = 7| issue = 11| year = 2002| last1 = Tuomi | first1 = I. | doi-access = free}}</ref> In a 2015 interview, Moore noted of the 1965 article: "...&nbsp;I just did a wild extrapolation saying it's going to continue to double every year for the next 10 years."<ref name="Moore 2015a"/> One historian of the law cites [[Stigler's law of eponymy]], to introduce the fact that the regular doubling of components was known to many working in the field.<ref name="Tuomi2002"/>

In 1974, [[Robert H. Dennard]] at [[IBM]] recognized the rapid [[MOSFET]] scaling technology and formulated what became known as [[Dennard scaling]], which describes that as MOS transistors get smaller, their [[power density]] stays constant such that the power use remains in proportion with area.<ref name=cartesian/><ref>{{cite book |last1=Streetman | first1=Ben G. | author1-link=Ben G. Streetman |last2=Banerjee |first2=Sanjay Kumar |author2-link=Sanjay Banerjee | title=Solid state electronic devices | publisher=Pearson | location=Boston | year=2016 | isbn=978-1-292-06055-2 | oclc=908999844 | page=341}}</ref> Evidence from the semiconductor industry shows that this inverse relationship between power density and [[Density_(computer_storage)|areal density]] broke down in the mid-2000s.<ref name="Turing Award Lecture 2018"/>

At the 1975 [[IEEE International Electron Devices Meeting]], Moore revised his forecast rate,<ref name="Takahashi">{{cite news |last=Takahashi |first=Dean |date=April 18, 2005 |title=Forty years of Moore's law |newspaper=Seattle Times |location=San Jose, California |url=http://www.seattletimes.com/business/forty-years-of-moores-law/ |access-date=April 7, 2015 |quote=A decade later, he revised what had become known as Moore's Law: The number of transistors on a chip would double every two years.}}</ref><ref name="Moore 1975b"/> predicting semiconductor complexity would continue to double annually until about 1980, after which it would decrease to a rate of doubling approximately every two years.<ref name="Moore 1975b"/><ref name="Moore 2006">{{cite book |last=Moore |first=Gordon |editor-last=Brock |editor-first=David |title=Understanding Moore's Law: Four Decades of Innovation |publisher=Chemical Heritage Foundation |date=2006 |pages=67–84 |chapter=Chapter 7: Moore's law at 40 |chapter-url=http://www.chemheritage.org/Downloads/Publications/Books/Understanding-Moores-Law/Understanding-Moores-Law_Chapter-07.pdf |access-date=March 22, 2018 |isbn=978-0-941901-41-3|archive-url=https://web.archive.org/web/20160304050107/http://www.chemheritage.org/Downloads/Publications/Books/Understanding-Moores-Law/Understanding-Moores-Law_Chapter-07.pdf |archive-date=2016-03-04}}</ref><ref  name="Intel 2011-05">{{cite press release |title=Over 6 Decades of Continued Transistor Shrinkage, Innovation |url=http://www.intel.com/content/www/us/en/silicon-innovations/standards-22-nanometers-technology-backgrounder.html |archive-url=https://web.archive.org/web/20120617144740/http://www.intel.com/content/dam/www/public/us/en/documents/backgrounders/standards-22-nanometers-technology-backgrounder.pdf |archive-date=2012-06-17 |publisher=[[Intel Corporation]] |date=May 2011 |quote=1965: Moore's Law is born when Gordon Moore predicts that the number of transistors on a chip will double roughly every year (a decade later, in 1975, Moore published an update, revising the doubling period to every 2 years) |access-date=2023-03-25}}</ref> He outlined several contributing factors for this exponential behavior:<ref name="schaller"/><ref name="Tuomi2002"/>
* The advent of [[metal–oxide–semiconductor]] (MOS) technology
* The exponential rate of increase in die sizes, coupled with a decrease in defective densities, with the result that semiconductor manufacturers could work with larger areas without losing reduction yields
* Finer minimum dimensions
* What Moore called "circuit and device cleverness"

Shortly after 1975, [[Caltech]] professor [[Carver Mead]] popularized the term ''Moore's law''.<ref name="IntelInterview">{{cite book |title=Understanding Moore's law: four decades of innovation |date=2006 |publisher=Chemical Heritage Foundation |isbn=978-0-941901-41-3 |editor-last1=Brock |editor-first1=David C. |location=Philadelphia, Pennsylvania}}</ref><ref name="SSCSnewsletterSept06">in reference to [[Gordon E. Moore]]'s statements at the IEEE. {{cite web |date=September 2006 |title=Moore's Law – The Genius Lives On |url=http://www.ieee.org/sscs-news |archive-url=https://web.archive.org/web/20070713083830/http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2165&path=sscs%2F06Sept&file=Gelsinger.xml |archive-date=2007-07-13 |access-date=2006-11-22 |publisher=IEEE solid-state circuits society newsletter}}</ref> Moore's law eventually came to be widely accepted as a goal for the semiconductor industry, and it was cited by competitive semiconductor manufacturers as they strove to increase processing power. Moore viewed his eponymous law as surprising and optimistic: "Moore's law is a violation of [[Murphy's law]]. Everything gets better and better."<ref>{{cite news|url=http://economist.com/displaystory.cfm?story_id=3798505| title = Moore's Law at 40 – Happy birthday|date=2005-03-23| newspaper=The Economist| access-date = 2006-06-24}}</ref> The observation was even seen as a [[self-fulfilling prophecy]].<ref name=Disco1998/><ref>
{{cite web
 | url = http://www.theinquirer.net/inquirer/news/1014782/gordon-moore-aloha-moore-law
 | archive-url = https://web.archive.org/web/20091106055601/http://www.theinquirer.net/inquirer/news/1014782/gordon-moore-aloha-moore-law
 | archive-date = November 6, 2009
 | title = Gordon Moore Says Aloha to Moore's Law
 | publisher = the Inquirer
 | date = April 13, 2005
 | access-date = September 2, 2009
}}</ref>

The doubling period is often misquoted as 18 months because of a separate prediction by Moore's colleague, Intel executive [[David House (computer designer)|David House]].<ref>{{cite book |last1=Meador |first1=Dan |title=Building Data Science Solutions with Anaconda: A comprehensive starter guide to building robust and complete models |last2=Goldsmith |first2=Kevin |publisher=Packt Publishing Limited |year=2022 |isbn=978-1-80056-878-5 |location=Birmingham, UK |page=9 |language=en}}</ref> In 1975, House noted that Moore's revised law of doubling transistor count every 2 years in turn implied that computer chip performance would roughly double every 18 months,<ref>{{cite news |url=https://www.pressreader.com/usa/technowize-magazine/20170501/282445643992141 |title=The Immutable Connection between Moore's Law and Artificial Intelligence |newspaper=Technowize Magazine |date=May 2017  |access-date=2018-08-24}}</ref> with no increase in power consumption.<ref name="news.cnet.com">{{cite web |url=http://news.cnet.com/2100-1001-984051.html |title=Moore's Law to roll on for another decade |quote=Moore also affirmed he never said transistor count would double every 18 months, as is commonly said. Initially, he said transistors on a chip would double every year. He then recalibrated it to every two years in 1975. David House, an Intel executive at the time, noted that the changes would cause computer performance to double every 18 months. |access-date=2011-11-27}}</ref> Mathematically, Moore's law predicted that transistor count would double every 2 years due to shrinking transistor dimensions and other improvements.<ref>{{cite book |last1=Sandhie |first1=Zarin Tasnim |title=Beyond Binary Memory Circuits: Multiple-Valued Logic |last2=Ahmed |first2=Farid Uddin |last3=Chowdhury |first3=Masud H. |publisher=Springer Nature |year=2022 |isbn=978-3-031-16194-0 |location=Cham, Switzerland |page=1 |language=en}}</ref> As a consequence of shrinking dimensions, Dennard scaling predicted that power consumption per unit area would remain constant. Combining these effects, David House deduced that computer chip performance would roughly double every 18 months. Also due to Dennard scaling, this increased performance would not be accompanied by increased power, i.e., the energy-efficiency of [[silicon]]-based computer chips roughly doubles every 18 months. Dennard scaling ended in the 2000s.<ref name="Turing Award Lecture 2018"/> Koomey later showed that a similar rate of efficiency improvement predated silicon chips and Moore's law, for technologies such as vacuum tubes.

[[File:Osbourne Executive (34 365).jpg|thumb|upright=1.4|A 1982 [[Osborne Executive]] portable computer, with a 4&nbsp;MHz 8-bit [[Zilog Z80]] CPU, and a 2007 [[Apple Inc.|Apple]] [[iPhone]] with a 412&nbsp;MHz 32-bit [[ARM11]] CPU; the Executive has 100 times the weight, almost 500 times the volume, approximately 10 times the inflation-adjusted cost, and 1/100th the [[clock frequency]] of the [[smartphone]].|alt=Large early portable computer next to a modern smartphone]]

Microprocessor architects report that since around 2010, semiconductor advancement has slowed industry-wide below the pace predicted by Moore's law.<ref name="Turing Award Lecture 2018"/> [[Brian Krzanich]], the former CEO of Intel, cited Moore's 1975 revision as a precedent for the current deceleration, which results from technical challenges and is "a natural part of the history of Moore's law".<ref name="Bradshaw"/><ref name="Waters"/><ref name="Niccolai"/> The rate of improvement in physical dimensions known as Dennard scaling also ended in the mid-2000s. As a result, much of the semiconductor industry has shifted its focus to the needs of major computing applications rather than semiconductor scaling.<ref name=Disco1998/><ref>{{cite journal |last1=Conte |first1=Thomas M. |last2=Track |first2=Elie |last3=DeBenedictis |first3=Erik |date=December 2015 |title=Rebooting Computing: New Strategies for Technology Scaling |journal= Computer|volume=48 |issue=12 |pages=10–13 |doi=10.1109/MC.2015.363 |bibcode=2015Compr..48l..10C |s2cid=43750026 |quote=Year-over-year exponential computer performance scaling has ended. Complicating this is the coming disruption of the "technology escalator" underlying the industry: Moore's law.}}</ref><ref name="Turing Award Lecture 2018"/> Nevertheless, as of 2019, leading semiconductor manufacturers [[TSMC]] and [[Samsung Electronics]] claimed to keep pace with Moore's law<ref name="TSMC 2019Oct" /><ref name="Samsung 5nm in 2020" /><ref>{{cite web|title=Moore's Law is not Dead|url=https://www.tsmc.com/english/newsEvents/blog_article_20190814.htm|last1=Cheng|first1=Godfrey|date=14 August 2019|website=TSMC Blog|publisher=[[TSMC]]|access-date=18 August 2019}}</ref><ref>{{cite web|title=Moore's Law is Alive and Well – Charts show it may be dying at Intel, but others are picking up the slack|url=https://medium.com/predict/moores-law-is-alive-and-well-adc010ea7a63|last1=Martin|first1=Eric|date=4 June 2019|website=[[Medium (website)|Medium]]|access-date=19 July 2019|archive-date=25 August 2019|archive-url=https://web.archive.org/web/20190825131253/https://medium.com/predict/moores-law-is-alive-and-well-adc010ea7a63}}</ref><ref>{{cite news|date=24 June 2019|title=5nm Vs. 3nm|work=Semiconductor Engineering|url=https://semiengineering.com/5nm-vs-3nm/|access-date=19 July 2019}}</ref><ref>{{cite news|last1=Lilly|first1=Paul|date=17 July 2019|title=Intel says it was too aggressive pursuing 10nm, will have 7nm chips in 2021|work=[[PC Gamer]]|url=https://www.pcgamer.com/intel-says-it-was-too-aggressive-pursuing-10nm-will-have-7nm-chips-in-2021/}}</ref> with [[10 nm process|10]], [[7 nm process|7]], and [[5 nm process|5&nbsp;nm]] nodes in mass production.<ref name="TSMC 2019Oct" >{{cite web|url=https://www.anandtech.com/show/15016/tsmc-5nm-on-track-for-q2-2020-hvm-will-ramp-faster-than-7nm |archive-url=https://web.archive.org/web/20191024004726/https://www.anandtech.com/show/15016/tsmc-5nm-on-track-for-q2-2020-hvm-will-ramp-faster-than-7nm |archive-date=October 24, 2019 |title= TSMC: 5nm on Track for Q2 2020 HVM, Will Ramp Faster Than 7nm |last= Shilov|first= Anton|website= www.anandtech.com|date= October 23, 2019 |access-date=December 1, 2019}}</ref><ref name="Samsung 5nm in 2020" >{{cite web|url= https://www.anandtech.com/show/14695/samsungs-aggressive-euv-plans-6nm-production-in-h2-5nm-4nm-on-track |archive-url= https://archive.today/20190801054547/https://www.anandtech.com/show/14695/samsungs-aggressive-euv-plans-6nm-production-in-h2-5nm-4nm-on-track |archive-date= August 1, 2019 |title= Home>Semiconductors Samsung's Aggressive EUV Plans: 6nm Production in H2, 5nm & 4nm On Track |last= Shilov|first= Anton|publisher= www.anandtech.com|date=  July 31, 2019 |access-date= December 1, 2019}}</ref><ref name="anandtech-samsung">{{cite web|url=https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|archive-url=https://web.archive.org/web/20190418063522/https://www.anandtech.com/show/14231/samsung-completes-development-of-5-nm-euv-process-technology|archive-date=April 18, 2019|title=Samsung Completes Development of 5nm EUV Process Technology|last=Shilov|first=Anton|website=anandtech.com|access-date=2019-05-31}}</ref><ref name="tsmc">{{citation | url = https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=THPGWQTHTH | title = TSMC and OIP Ecosystem Partners Deliver Industry's First Complete Design Infrastructure for 5nm Process Technology | date = 3 April 2019 | type = press release | publisher = TSMC | access-date = 19 July 2019 | archive-date = 14 May 2020 | archive-url = https://web.archive.org/web/20200514031427/https://www.tsmc.com/tsmcdotcom/PRListingNewsAction.do?action=detail&language=E&newsid=THPGWQTHTH }}</ref><ref>{{cite web |last=Cutress |first=Dr. Ian |title='Better Yield on 5nm than 7nm': TSMC Update on Defect Rates for N5 |url=https://www.anandtech.com/show/16028/better-yield-on-5nm-than-7nm-tsmc-update-on-defect-rates-for-n5 |archive-url=https://web.archive.org/web/20200825135522/https://www.anandtech.com/show/16028/better-yield-on-5nm-than-7nm-tsmc-update-on-defect-rates-for-n5 |archive-date=August 25, 2020 |access-date=2023-03-27 |website=www.anandtech.com}}</ref>

=== Moore's second law ===
{{Further|Moore's second law}}

As the cost of computer power to the consumer falls, the cost for producers to fulfill Moore's law follows an opposite trend: R&D, manufacturing, and test costs have increased steadily with each new generation of chips. The cost of the tools, principally [[extreme ultraviolet lithography]] (EUVL), used to manufacture chips doubles every 4 years.<ref>{{cite report |url=https://www.usitc.gov/publications/332/working_papers/id_058_the_health_and_competitiveness_of_the_sme_industry_final_070219checked.pdf |title=The Health and Competitiveness of the U.S. Semiconductor Manufacturing Equipment Industry |author=VerWey |first=John |date=July 2019 |publisher=U.S. International Trade Commission |page=17 |docket= |quote=The costs required to fabricate chips have increased in a predictable manner, operating under what is referred to Moore's Second Law or "Rock's Law", which says the cost of semiconductor tools doubles every four years. |access-date=30 April 2024}}</ref> Rising manufacturing costs are an important consideration for the sustaining of Moore's law.<ref>{{cite magazine| first1 = Sumner | last1 = Lemon | first2 = Tom | last2 = Krazit |url=http://www.infoworld.com/article/2669732/computer-hardware/with-chips--moore-s-law-is-not-the-problem.html |title=With chips, Moore's Law is not the problem |magazine=Infoworld |date=2005-04-19 |access-date=2011-08-22}}</ref> This led to the formulation of [[Moore's second law]], also called Rock's law (named after [[Arthur Rock]]), which is that the [[capital cost]] of a [[semiconductor fabrication plant]] also increases exponentially over time.<ref>{{cite web |url=http://www.edavision.com/200111/feature.pdf |publisher=EDA Vision |title=Does Moore's Law Still Hold Up? |first=Jeff |last=Dorsch |access-date=2011-08-22 |archive-date=2006-05-06 |archive-url=https://web.archive.org/web/20060506114410/http://www.edavision.com/200111/feature.pdf |url-status=usurped }}</ref><ref>{{cite web|url=http://research.microsoft.com/~gray/Moore_Law.html |title=The Origin, Nature, and Implications of 'Moore's Law' | first = Bob | last = Schaller |publisher=Research.microsoft.com |date=1996-09-26 |access-date=2011-08-22}}</ref>

== Major enabling factors ==
{{See also|List of semiconductor scale examples|Transistor count}}
[[File:NAND scaling timeline.png|thumb|upright=2|The trend of [[MOSFET scaling]] for [[NAND flash]] memory allows [[transistor count|the doubling]] of [[floating-gate MOSFET]] components manufactured in the same wafer area in less than 18 months.|alt=A semi-log plot of NAND flash design rule dimensions in nanometers against dates of introduction. The downward linear regression indicates an exponential decrease in feature dimensions over time.]]

Numerous innovations by scientists and engineers have sustained Moore's law since the beginning of the IC era. Some of the key innovations are listed below, as examples of breakthroughs that have advanced integrated circuit and [[semiconductor device fabrication]] technology, allowing transistor counts to grow by more than seven orders of magnitude in less than five decades.
* [[Integrated circuit]] (IC): The ''raison d'être'' for Moore's law. The [[germanium]] [[Hybrid integrated circuit|hybrid IC]] was invented by [[Jack Kilby]] at [[Texas Instruments]] in 1958,<ref>Kilby, Jack, "Miniaturized electronic circuits", {{patent|US|3138743}}, issued June 23, 1964 (filed February 6, 1959).</ref> followed by the invention of the [[silicon]] [[Monolithic integrated circuit|monolithic IC]] chip by [[Robert Noyce]] at Fairchild Semiconductor in 1959.<ref>Noyce, Robert, "Semiconductor device-and-lead structure", {{patent|US|2981877}}, issued April 25, 1961 (filed July 30, 1959).</ref>
* [[Complementary metal–oxide–semiconductor]] (CMOS): The CMOS process was invented by [[Chih-Tang Sah]] and [[Frank Wanlass]] at Fairchild Semiconductor in 1963.<ref name="computerhistory1963">{{cite web |title=1963: Complementary MOS Circuit Configuration is Invented |url=https://www.computerhistory.org/siliconengine/complementary-mos-circuit-configuration-is-invented/ |access-date=6 July 2019 |website=[[Computer History Museum]]}}</ref><ref name="sah">{{cite book |last1=Sah |first1=Chih-Tang |author1-link=Chih-Tang Sah |last2=Wanlass |first2=Frank |author2-link=Frank Wanlass |date=1963 |title= 1963 IEEE International Solid-State Circuits Conference. Digest of Technical Papers|chapter=Nanowatt logic using field-effect metal-oxide semiconductor triodes |volume=VI |pages=32–33 |doi=10.1109/ISSCC.1963.1157450}}</ref><ref>Wanlass, F., "Low stand-by power complementary field effect circuitry", {{patent|US|3356858}}, issued December 5, 1967 (filed June 18, 1963).</ref>
* [[Dynamic random-access memory]] (DRAM): DRAM was developed by [[Robert H. Dennard]] at [[IBM]] in 1967.<ref>Dennard, Robert H., "Field-effect transistor memory", {{patent|US|3387286}}, issued June 4, 1968 (filed July 14, 1967)</ref>
* [[Photoresist#Chemical amplification|Chemically amplified photoresist]]: Invented by Hiroshi Ito, [[C. Grant Willson]] and J. M. J. Fréchet at IBM ''circa'' 1980,<ref>{{US patent|4491628}}, "Positive and Negative Working Resist Compositions with Acid-Generating Photoinitiator and Polymer with Acid-Labile Groups Pendant From Polymer Backbone" J. M. J. Fréchet, H. Ito and C. G. Willson 1985.[http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=%2Fnetahtml%2Fsearch-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN%2F4491628], {{Webarchive|url=https://web.archive.org/web/20190202041857/http://patft.uspto.gov/netacgi/nph-Parser?Sect2=PTO1&Sect2=HITOFF&p=1&u=%2Fnetahtml%2Fsearch-bool.html&r=1&f=G&l=50&d=PALL&RefSrch=yes&Query=PN%2F4491628|date=February 2, 2019}}.</ref><ref name=Ito01>{{cite journal| last1 = Ito | first1 = H. | last2 = Willson | first2 = C. G. |journal=Polymer Engineering & Science |volume=23|issue=18|page=204|year=1983|title=Chemical amplification in the design of dry developing resist material | doi = 10.1002/pen.760231807 | bibcode = 1983PESci..23.1012I }}</ref><ref name=Ito02>{{cite journal| last1 = Ito | first1 = Hiroshi | first2 = C. Grant | last2 = Willson | first3 = Jean H. J. | last3 = Frechet |journal= VLSI Technology, 1982. Digest of Technical Papers. Symposium on |year=1982 |title=New UV resists with negative or positive tone }}</ref> which was 5–10 times more sensitive to ultraviolet light.<ref name="Brock">{{cite news |url=https://www.sciencehistory.org/distillations/magazine/patterning-the-world-the-rise-of-chemically-amplified-photoresists |title=Patterning the World: The Rise of Chemically Amplified Photoresists |work=Chemical Heritage Magazine|publisher=[[Chemical Heritage Foundation]] |date=2007-10-01 |first= David C. |last=Brock|access-date=27 March 2018 }}</ref> IBM introduced chemically amplified photoresist for DRAM production in the mid-1980s.<ref>{{cite journal |last1=Lamola |first1=A. A. |last2=Szmanda |first2=C. R. |last3=Thackeray |first3=J. W. |date=August 1991 |title=Chemically amplified resists |url=http://go.galegroup.com/ps/anonymous?p=AONE&sw=w&issn=0038111X&v=2.1&it=r&id=GALE%7CA11137024&sid=googleScholar&linkaccess=fulltext&authCount=1&isAnonymousEntry=true |journal=Solid State Technology |volume=34 |issue=8 |access-date=2017-11-01}}</ref><ref>{{cite web|url=http://researcher.watson.ibm.com/researcher/files/us-saswans/05389371.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://researcher.watson.ibm.com/researcher/files/us-saswans/05389371.pdf |archive-date=2022-10-09 |url-status=live |title=Chemical amplification resists: History and development within IBM |publisher=[[IBM Journal of Research and Development]] |first=Hiroshi |last=Ito  |year=2000 |access-date=2014-05-20}}</ref>
* Deep UV excimer laser [[photolithography]]: Invented by Kanti Jain<ref name="Jain_Willson">{{US patent reference|number=US 4458994 A|y=1984|m=07|d=10|inventor=Kantilal Jain, Carlton G. Willson|title=High resolution optical lithography method and apparatus having excimer laser light source and stimulated Raman shifting}}.</ref> at IBM ''circa'' 1980.<ref name=ieee1982>{{cite journal |last1=Jain |first1=K. |last2=Willson |first2=C. G. |last3=Lin |first3=B. J. |title=Ultrafast deep-UV lithography with excimer lasers |journal=IEEE Electron Device Letters |volume=3 |issue=3 |date=1982 |pages=53–55 |doi=10.1109/EDL.1982.25476|bibcode=1982IEDL....3...53J |s2cid=43335574 }}</ref><ref name="spie1990">{{cite book |last=Jain |first=K. |url=https://spie.org/Publications/Book/2301 |title=Excimer Laser Lithography |date=1990 |publisher=SPIE Press |isbn=978-0-8194-0271-4 |location=Bellingham, Washington |oclc=20492182}}</ref><ref name=LaFontaine>{{cite web |last=La Fontaine |first=Bruno |title=Lasers and Moore's Law |work=SPIE Professional |date=October 2010 |page=20 |url=http://spie.org/x42152.xml}}</ref> Prior to this, [[excimer laser]]s had been mainly used as research devices since their development in the 1970s.<ref>Basov, N. G. et al., Zh. Eksp. Fiz. i Tekh. Pis'ma. Red. 12, 473 (1970).</ref><ref>{{cite journal | last1 = Burnham | first1 = R. | last2 = Djeu | first2 = N. | year = 1976 | title =  Ultraviolet-preionized discharge-pumped lasers in XeF, KrF, and ArF| doi = 10.1063/1.88934 | journal = Appl. Phys. Lett. | volume = 29 | issue = 11| page = 707 | bibcode = 1976ApPhL..29..707B }}</ref> From a broader scientific perspective, the invention of excimer laser lithography has been highlighted as one of the major milestones in the 50-year history of the laser.<ref>{{citation|title=Lasers in Our Lives / 50 Years of Impact|url=http://www.stfc.ac.uk/Resources/PDF/Lasers50_final1.pdf|publisher=U.K. Engineering and Physical Sciences Research Council|access-date=2011-08-22|archive-url=https://web.archive.org/web/20110913160302/http://www.stfc.ac.uk/Resources/PDF/Lasers50_final1.pdf|archive-date=2011-09-13}}</ref><ref>{{cite web |publisher=SPIE |title=50 Years Advancing the Laser |url=http://spie.org/Documents/AboutSPIE/SPIE%20Laser%20Luminaries.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://spie.org/Documents/AboutSPIE/SPIE%20Laser%20Luminaries.pdf |archive-date=2022-10-09 |url-status=live |access-date=2011-08-22}}</ref>
* [[Semiconductor fabrication#Back-end-of-line (BEOL) processing|Interconnect]] innovations: Interconnect innovations of the late 1990s, including chemical-mechanical polishing or [[chemical mechanical planarization]] (CMP), trench isolation, and copper interconnects—although not directly a factor in creating smaller transistors—have enabled improved [[Wafer (electronics)|wafer]] yield, additional [[Technology node#Interconnect|layers of metal]] wires, closer spacing of devices, and lower electrical resistance.<ref name="Moore_2003">{{cite conference |last=Moore |first=Gordon E.|author-link=Gordon Moore |title=transcription of Gordon Moore's Plenary Address at ISSCC 50th Anniversary |url=http://isscc.org/doc/50th/Moore_Transcript.pdf |book-title=transcription "Moore on Moore: no Exponential is forever" |conference=2003 IEEE International Solid-State Circuits Conference |conference-url=http://isscc.org/ |publisher=ISSCC |place=San Francisco, California |date=2003-02-10 |archive-url=https://web.archive.org/web/20100331010101/http://isscc.org/doc/50th/Moore_Transcript.pdf|archive-date=2010-03-31 }}</ref><ref name="Steigerwald">{{cite book | doi = 10.1109/IEDM.2008.4796607| chapter = Chemical mechanical polish: The enabling technology| title = 2008 IEEE International Electron Devices Meeting| pages = 1–4| year = 2008| last1 = Steigerwald | first1 = J. M. | isbn = 978-1-4244-2377-4| s2cid = 8266949}} "Table1: 1990 enabling multilevel metallization; 1995 enabling STI compact isolation, polysilicon patterning and yield / defect reduction"</ref><ref>{{cite web |url=http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/ |archive-url=https://web.archive.org/web/20120403013037/http://www-03.ibm.com/ibm/history/ibm100/us/en/icons/copperchip/ |archive-date=April 3, 2012 |title=IBM100 – Copper Interconnects: The Evolution of Microprocessors |access-date=October 17, 2012|date=2012-03-07 }}</ref>

Computer industry technology road maps predicted in 2001 that Moore's law would continue for several generations of semiconductor chips.<ref name="International Technology Roadmap">{{cite web |url=http://public.itrs.net/ |title=International Technology Roadmap for Semiconductors |access-date=2011-08-22 |archive-url=https://web.archive.org/web/20110825075240/http://public.itrs.net/ |archive-date=2011-08-25 }}</ref>

=== Recent trends ===
{{Prose|section|date=March 2025}}
[[File:Threshold formation nowatermark.gif|thumb|upright=2|A simulation of electron density as gate voltage (Vg) varies in a [[nanowire]] MOSFET. The threshold voltage is around 0.45&nbsp;V. Nanowire MOSFETs lie toward the end of the ITRS road map for scaling devices below 10&nbsp;nm gate lengths.|alt=animated plot showing electron density and current as gate voltage varies ]]

One of the key technical challenges of engineering future [[Nanoelectronics|nanoscale]] transistors is the design of gates. As device dimensions shrink, controlling the current flow in the thin channel becomes more difficult. Modern nanoscale transistors typically take the form of [[multi-gate MOSFET]]s, with the [[FinFET]] being the most common nanoscale transistor. The FinFET has gate dielectric on three sides of the channel. In comparison, the [[gate-all-around]] MOSFET ([[GAAFET]]) structure has even better gate control.

* A [[gate-all-around]] MOSFET (GAAFET) was first demonstrated in 1988, by a [[Toshiba]] research team led by [[Fujio Masuoka]], who demonstrated a vertical nanowire GAAFET that he called a surrounding gate transistor (SGT).<ref>{{cite book |last1=Masuoka |first1=Fujio |author1-link=Fujio Masuoka |last2=Takato |first2=H. |last3=Sunouchi |first3=K. |last4=Okabe |first4=N. |last5=Nitayama |first5=A. |last6=Hieda |first6=K. |last7=Horiguchi |first7=F. |title=Technical Digest., International Electron Devices Meeting |chapter=High performance CMOS surrounding gate transistor (SGT) for ultra high density LSIs |date=December 1988 |pages=222–225 |doi=10.1109/IEDM.1988.32796|s2cid=114148274 }}</ref><ref>{{cite book |last1=Brozek |first1=Tomasz |title=Micro- and Nanoelectronics: Emerging Device Challenges and Solutions |date=2017 |publisher=[[CRC Press]] |isbn=978-1-351-83134-5 |page=117 |url=https://books.google.com/books?id=dAhEDwAAQBAJ&pg=PA117}}</ref> Masuoka, best known as the inventor of [[flash memory]], later left Toshiba and founded Unisantis Electronics in 2004 to research surrounding-gate technology along with [[Tohoku University]].<ref>{{cite web |title=Company Profile |url=http://www.unisantis-el.jp/profile.htm |website=Unisantis Electronics |archive-url=https://web.archive.org/web/20070222112935/http://www.unisantis-el.jp/profile.htm |archive-date=22 February 2007 |access-date=17 July 2019 }}</ref>
* In 2006, a team of Korean researchers from the [[Korea Advanced Institute of Science and Technology]] (KAIST) and the National Nano Fab Center developed a [[3&nbsp;nm]] transistor, the world's smallest [[nanoelectronic]] device at the time, based on FinFET technology.<ref>{{citation |url=http://www.highbeam.com/doc/1G1-145838158.html|archive-url=https://web.archive.org/web/20121106011401/http://www.highbeam.com/doc/1G1-145838158.html|archive-date=6 November 2012|title=Still Room at the Bottom.(nanometer transistor developed by Yang-kyu Choi from the Korea Advanced Institute of Science and Technology )|date=1 April 2006|work = Nanoparticle News }}</ref><ref>{{cite book|first=Hyunjin |last=Lee |title=2006 Symposium on VLSI Technology, 2006. Digest of Technical Papers |chapter=Sub-5nm All-Around Gate FinFET for Ultimate Scaling |year=2006 |pages=58–59 |doi=10.1109/VLSIT.2006.1705215 |display-authors=etal|isbn=978-1-4244-0005-8 |hdl=10203/698 |s2cid=26482358 |hdl-access=free }}</ref>
* In 2010, researchers at the [[Tyndall National Institute]] in Cork, Ireland announced a junctionless transistor. A control gate wrapped around a silicon nanowire can control the passage of electrons without the use of junctions or doping. They claim these may be produced at 10&nbsp;nm scale using existing fabrication techniques.<ref>{{cite magazine |url=https://spectrum.ieee.org/junctionless-transistor-fabricated-from-nanowires| title =Junctionless Transistor Fabricated from Nanowires|date=2010-02-22|  first = Dexter | last = Johnson|magazine=IEEE Spectrum| access-date = 2010-04-20}}</ref>
* In 2011, researchers at the University of Pittsburgh announced the development of a single-electron transistor, 1.5&nbsp;nm in diameter, made out of oxide-based materials. Three wires converge on a central island that can house one or two electrons. Electrons tunnel from one wire to another through the island. Conditions on the third wire result in distinct conductive properties including the ability of the transistor to act as a solid-state memory.<ref>{{cite journal |url=http://www.sciencedaily.com/releases/2011/04/110418135541.htm |title=Super-small transistor created: Artificial atom powered by single electron |doi=10.1038/nnano.2011.56 |pmid=21499252 |date=2011-04-19 |access-date=2011-08-22|bibcode = 2011NatNa...6..343C |volume=6 |issue=6 |journal=Nature Nanotechnology |pages=343–347|last1=Cheng |first1=Guanglei |last2=Siles |first2=Pablo F. |last3=Bi |first3=Feng |last4=Cen |first4=Cheng |last5=Bogorin |first5=Daniela F. |last6=Bark |first6=Chung Wung |last7=Folkman |first7=Chad M. |last8=Park |first8=Jae-Wan |last9=Eom |first9=Chang-Beom |last10=Medeiros-Ribeiro |first10=Gilberto |last11=Levy |first11=Jeremy }}</ref> Nanowire transistors could spur the creation of microscopic computers.<ref>{{cite book|page=173|title=Physics of the Future|first=Michio | last=Kaku |author-link=Michio Kaku |publisher=Doubleday|date=2010|isbn=978-0-385-53080-4}}</ref><ref>{{cite journal |last=Yirka |first=Bob |date=2013-05-02 |title=New nanowire transistors may help keep Moore's Law alive |url=http://phys.org/news/2013-05-nanowire-transistors-law-alive.html |journal=Nanoscale |volume=5 |issue=6 |pages=2437–2441 |bibcode=2013Nanos...5.2437L |doi=10.1039/C3NR33738C |pmid=23403487 |access-date=2013-08-08}}</ref><ref>{{cite magazine|url=https://www.forbes.com/2007/06/05/nanotech-geim-graphene-pf-guru-in_jw_0605adviserqa_inl.html |title=Rejuvenating Moore's Law With Nanotechnology |magazine=Forbes |date=2007-06-05 |access-date=2013-08-08}}</ref>
* In 2012, a research team at the [[University of New South Wales]] announced the development of the first working transistor consisting of a single atom placed precisely in a silicon crystal (not just picked from a large sample of random transistors).<ref>{{cite journal |last1=Fuechsle |first1=M. |last2=Miwa |first2=J. A. |last3=Mahapatra |first3=S. |last4=Ryu |first4=H. |last5=Lee |first5=S. |last6=Warschkow |first6=O. |last7=Hollenberg |first7=L. C. |last8=Klimeck |first8=G. |last9=Simmons |first9=M. Y. |date=2011-12-16 |title=A single-atom transistor |journal=Nat Nanotechnol |volume=7 |issue=4 |pages=242–246 |bibcode=2012NatNa...7..242F |doi=10.1038/nnano.2012.21 |pmid=22343383 |s2cid=14952278}}</ref> Moore's law predicted this milestone to be reached for ICs in the lab by 2020.
* In 2015, IBM demonstrated [[7&nbsp;nm]] node chips with [[silicon–germanium]] transistors produced using EUVL. The company believed this transistor density would be four times that of the then-current [[14&nbsp;nm]] chips.<ref>{{cite news | url=https://www.wsj.com/articles/ibm-reports-advances-in-shrinking-future-chips-1436414814 | title=IBM Reports Advance in Shrinking Chip Circuitry | work=The Wall Street Journal | date=July 9, 2015 | access-date=July 9, 2015}}</ref>
* Samsung and TSMC plan to manufacture 3{{nbsp}}nm GAAFET nodes by 2021{{ndash}}2022.<ref>{{citation| url  =https://www.tomshardware.com/news/samsung-3nm-gaafet-production-2021,38426.html | title = Samsung Plans Mass Production of 3nm GAAFET Chips in 2021 | first = Lucian |last = Armasu | date = 11 January 2019| work = www.tomshardware.com }}</ref><ref>{{citation| url = https://www.eetimes.com/document.asp?doc_id=1332388 | title = TSMC Aims to Build World's First 3-nm Fab| first= Alan | last= Patterson | date= October 2, 2017 | work = www.eetimes.com }}</ref> Note that node names, such as 3{{nbsp}}nm, have no relation to the physical size of device elements (transistors).
* A [[Toshiba]] research team including T. Imoto, M. Matsui and C. Takubo developed a ''system block module'' wafer bonding process for manufacturing [[three-dimensional integrated circuit]] (3D IC) packages in 2001.<ref>{{cite book |last1=Garrou |first1=Philip |title=Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits |date=6 August 2008 |publisher=[[Wiley-VCH]] |isbn=978-3-527-62305-1 |chapter=Introduction to 3D Integration |doi=10.1002/9783527623051.ch1 |pages=4 |chapter-url=https://application.wiley-vch.de/books/sample/3527332650_c01.pdf |archive-url=https://ghostarchive.org/archive/20221009/https://application.wiley-vch.de/books/sample/3527332650_c01.pdf |archive-date=2022-10-09 |url-status=live}}</ref><ref>{{cite journal |last1=Imoto |first1=T. |last2=Matsui |first2=M. |last3=Takubo |first3=C. |last4=Akejima |first4=S. |last5=Kariya |first5=T. |last6=Nishikawa |first6=T. |last7=Enomoto |first7=R. |date=2001 |title=Development of 3-Dimensional Module Package, "System Block Module" |url=https://www.tib.eu/en/search/id/BLCP%3ACN039662991/Development-of-3-Dimensional-Module-Package-System/ |journal=Electronic Components and Technology Conference |publisher=[[Institute of Electrical and Electronics Engineers]] |issue=51 |pages=552–557}}</ref> In April 2007, Toshiba introduced an eight-layer 3D IC, the 16{{nbsp}}[[Gigabyte|GB]] THGAM [[Embedded system|embedded]] [[NAND flash]] memory chip that was manufactured with eight stacked 2{{nbsp}}GB NAND flash chips.<ref>{{cite news |title=TOSHIBA COMMERCIALIZES INDUSTRY'S HIGHEST CAPACITY EMBEDDED NAND FLASH MEMORY FOR MOBILE CONSUMER PRODUCTS |url=http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |archive-url=https://web.archive.org/web/20101123023805/http://www.toshiba.com/taec/news/press_releases/2007/memy_07_470.jsp |archive-date=November 23, 2010 |access-date=23 November 2010 |work=Toshiba |date=April 17, 2007}}</ref> In September 2007, [[Hynix]] introduced 24-layer 3D IC, a 16{{nbsp}}GB flash memory chip that was manufactured with 24 stacked NAND flash chips using a wafer bonding process.<ref>{{cite news |title=Hynix Surprises NAND Chip Industry |url=https://www.koreatimes.co.kr/www/news/biz/2007/09/123_9628.html |access-date=8 July 2019 |work=[[Korea Times]] |date=5 September 2007}}</ref>
* [[V-NAND]], also known as 3D NAND, allows flash memory cells to be stacked vertically using [[charge trap flash]] technology originally presented by John Szedon in 1967, significantly increasing the number of transistors on a flash memory chip. 3D NAND was first announced by Toshiba in 2007.<ref>{{cite news |title=Toshiba announces new "3D" NAND flash technology |url=https://www.engadget.com/2007/06/12/toshiba-announces-new-3d-nand-flash-technology/ |access-date=10 July 2019 |work=[[Engadget]] |date=2007-06-12}}</ref> V-NAND was first commercially manufactured by [[Samsung Electronics]] in 2013.<ref>{{cite web|url=https://www.samsung.com/semiconductor/insights/news-events/samsung-introduces-worlds-first-3d-v-nand-based-ssd-for-enterprise-applications/|title=Samsung Introduces World's First 3D V-NAND Based SSD for Enterprise Applications &#124; Samsung &#124; Samsung Semiconductor Global Website|website=www.samsung.com}}</ref><ref>{{cite web|url=https://www.eetimes.com/author.asp?section_id=36&doc_id=1319167|title=Samsung Confirms 24 Layers in 3D NAND|first=Peter|last=Clarke|website=EETimes}}</ref><ref>{{cite web|url=https://news.samsung.com/global/samsung-electronics-starts-mass-production-of-industry-first-3-bit-3d-v-nand-flash-memory|title=Samsung Electronics Starts Mass Production of Industry First 3-bit 3D V-NAND Flash Memory|website=news.samsung.com}}</ref>
* In 2008, researchers at HP Labs announced a working [[memristor]], a fourth basic passive circuit element whose existence only had been theorized previously. The memristor's unique properties permit the creation of smaller and better-performing electronic devices.<ref name="Williams08">
{{cite journal
 |last1=Strukov|first1=Dmitri B
 |last2=Snider|first2=Gregory S
 |last3=Stewart|first3=Duncan R
 |last4=Williams|first4=Stanley R
 |title=The missing memristor found
 |journal=Nature
 |volume=453
 |issue=7191
 |pages=80–83
 |year=2008
 |doi=10.1038/nature06932
 |pmid=18451858
 |bibcode=2008Natur.453...80S|s2cid=4367148
}}</ref>
* In 2014, bioengineers at [[Stanford University]] developed a circuit modeled on the human brain. [[Neurogrid|Sixteen Neurocore chips]] simulate one million neurons and billions of synaptic connections, claimed to be {{val|9,000}} times faster as well as more energy efficient than a typical PC.<ref>{{cite web|url=http://news.stanford.edu/pr/2014/pr-neurogrid-boahen-engineering-042814.html|title=Stanford bioengineers create circuit board modeled on the human brain – Stanford News Release|website=news.stanford.edu|date=2014-04-28|access-date=May 4, 2014|archive-date=January 22, 2019|archive-url=https://web.archive.org/web/20190122182434/https://news.stanford.edu/pr/2014/pr-neurogrid-boahen-engineering-042814.html}}</ref>
* In 2015, Intel and [[Micron Technology|Micron]] announced [[3D XPoint]], a [[non-volatile memory]] claimed to be significantly faster with similar density compared to NAND. Production scheduled to begin in 2016 was delayed until the second half of 2017.<ref>{{cite news|url=https://www.bbc.com/news/technology-33675734|title=3D Xpoint memory: Faster-than-flash storage unveiled|newspaper=BBC News|date=2015-07-28|last1=Kelion|first1=Leo}}</ref><ref>{{cite magazine|url=https://www.wired.com/2015/07/3d-xpoint/|title=Intel's New Memory Chips Are Faster, Store Way More Data|date=July 28, 2015|magazine=WIRED}}</ref><ref>{{cite news |author=Bright |first=Peter |date=March 19, 2017 |title=Intel's first Optane SSD: 375GB that you can also use as RAM |url=https://arstechnica.com/information-technology/2017/03/intels-first-optane-ssd-375gb-that-you-can-also-use-as-ram/ |access-date=March 31, 2017 |work=Ars Technica}}</ref>
* In 2017, Samsung combined its V-NAND technology with [[eUFS]] 3D IC stacking to produce a 512{{nbsp}}GB flash memory chip, with eight stacked 64-layer V-NAND dies.<ref name="anandtech-samsung-2017">{{cite news|url=https://www.anandtech.com/show/12120/samsung-starts-production-of-512-gb-ufs-chips|archive-url=https://web.archive.org/web/20171205221122/https://www.anandtech.com/show/12120/samsung-starts-production-of-512-gb-ufs-chips|archive-date=December 5, 2017|title=Samsung Starts Production of 512 GB UFS NAND Flash Memory: 64-Layer V-NAND, 860 MB/s Reads|last1=Shilov|first1=Anton|date=December 5, 2017|work=[[AnandTech]]|access-date=23 June 2019}}</ref> In 2019, Samsung produced a 1{{nbsp}}[[Terabyte|TB]] flash chip with eight stacked 96-layer V-NAND dies, along with [[quad-level cell]] (QLC) technology ([[4-bit]] per transistor),<ref name="electronicsweekly-samsung">{{cite news |last1=Manners |first1=David |title=Samsung makes 1TB flash eUFS module |url=https://www.electronicsweekly.com/news/business/samsung-makes-1tb-flash-module-2019-01/ |access-date=23 June 2019 |work=[[Electronics Weekly]] |date=30 January 2019}}</ref><ref name="anandtech-samsung-2018">{{cite news |last1=Tallis |first1=Billy |title=Samsung Shares SSD Roadmap for QLC NAND And 96-layer 3D NAND |url=https://www.anandtech.com/show/13497/samsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand |archive-url=https://web.archive.org/web/20181018063357/https://www.anandtech.com/show/13497/samsung-shares-ssd-roadmap-for-qlc-nand-and-96layer-3d-nand |archive-date=October 18, 2018 |access-date=27 June 2019 |work=[[AnandTech]] |date=October 17, 2018}}</ref> equivalent to 2{{nbsp}}trillion transistors, the highest transistor count of any IC chip.
* In 2020, Samsung Electronics planned to produce the [[5&nbsp;nm]] node, using FinFET and [[Extreme ultraviolet lithography|EUV]] technology.<ref name="Samsung 5nm in 2020"/>{{Update inline|reason=Has it been produced?|date=May 2021}}
* In May 2021, IBM announced the creation of the first [[2 nm]] computer chip, with parts supposedly being smaller than human DNA.<ref>{{cite web|last=IBM|date=May 6, 2021|title=IBM Unveils World's First 2 Nanometer Chip Technology, Opening a New Frontier for Semiconductors|url=https://newsroom.ibm.com/2021-05-06-IBM-Unveils-Worlds-First-2-Nanometer-Chip-Technology,-Opening-a-New-Frontier-for-Semiconductors#assets_all|url-status=live|archive-url=https://web.archive.org/web/20210506142313/https://newsroom.ibm.com/2021-05-06-IBM-Unveils-Worlds-First-2-Nanometer-Chip-Technology,-Opening-a-New-Frontier-for-Semiconductors|archive-date=May 6, 2021|access-date=May 14, 2021}}</ref>

Microprocessor architects report that semiconductor advancement has slowed industry-wide since around 2010, below the pace predicted by Moore's law.<ref name="Turing Award Lecture 2018"/> Brian Krzanich, the former CEO of Intel, announced, "Our cadence today is closer to two and a half years than two."<ref>{{cite news | title = Intel Rechisels the Tablet on Moore's Law | first = Don | last = Clark | work = Wall Street Journal Digits Tech News and Analysis | date = July 15, 2015 | url = https://blogs.wsj.com/digits/2015/07/16/intel-rechisels-the-tablet-on-moores-law/ |quote=The last two technology transitions have signaled that our cadence today is closer to two and a half years than two |access-date=2015-07-16}}</ref> Intel stated in 2015 that improvements in MOSFET devices have slowed, starting at the [[22&nbsp;nm]] feature width around 2012, and continuing at [[14&nbsp;nm]].<ref>{{cite web|url=http://files.shareholder.com/downloads/INTC/867590276x0xS50863-16-105/50863/filing.pdf|title=INTEL CORP, FORM 10-K (Annual Report), Filed 02/12/16 for the Period Ending 12/26/15|access-date=2017-02-24|archive-url=https://web.archive.org/web/20181204023944/http://files.shareholder.com/downloads/INTC/867590276x0xS50863-16-105/50863/filing.pdf|archive-date=2018-12-04}}</ref> Pat Gelsinger, former Intel CEO, stated at the end of 2023 that "we're no longer in the golden era of Moore's Law, it's much, much harder now, so we're probably doubling effectively closer to every three years now, so we've definitely seen a slowing."<ref>{{cite web |url=https://www.tomshardware.com/tech-industry/semiconductors/intels-ceo-says-moores-law-is-slowing-to-a-three-year-cadence-but-its-not-dead-yet |title=Intel's CEO says Moore's Law is slowing to a three-year cadence, but it's not dead yet |last=Connatser |first=Matthew |date=24 December 2023 |website=Tom's Hardware |publisher=Future US |access-date=30 April 2024 |quote=...the CEO stated transistors now double closer to every three years, which is actually significantly behind the pace of Moore's Law, which dictated a two-year cadence.}}</ref>

The physical limits to transistor scaling have been reached due to source-to-drain leakage, limited gate metals and limited options for channel material. Other approaches are being investigated, which do not rely on physical scaling. These include the spin state of electron [[spintronics]], [[tunnel junction]]s, and advanced confinement of channel materials via nano-wire geometry.<ref>{{cite book |last1=Nikonov|first1=Dmitri E.|last2=Young|first2=Ian A.|date=2013-02-01|title=Overview of Beyond-CMOS Devices and A Uniform Methodology for Their Benchmarking|publisher=Cornell University Library|arxiv=1302.0244|bibcode=2013arXiv1302.0244N}}</ref> Spin-based logic and memory options are being developed actively in labs.<ref>{{cite journal|last1=Manipatruni|first1=Sasikanth|author1-link=Sasikanth Manipatruni|last2=Nikonov|first2=Dmitri E.|last3=Young|first3=Ian A.|year=2016|title=Material Targets for Scaling All Spin Logic|journal=Physical Review Applied|volume=5|issue=1|article-number=014002|arxiv=1212.3362|bibcode=2016PhRvP...5a4002M|doi=10.1103/PhysRevApplied.5.014002|s2cid=1541400}}</ref><ref>{{cite journal|date=2010-02-28|title=Proposal for an all-spin logic device with built-in memory|journal=Nature Nanotechnology|volume=5|issue=4|pages=266–270|bibcode=2010NatNa...5..266B|doi=10.1038/nnano.2010.31|pmid=20190748|last1=Behin-Aein|first1=Behtash|last2=Datta|first2=Deepanjan|author3-link=Sayeef Salahuddin|last3=Salahuddin|first3=Sayeef|last4=Datta|first4=Supriyo|author4-link=Supriyo Datta}}</ref>

=== Alternative materials research ===
The vast majority of current transistors on integrated circuits are composed principally of [[Doping (semiconductor)|doped]] silicon and its alloys. As silicon is fabricated into single nanometer transistors, [[short-channel effect]]s adversely changes desired material properties of silicon as a functional transistor. Below are several non-silicon substitutes in the fabrication of small nanometer transistors.

One proposed material is [[Indium gallium arsenide#Applications|indium gallium arsenide]], or InGaAs. Compared to their silicon and germanium counterparts, InGaAs transistors are more promising for future high-speed, low-power logic applications. Because of intrinsic characteristics of [[List of semiconductor materials#Compound semiconductors|III–V compound semiconductors]], quantum well and [[tunnel field-effect transistor|tunnel]] effect transistors based on InGaAs have been proposed as alternatives to more traditional MOSFET designs.
* In the early 2000s, the [[atomic layer deposition]] [[high-κ]] [[thin film|film]] and pitch [[double patterning|double-patterning]] processes were invented by [[Gurtej Singh Sandhu]] at [[Micron Technology]], extending Moore's law for planar CMOS technology to [[32 nanometer|30&nbsp;nm]] class and smaller.
* In 2009, Intel announced the development of 80&nbsp;nm InGaAs [[quantum well]] transistors. Quantum well devices contain a material sandwiched between two layers of material with a wider band gap. Despite being double the size of leading pure silicon transistors at the time, the company reported that they performed equally as well while consuming less power.<ref>{{cite book |pages=1–4 |publisher=IEEE |date=2009-12-07 |first1 = G. | last1 = Dewey |first2 = R. |last2 = Kotlyar |first3 = R. |last3 = Pillarisetty |first4 = M. |last4 = Radosavljevic |first5 = T. |last5 = Rakshit |first6 = H. |last6 = Then |first7 = R. |last7 = Chau|title=2009 IEEE International Electron Devices Meeting (IEDM) |chapter=Logic performance evaluation and transport physics of Schottky-gate III&ndash;V compound semiconductor quantum well field effect transistors for power supply voltages (V<sub>CC</sub>) ranging from 0.5v to 1.0v |doi=10.1109/IEDM.2009.5424314 |isbn=978-1-4244-5639-0 |s2cid=41734511 }}</ref>
* In 2011, researchers at Intel demonstrated 3-D [[Multigate device#Types|tri-gate]] InGaAs transistors with improved leakage characteristics compared to traditional planar designs. The company claims that their design achieved the best electrostatics of any III–V compound semiconductor transistor.<ref>{{cite book |vauthors = Radosavljevic R, etal |title=2011 International Electron Devices Meeting |chapter=Electrostatics improvement in 3-D tri-gate over ultra-thin body planar InGaAs quantum well field effect transistors with high-K gate dielectric and scaled gate-to-drain/Gate-to-source separation |pages=33.1.1–33.1.4 |publisher=IEEE |date=2011-12-05 |doi=10.1109/IEDM.2011.6131661 |isbn=978-1-4577-0505-2 |s2cid=37889140 }}</ref> At the 2015 [[International Solid-State Circuits Conference]], Intel mentioned the use of III–V compounds based on such an architecture for their 7&nbsp;nm node.<ref>{{cite news |title=Intel at ISSCC 2015: Reaping the Benefits of 14nm and Going Beyond 10nm |publisher=Anandtech |date=2015-02-22 |access-date=2016-08-15 |url=http://www.anandtech.com/show/8991/intel-at-isscc-2015-reaping-the-benefits-of-14nm-and-going-beyond-10nm |archive-url=https://web.archive.org/web/20150223025735/http://www.anandtech.com/show/8991/intel-at-isscc-2015-reaping-the-benefits-of-14nm-and-going-beyond-10nm |archive-date=February 23, 2015 |first = Ian | last = Cutress}}</ref><ref>{{cite web |title=Intel forges ahead to 10nm, will move away from silicon at 7nm |website=Ars Technica |date=2015-02-23 |access-date=2016-08-15 |url=https://arstechnica.com/gadgets/2015/02/intel-forges-ahead-to-10nm-will-move-away-from-silicon-at-7nm/ |first = Sebastian | last = Anthony}}</ref>
* In 2011, researchers at the [[University of Texas at Austin]] developed an InGaAs tunneling field-effect transistors capable of higher operating currents than previous designs. The first III–V TFET designs were demonstrated in 2009 by a joint team from [[Cornell University]] and [[Pennsylvania State University]].<ref>{{cite news |title=InGaAs tunnel FET with ON current increased by 61% |publisher=Semiconductor Today |volume = 6 |issue = 6 |date=April{{ndash}}May 2011 |access-date=2016-08-15 |url=http://www.semiconductor-today.com/features/PDF/SemiconductorToday_AprMay2011_InGaAsFET.pdf |first = Mike |last = Cooke}}</ref><ref>{{cite journal |author=Zhao |first=Han |display-authors=etal |date=2011-02-28 |title=Improving the on-current of In0.7Ga0.3As tunneling field-effect-transistors by p++/n+ tunneling junction |journal=Applied Physics Letters |volume=98 |issue=9 |article-number=093501 |bibcode=2011ApPhL..98i3501Z |doi=10.1063/1.3559607}}</ref>
* In 2012, a team in MIT's Microsystems Technology Laboratories developed a 22&nbsp;nm transistor based on InGaAs that, at the time, was the smallest non-silicon transistor ever built. The team used techniques used in silicon device fabrication and aimed for better electrical performance and a reduction to [[10 nanometer|10-nanometer]] scale.<ref>{{cite web |title=Tiny compound semiconductor transistor could challenge silicon's dominance |publisher=MIT News  |date=2012-10-12 |access-date=2016-08-15 |url=https://news.mit.edu/2012/tiny-compound-semiconductor-transistor-could-challenge-silicons-dominance-1210 |first = Helen| last = Knight}}</ref>

[[Biological computing]] research shows that biological material has superior information density and energy efficiency compared to silicon-based computing.<ref>{{cite journal |last1=Cavin |first1=R. K. |last2=Lugli |first2=P. |last3=Zhirnov |first3=V. V. |date=2012-05-01 |title=Science and Engineering Beyond Moore's Law |journal=Proceedings of the IEEE |volume=100 |issue=Special Centennial Issue |pages=1720–1749 |doi=10.1109/JPROC.2012.2190155 |doi-access=free}}</ref>

[[File:Graphene SPM.jpg|thumb|upright=0.8|[[Scanning probe microscopy]] image of graphene in its hexagonal lattice structure |alt=refer to caption]]
Various forms of [[graphene]] are being studied for [[graphene electronics]], e.g., [[graphene nanoribbon]] [[graphene transistor|transistors]] have shown promise since their appearance in publications in 2008. (Bulk graphene has a [[band gap]] of zero and thus cannot be used in transistors because of its constant conductivity, an inability to turn off. The zigzag edges of the nanoribbons introduce localized energy states in the conduction and valence bands and thus a bandgap that enables switching when fabricated as a transistor. As an example, a typical GNR of width of 10&nbsp;nm has a desirable bandgap energy of 0.4&nbsp;eV.<ref name="nature 2007"/><ref>{{Cite book |last=Schwierz |first=Frank |chapter=Graphene transistors — A new contender for future electronics |date=November 2010 |title=2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology |pages=1202–1205 |doi=10.1109/ICSICT.2010.5667602 |isbn=978-1-4244-5797-7 }}</ref>) More research will need to be performed, however, on sub-50&nbsp;nm graphene layers, as its resistivity value increases and thus electron mobility decreases.<ref name="nature 2007">{{cite journal |last1=Avouris |first1=Phaedon |last2=Chen |first2=Zhihong |author2-link=Zhihong Chen |last3=Perebeinos |first3=Vasili |date=2007-09-30 |title=Carbon-based electronics |url=http://physics.oregonstate.edu/~tatej/COURSES/ph575/lib/exe/fetch.php?media=avouris_review_nnano.2007.300.pdf |journal=Nature Nanotechnology |volume=2 |issue=10 |pages=605–615 |bibcode=2007NatNa...2..605A |doi=10.1038/nnano.2007.300 |pmid=18654384 |access-date=2016-08-15}}</ref>

== Forecasts and roadmaps ==
In April 2005, [[Gordon Moore]] stated in an interview that the projection cannot be sustained indefinitely: "It can't continue forever. The nature of exponentials is that you push them out and eventually disaster happens." He also noted that transistors eventually would reach the limits of miniaturization at [[atom]]ic levels:
{{Blockquote|In terms of size [of transistors] you can see that we're approaching the size of atoms which is a fundamental barrier, but it'll be two or three generations before we get that far—but that's as far out as we've ever been able to see. We have another 10 to 20 years before we reach a fundamental limit. By then they'll be able to make bigger chips and have transistor budgets in the billions.<ref>{{cite web|url=http://www.techworld.com/news/operating-systems/moores-law-is-dead-says-gordon-moore-3576581/| title =Moore's Law is dead, says Gordon Moore|date=2005-04-13|  first = Manek | last = Dubash| work =Techworld| access-date = 2006-06-24}}</ref>|author=Gordon Moore in 2006}}In 2016 the [[International Technology Roadmap for Semiconductors]], after using Moore's Law to drive the industry since 1998, produced its final roadmap. It no longer centered its research and development plan on Moore's law. Instead, it outlined what might be called the More than Moore strategy in which the needs of applications drive chip development, rather than a focus on semiconductor scaling. Application drivers range from smartphones to AI to data centers.<ref name=":0">{{cite journal|last=Waldrop|first=M. Mitchell|date=2016-02-09|title=The chips are down for Moore's law|journal=Nature|volume=530|issue=7589|pages=144–147|doi=10.1038/530144a|pmid=26863965|issn=0028-0836|bibcode=2016Natur.530..144W|doi-access=free}}</ref>

IEEE began a road-mapping initiative in 2016, Rebooting Computing, named the [[International Roadmap for Devices and Systems]] (IRDS).<ref name="IRDS">{{cite web|url=https://rebootingcomputing.ieee.org/images/files/pdf/rc_irds.pdf |archive-url=https://web.archive.org/web/20160527224136/http://rebootingcomputing.ieee.org/images/files/pdf/rc_irds.pdf |archive-date=2016-05-27 |url-status=live|title=IRDS launch announcement 4 MAY 2016}}</ref>

Some forecasters, including Gordon Moore,<ref name="TheEconomist_Cross">{{cite news |last=Cross |first=Tim |date=12 March 2016 |title=After Moore's Law |url=http://www.economist.com/technology-quarterly/2016-03-12/after-moores-law |archive-url=https://web.archive.org/web/20160313010149/http://www.economist.com/technology-quarterly/2016-03-12/after-moores-law |archive-date=13 March 2016 |access-date=2016-03-13 |newspaper=The Economist |publisher=The Economist Technology Quarterly |quote=}}</ref> predict that Moore's law will end by around 2025.<ref>{{cite arXiv|last=Kumar|first=Suhas|title=Fundamental Limits to Moore's Law|year=2012|eprint=1511.05956|class=cond-mat.mes-hall}}</ref><ref name=":0" /><ref>{{cite news |url=https://www.nytimes.com/2015/09/27/technology/smaller-faster-cheaper-over-the-future-of-computer-chips.html?&moduleDetail=section-news-2&action=click&contentCollection=Business%20Day&region=Footer&module=MoreInSection&version=WhatsNext&contentID=WhatsNext&pgtype=article&_r=0 |title=Smaller, Faster, Cheaper, Over: The Future of Computer Chips |newspaper=New York Times |date=September 2015}}</ref> Although Moore's Law will reach a physical limit, some forecasters are optimistic about the continuation of technological progress in a variety of other areas, including new chip architectures, quantum computing, and AI and machine learning.<ref>{{cite web|url=https://medium.com/@sgblank/the-end-of-more-the-death-of-moores-law-5ddcfd8439dd|title = The End of More – the Death of Moore's Law| work=Medium |date = 6 March 2020 | last1=Blank | first1=Steve }}</ref><ref>{{cite web|url=https://www.forbes.com/sites/stephenmcbride1/2019/04/23/these-3-computing-technologies-will-beat-moores-law/?sh=27d34cd137b0|title=These 3 Computing Technologies Will Beat Moore's Law|website=[[Forbes]]}}</ref> [[Nvidia]] CEO [[Jensen Huang]] declared Moore's law dead in 2022;<ref name="nvidia">{{cite web |url=https://www.marketwatch.com/story/moores-laws-dead-nvidia-ceo-jensen-says-in-justifying-gaming-card-price-hike-11663798618 |title='Moore's Law's dead,' Nvidia CEO Jensen Huang says in justifying gaming-card price hike |date=2022-09-22 |access-date=2022-09-23 |language=en-US |publisher=[[MarketWatch]] |last=Witkowski |first=Wallace}}</ref> several days later, Intel CEO Pat Gelsinger countered with the opposite claim.<ref name="intel">{{cite web |url=https://arstechnica.com/gadgets/2022/09/the-intel-arc-a770-gpu-launches-october-12-for-329/ |title=Intel: 'Moore's law is not dead' as Arc A770 GPU is priced at $329 |date=2022-09-27 |access-date=2022-09-28 |language=en-US |publisher=[[Ars Technica]] |last=Machkovech |first=Sam}}</ref>

== Consequences ==
Digital electronics have contributed to world economic growth in the late twentieth and early twenty-first centuries.<ref name="Rauch" /> The primary driving force of economic growth is the growth of [[productivity]],<ref name="Kendrick 1961 3" /> which Moore's law factors into. Moore (1995) expected that "the rate of technological progress is going to be controlled from financial realities".<ref name="Moore1995" /> The reverse could and did occur around the late-1990s, however, with economists reporting that "Productivity growth is the key economic indicator of innovation."<ref name="Jorgenson01" /> Moore's law describes a driving force of technological and social change, productivity, and economic growth.<ref name="Keyes 2006" /><ref name="Liddle 2006" /><ref name="Kendrick 1961 3" />

An acceleration in the rate of semiconductor progress contributed to a surge in U.S. productivity growth,<ref>{{cite book | citeseerx=10.1.1.198.9555 |title=Information Technology and the U.S. Economy: Presidential Address to the American Economic Association |publisher=[[American Economic Association]] | first = Dale W. | last = Jorgenson | author-link = Dale W. Jorgenson | date = 2000 }}</ref><ref>{{cite journal|title=A Retrospective Look at the U.S. Productivity Growth Resurgence |journal = Journal of Economic Perspectives|volume = 22|pages = 3–24| first1 = Dale W. | last1 = Jorgenson | author1-link = Dale W. Jorgenson | first2 = Mun S. | last2 = Ho | first3 = Kevin J. | last3 = Stiroh | date = 2008 |doi=10.1257/jep.22.1.3 | doi-access = free | hdl = 10419/60598 | hdl-access = free }}</ref><ref>{{cite web|url=http://bea.gov/papers/pdf/ip-nipa.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://bea.gov/papers/pdf/ip-nipa.pdf |archive-date=2022-10-09 |url-status=live |title=Information Processing Equipment and Software in the National Accounts |publisher=U.S. Department of Commerce Bureau of Economic Analysis | first1 = Bruce T. | last1 = Grimm | first2 = Brent R. | last2 = Moulton | first3 = David B. | last3 = Wasshausen | date = 2002 |access-date=2014-05-15}}</ref> which reached 3.4% per year in 1997–2004, outpacing the 1.6% per year during both 1972–1996 and 2005–2013.<ref>{{cite web|url=http://research.stlouisfed.org/fred2/series/OPHNFB |title=Nonfarm Business Sector: Real Output Per Hour of All Persons |publisher=Federal Reserve Bank of St. Louis Economic Data |year=2014 |access-date=2014-05-27}}</ref> As economist Richard G. Anderson notes, "Numerous studies have traced the cause of the productivity acceleration to technological innovations in the production of semiconductors that sharply reduced the prices of such components and of the products that contain them (as well as expanding the capabilities of such products)."<ref>{{cite web|url=http://research.stlouisfed.org/publications/es/07/ES0707.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://research.stlouisfed.org/publications/es/07/ES0707.pdf |archive-date=2022-10-09 |url-status=live |title=How Well Do Wages Follow Productivity Growth? |publisher=Federal Reserve Bank of St. Louis Economic Synopses | first = Richard G. | last = Anderson | date = 2007 |access-date=2014-05-27}}</ref>

The primary negative implication of Moore's law is that [[obsolescence]] pushes society up against the [[Limits to Growth]]. As technologies continue to rapidly improve, they render predecessor technologies obsolete. In situations in which security and survivability of hardware or data are paramount, or in which resources are limited, rapid obsolescence often poses obstacles to smooth or continued operations.<ref>{{cite magazine |title=Trapped on Technology's Trailing Edge |magazine=IEEE Spectrum |date=April 2008 |access-date=2011-11-27 |url=https://spectrum.ieee.org/trapped-on-technologys-trailing-edge |first = Peter | last = Sandborn | author-link = Peter Sandborn}}</ref>

[[File:Intel.svg|thumb|upright=1.4|Intel transistor gate length trend. Transistor scaling]]

== Other formulations and similar observations ==
Several measures of digital technology are improving at exponential rates related to Moore's law, including the size, cost, density, and speed of components. Moore wrote only about the density of components, "a component being a transistor, resistor, diode or capacitor",<ref name=Moore1995 >{{cite web|url=http://www.lithoguru.com/scientist/CHE323/Moore1995.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.lithoguru.com/scientist/CHE323/Moore1995.pdf |archive-date=2022-10-09 |url-status=live |title=Lithography and the future of Moore's law |publisher=[[SPIE]] |last=Moore |first=Gordon E.|author-link=Gordon Moore |year=1995 |access-date=2014-05-27}}</ref> at minimum cost.

''Transistors per integrated circuit'' – The most popular formulation is of the doubling of the number of transistors on ICs every two years. At the end of the 1970s, Moore's law became known as the limit for the number of transistors on the most complex chips. The graph at the top of this article shows this trend holds true today. {{as of|2025}}, the commercially available processor possessing one of the highest numbers of transistors is a [[GeForce 50 series|GB202 graphics processor]] with more than 92.2&nbsp;billion transistors.<ref>{{cite web|url=https://www.techpowerup.com/gpu-specs/geforce-rtx-5090.c4216 |title=NVIDIA GB202|publisher= TechPowerUp|date=2025}}</ref>

''Density at minimum cost per transistor'' – This is the formulation given in Moore's 1965 paper.<ref name="Moore 1965"/> It is not just about the density of transistors that can be achieved, but about the density of transistors at which the cost per transistor is the lowest.<ref>{{cite web|last=Stokes |first=Jon |url=https://arstechnica.com/hardware/news/2008/09/moore.ars |title=Understanding Moore's Law |website=Ars Technica |date=2008-09-27 |access-date=2011-08-22}}</ref>

As more transistors are put on a chip, the cost to make each transistor decreases, but the chance that the chip will not work due to a defect increases. In 1965, Moore examined the density of transistors at which cost is minimized, and observed that, as transistors were made smaller through advances in [[photolithography]], this number would increase at "a rate of roughly a factor of two per year".<ref name="Moore 1965" />

''Dennard scaling'' – This posits that power usage would decrease in proportion to area (both voltage and current being proportional to length) of transistors. Combined with Moore's law, [[performance per watt]] would grow at roughly the same rate as transistor density, doubling every 1–2 years. According to Dennard scaling transistor dimensions would be scaled by 30% (0.7×) every technology generation, thus reducing their area by 50%. This would reduce the delay by 30% (0.7×) and therefore increase operating frequency by about 40% (1.4×). Finally, to keep electric field constant, voltage would be reduced by 30%, reducing energy by 65% and power (at 1.4× frequency) by 50%.{{efn|Active power {{=}} ''CV''<sup>2</sup>''f''}} Therefore, in every technology generation transistor density would double, circuit becomes 40% faster, while power consumption (with twice the number of transistors) stays the same.<ref>{{cite journal| url=http://cacm.acm.org/magazines/2011/5/107702-the-future-of-microprocessors/fulltext |access-date=2011-11-27 |title=The Future of Microprocessors|date=May 2011| first1 = Shekhar | last1 = Borkar | first2 = Andrew A. | last2 = Chien|journal=Communications of the ACM  |volume=54 |issue=5 |page=67 | doi=10.1145/1941487.1941507
|citeseerx=10.1.1.227.3582 |s2cid=11032644 }}</ref> Dennard scaling ended in 2005–2010, due to leakage currents.<ref name="Turing Award Lecture 2018" />

The exponential processor transistor growth predicted by Moore does not always translate into exponentially greater practical CPU performance. Since around 2005–2007, Dennard scaling has ended, so even though Moore's law continued after that, it has not yielded proportional dividends in improved performance.<ref name="cartesian">{{cite web|url=http://cartesianproduct.wordpress.com/2013/04/15/the-end-of-dennard-scaling/|title = The end of Dennard scaling|date = April 15, 2013|last = McMenamin|first = Adrian|access-date = January 23, 2014}}</ref><ref name="retrospective">{{cite web|url=http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07.pdf |archive-url=https://web.archive.org/web/20131111040130/http://www.eng.auburn.edu/~agrawvd/COURSE/READING/LOWP/Boh07.pdf |archive-date=2013-11-11 |url-status=live|title = A 30 Year Retrospective on Dennard's MOSFET Scaling Paper|publisher = Solid-State Circuits Society|last = Bohr|first = Mark|date = January 2007|access-date = January 23, 2014}}</ref> The primary reason cited for the breakdown is that at small sizes, current leakage poses greater challenges, and also causes the chip to heat up, which creates a threat of [[thermal runaway]] and therefore, further increases energy costs.<ref name="cartesian" /><ref name="retrospective" /><ref name="Turing Award Lecture 2018" />

The breakdown of Dennard scaling prompted a greater focus on multicore processors, but the gains offered by switching to more cores are lower than the gains that would be achieved had Dennard scaling continued.<ref>{{cite web|url=http://www.cc.gatech.edu/~hadi/doc/paper/2012-toppicks-dark_silicon.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.cc.gatech.edu/~hadi/doc/paper/2012-toppicks-dark_silicon.pdf |archive-date=2022-10-09 |url-status=live|title = Dark Silicon and the end of multicore scaling|last1 = Esmaeilzedah|first1 = Hadi|last2 = Blem|first2 = Emily|last3 = St. Amant|first3 = Renee|last4 = Sankaralingam|first4 = Kartikeyan|last5 = Burger|first5 = Doug}}</ref><ref>{{cite web |last=Hruska |first=Joel |date=February 1, 2012 |title=The death of CPU scaling: From one core to many – and why we're still stuck |url=http://www.extremetech.com/computing/116561-the-death-of-cpu-scaling-from-one-core-to-many-and-why-were-still-stuck |access-date=January 23, 2014 |publisher=[[ExtremeTech]]}}</ref> In another departure from Dennard scaling, Intel microprocessors adopted a non-planar tri-gate FinFET at 22&nbsp;nm in 2012 that is faster and consumes less power than a conventional planar transistor.<ref>{{cite web |url=http://www.semiconwest.org/sites/semiconwest.org/files/docs/Kaizad%20Mistry_Intel.pdf |title=Tri-Gate Transistors: Enabling Moore's Law at 22nm and Beyond |publisher=Intel Corporation at semiconwest.org |first=Kaizad |last=Mistry |date=2011 |access-date=2014-05-27 |archive-url=https://web.archive.org/web/20150623193119/http://www.semiconwest.org/sites/semiconwest.org/files/docs/Kaizad%20Mistry_Intel.pdf |archive-date=2015-06-23 }}</ref> The rate of performance improvement for single-core microprocessors has slowed significantly.<ref name="Turing Award Lecture slides">{{cite web |last1=Hennessy |first1=John L. |author1-link=John L. Hennessy |last2=Patterson |first2=David A. |author2-link=David Patterson (computer scientist) |date=June 4, 2018 |title=A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development |url=https://iscaconf.org/isca2018/docs/HennessyPattersonTuringLectureISCA4June2018.pdf |url-status=live |archive-url=https://ghostarchive.org/archive/20221009/https://iscaconf.org/isca2018/docs/HennessyPattersonTuringLectureISCA4June2018.pdf |archive-date=2022-10-09 |publisher=International Symposium on Computer Architecture – ISCA 2018 |quote=End of Growth of Single Program Speed?}}</ref> Single-core performance was improving by 52% per year in 1986–2003 and 23% per year in 2003–2011, but slowed to just seven percent per year in 2011–2018.<ref name="Turing Award Lecture slides" />

''Quality adjusted price of IT equipment'' – The [[Price index|price]] of information technology (IT), computers and peripheral equipment, adjusted for quality and inflation, declined 16% per year on average over the five decades from 1959 to 2009.<ref name=ITprices >{{cite web|url=http://research.stlouisfed.org/fred2/series/B935RG3Q086SBEA |title=Private fixed investment, chained price index: Nonresidential: Equipment: Information processing equipment: Computers and peripheral equipment |publisher=[[Federal Reserve Bank of St. Louis]] |year=2014 |access-date=2014-05-12}}</ref><ref name=NambiarPoess >{{cite book|volume = 6417|pages = 110–120| first1 = Raghunath | last1 = Nambiar | first2 = Meikel | last2 = Poess| title=Performance Evaluation, Measurement and Characterization of Complex Systems | chapter=Transaction Performance vs. Moore's Law: A Trend Analysis |publisher=[[Springer Science+Business Media|Springer]] | date = 2011 |doi=10.1007/978-3-642-18206-8_9|series = Lecture Notes in Computer Science|isbn = 978-3-642-18205-1|s2cid = 31327565}}</ref> The pace accelerated, however, to 23% per year in 1995–1999 triggered by faster IT innovation,<ref name=Jorgenson01 >{{cite web|url=http://www.worldklems.net/conferences/worldklems2014/worldklems2014_Ho.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.worldklems.net/conferences/worldklems2014/worldklems2014_Ho.pdf |archive-date=2022-10-09 |url-status=live |title=Long-term Estimates of U.S. Productivity and Growth |publisher=World KLEMS Conference | first1 = Dale W. | last1 = Jorgenson| author-link = Dale W. Jorgenson | first2 = Mun S. | last2 = Ho | first3 = Jon D. | last3 = Samuels | date = 2014 |access-date=2014-05-27}}</ref> and later, slowed to 2% per year in 2010–2013.<ref name=ITprices/><ref>{{cite web|url=http://blogs.elis.org/isa/files/2013/02/report_jpmorgan.pdf |archive-url=https://web.archive.org/web/20140517115045/http://blogs.elis.org/isa/files/2013/02/report_jpmorgan.pdf |archive-date=2014-05-17 |url-status=live |title=US: is I.T. over? |publisher=JPMorgan Chase Bank NA Economic Research | first = Michael | last = Feroli | date = 2013 |access-date=2014-05-15}}</ref>

While [[Price index#Quality change|quality-adjusted]] microprocessor price improvement continues,<ref name="Byrne2013a"/> the rate of improvement likewise varies, and is not linear on a log scale. Microprocessor price improvement accelerated during the late 1990s, reaching 60% per year (halving every nine months) versus the typical 30% improvement rate (halving every two years) during the years earlier and later.<ref name=Aizcorbe01>{{cite web|url=http://www.federalreserve.gov/Pubs/FEDS/2006/200644/ |title=Shifting Trends in Semiconductor Prices and the Pace of Technological Progress |publisher=The Federal Reserve Board Finance and Economics Discussion Series | first1 = Ana | last1 = Aizcorbe | first2 = Stephen D. | last2 = Oliner | first3 = Daniel E. | last3 = Sichel | date = 2006 |access-date=2014-05-15}}</ref><ref>{{cite web |url=http://www.bea.gov/papers/pdf/semiconductorprices.pdf |title=Why Are Semiconductor Price Indexes Falling So Fast? Industry Estimates and Implications for Productivity Measurement |publisher=U.S. Department of Commerce Bureau of Economic Analysis |first=Ana |last=Aizcorbe |date=2005 |access-date=2014-05-15 |archive-url=https://web.archive.org/web/20170809160523/https://www.bea.gov/papers/pdf/semiconductorprices.pdf |archive-date=2017-08-09 }}</ref> Laptop microprocessors in particular improved 25–35% per year in 2004–2010, and slowed to 15–25% per year in 2010–2013.<ref name="Sun 2014" >{{cite web |url=http://repository.wellesley.edu/cgi/viewcontent.cgi?article=1284&context=thesiscollection |title=What We Are Paying for: A Quality Adjusted Price Index for Laptop Microprocessors |last=Sun |first=Liyang |publisher=Wellesley College |date=2014-04-25 |access-date=2014-11-07 |quote=... compared with −25% to −35% per year over 2004–2010, the annual decline plateaus around −15% to −25% over 2010–2013. |archive-date=2014-11-11 |archive-url=https://web.archive.org/web/20141111024422/http://repository.wellesley.edu/cgi/viewcontent.cgi?article=1284&context=thesiscollection }}</ref>

The number of transistors per chip cannot explain quality-adjusted microprocessor prices fully.<ref name=Aizcorbe01/><ref>{{cite web|url=http://www.bea.gov/papers/pdf/aizcorbe_kortum.pdf |archive-url=https://web.archive.org/web/20070605131130/http://www.bea.gov/papers/pdf/aizcorbe_kortum.pdf |archive-date=2007-06-05 |url-status=live |title=Moore's Law and the Semiconductor Industry: A Vintage Model |publisher=U.S. Department of Commerce Bureau of Economic Analysis | first1 = Ana | last1 = Aizcorbe | first2 = Samuel | last2 = Kortum | date = 2004 |access-date=2014-05-27}}</ref><ref>{{cite news|url=https://www.nytimes.com/2004/05/17/business/technology-intel-s-big-shift-after-hitting-technical-wall.html |title=Intel's Big Shift After Hitting Technical Wall |newspaper=New York Times | first = John | last = Markoff |author-link = John Markoff | date = 2004 |access-date=2014-05-27}}</ref> Moore's 1995 paper does not limit Moore's law to strict linearity or to transistor count, "The definition of 'Moore's Law' has come to refer to almost anything related to the semiconductor industry that on a [[semi-log plot]] approximates a straight line. I hesitate to review its origins and by doing so restrict its definition."<ref name=Moore1995/>

''Hard disk drive areal density'' – A similar prediction (sometimes called [[Mark Kryder|Kryder's law]]) was made in 2005 for [[hard disk drive]] [[areal density (computer storage)|areal density]].<ref>
{{cite news
 | first=Chip
 | last=Walter
 | url=https://www.scientificamerican.com/article/kryders-law/
 | title=Kryder's Law
 | work=Scientific American
 | publisher= (Verlagsgruppe Georg von Holtzbrinck GmbH)
 | date=2005-07-25
 | access-date=2006-10-29
}}</ref> The prediction was later viewed as over-optimistic. Several decades of rapid progress in areal density slowed around 2010, from 30 to 100% per year to 10–15% per year, because of noise related to [[Superparamagnetism#Effect on hard drives|smaller grain size]] of the disk media, thermal stability, and writability using available magnetic fields.<ref>
{{cite journal
 | title = New Paradigms in Magnetic Recording
 | last = Plumer |display-authors=etal
 | first = Martin L.
 | journal = Physics in Canada
 | volume =  67
 | issue = 1
 | date = March 2011
 | pages = 25–29
 | arxiv = 1201.5543
 | bibcode = 2012arXiv1201.5543P
}}</ref><ref name="Mellor 2014-11-10">{{cite news |last=Mellor |first=Chris |url=https://www.theregister.co.uk/2014/11/10/kryders_law_of_ever_cheaper_storage_disproven/ |title=Kryder's law craps out: Race to UBER-CHEAP STORAGE is OVER |work=theregister.co.uk |location=UK |publisher=The Register |date=2014-11-10 |access-date=2014-11-12 |quote=Currently 2.5-inch drives are at 500GB/platter with some at 600GB or even 667GB/platter – a long way from 20TB/platter. To reach 20TB by 2020, the 500GB/platter drives will have to increase areal density 44 times in six years. It isn't going to happen. ... Rosenthal writes: "The technical difficulties of migrating from PMR to HAMR, meant that already in 2010 the Kryder rate had slowed significantly and was not expected to return to its trend in the near future. The floods reinforced this." }}</ref>

''Fiber-optic capacity'' – The number of bits per second that can be sent down an optical fiber increases exponentially, faster than Moore's law. '''Keck's law''', in honor of [[Donald Keck]].<ref>
{{cite web |last=Hecht |first=Jeff |date=2016 |title=Is Keck's Law Coming to an End? – IEEE Spectrum |url=https://spectrum.ieee.org/is-kecks-law-coming-to-an-end |access-date=2023-06-16 |website=[[IEEE]] |language=en}}
</ref>

''Network capacity'' – According to Gerald Butters,<ref>{{cite magazine|url=https://www.forbes.com/finance/mktguideapps/personinfo/FromPersonIdPersonTearsheet.jhtml?passedPersonId=922126 |archive-url=https://web.archive.org/web/20071012201431/http://www.forbes.com/finance/mktguideapps/personinfo/FromPersonIdPersonTearsheet.jhtml?passedPersonId=922126 |archive-date=2007-10-12 |title=Gerald Butters is a communications industry veteran |magazine=Forbes.com}}</ref><ref>{{cite web|url=http://www.lambdaopticalsystems.com/about-board-dir.php |title=Board of Directors |publisher=LAMBDA OpticalSystems |access-date=2011-08-22}}</ref> the former head of Lucent's Optical Networking Group at Bell Labs, there is another version, called Butters' Law of Photonics,<ref>{{cite web|url=http://www.tmcnet.com/articles/comsol/0100/0100pubout.htm |title=As We May Communicate |publisher=Tmcnet.com | first = Rich | last = Tehrani |access-date=2011-08-22}}</ref> a formulation that deliberately parallels Moore's law. Butters' law says that the amount of data coming out of an optical fiber is doubling every nine months.<ref>{{cite magazine |url=http://www.eetimes.com/story/OEG20000926S0065 |title=Speeding net traffic with tiny mirrors |magazine=[[EE Times]] |date=2000-09-26 |first=Gail |last=Robinson |access-date=2011-08-22 |archive-date=2010-01-07 |archive-url=https://web.archive.org/web/20100107113634/http://eetimes.com/story/OEG20000926S0065 }}</ref> Thus, the cost of transmitting a bit over an optical network decreases by half every nine months. The availability of [[wavelength-division multiplexing]] (sometimes called WDM) increased the capacity that could be placed on a single fiber by as much as a factor of 100. Optical networking and [[dense wavelength-division multiplexing]] (DWDM) is rapidly bringing down the cost of networking, and further progress seems assured. As a result, the wholesale price of data traffic collapsed in the [[dot-com bubble]]. [[Nielsen's Law]] says that the bandwidth available to users increases by 50% annually.<ref>{{cite web|url=http://www.useit.com/alertbox/980405.html |title=Nielsen's Law of Internet Bandwidth |publisher=Alertbox | first = Jakob | last = Nielsen |date=1998-04-05 |access-date=2011-08-22}}</ref>

''Pixels per dollar'' – Similarly, Barry Hendy of Kodak Australia has plotted pixels per dollar as a basic measure of value for a digital camera, demonstrating the historical linearity (on a log scale) of this market and the opportunity to predict the future trend of digital camera price, [[LCD]] and [[LED]] screens, and resolution.<ref>{{cite news |url=http://www.theaustralian.com.au/archive/news/trust-the-power-of-technology/story-e6frg6q6-1225696991379 |title=Trust the power of technology |date=2009-04-09 |access-date=2013-12-02 | first = Ziggy | last = Switkowski |newspaper=The Australian}}</ref><ref>{{cite book |url=https://www.cs.cornell.edu/people/egs/papers/lesser-known-laws.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.cs.cornell.edu/people/egs/papers/lesser-known-laws.pdf |archive-date=2022-10-09 |url-status=live |title=Some Lesser-Known Laws of Computer Science | first1 = Emin Gün | last1 = Sirer | author-link = Emin Gün Sirer | first2 = Rik | last2 = Farrow |access-date=2013-12-02}}</ref><ref>{{cite web |url=http://antranik.org/using-moores-law-to-predict-future-memory-trends/ |title=Using Moore's Law to Predict Future Memory Trends |date=2011-11-21 |access-date=2013-12-02}}</ref><ref name="Myhrvold"/>

''The great Moore's law compensator (TGMLC)'', also known as [[Wirth's law]], is the principle that successive generations of computer software increase in size and complexity ([[software bloat]]), thereby offsetting the performance gains predicted by Moore's law. In a 2008 article in [[InfoWorld]], Randall C. Kennedy,<ref>{{cite magazine|last=Kennedy |first=Randall C. |url=http://www.infoworld.com/t/applications/fat-fatter-fattest-microsofts-kings-bloat-278?page=0,4 |title=Fat, fatter, fattest: Microsoft's kings of bloat |magazine=InfoWorld |date=2008-04-14 |access-date=2011-08-22}}</ref> formerly of Intel, introduces this term using successive versions of [[Microsoft Office]] between the year 2000 and 2007 as his premise. Despite the gains in computational performance during this time period according to Moore's law, Office 2007 performed the same task at half the speed on a prototypical year 2007 computer as compared to Office 2000 on a year 2000 computer.{{cn|date=August 2025}}

''Library expansion'' – was calculated in 1945 by [[Fremont Rider]] to double in capacity every 16 years, if sufficient space were made available.<ref name="The Scholar">{{cite book |last=Rider |first=Fremont |title=The Scholar and the Future of the Research Library |publisher=Hadham Press |year=1944 |oclc=578215272}}</ref> He advocated replacing bulky, decaying printed works with miniaturized [[microform]] analog photographs, which could be duplicated on-demand for library patrons or other institutions. He did not foresee the digital technology that would follow decades later to replace analog microform with digital imaging, storage, and transmission media. Automated, potentially lossless digital technologies allowed vast increases in the rapidity of information growth in an era that now sometimes is called the [[Information Age]].{{cn|date=August 2025}}

''[[Carlson curve]]'' – is a term coined by ''The Economist''<ref>Life 2.0. (August 31, 2006). The Economist.</ref> to describe the biotechnological equivalent of Moore's law, and is named after author Rob Carlson.<ref>{{cite book | last = Carlson | first = Robert H. | title = Biology Is Technology: The Promise, Peril, and New Business of Engineering Life | publisher = Harvard University Press | date = 2010 |url={{GBurl|NGTbnaXOKD8C|pg=PP6}} |isbn=978-0-674-05362-5}}</ref> Carlson accurately predicted that the doubling time of DNA sequencing technologies (measured by cost and performance) would be at least as fast as Moore's law.<ref>{{cite journal |last=Carlson |first=Robert H. |date=September 2003 |title=The Pace and Proliferation of Biological Technologies |journal=Biosecurity and Bioterrorism: Biodefense Strategy, Practice, and Science |volume=1 |issue=3 |pages=203–214 |doi=10.1089/153871303769201851 |pmid=15040198 |s2cid=18913248}}</ref> Carlson Curves illustrate the rapid (in some cases hyperexponential) decreases in cost, and increases in performance, of a variety of technologies, including DNA sequencing, DNA synthesis, and a range of physical and computational tools used in protein expression and in determining protein structures.{{cn|date=August 2025}}

''[[Eroom's law]]'' – is a pharmaceutical drug development observation that was deliberately written as Moore's Law spelled backward in order to contrast it with the exponential advancements of other forms of technology (such as transistors) over time. It states that the cost of developing a new drug roughly doubles every nine years.{{cn|date=August 2025}}

''[[Experience curve effects]]'' says that each doubling of the cumulative production of virtually any product or service is accompanied by an approximate constant percentage reduction in the unit cost. The acknowledged first documented qualitative description of this dates from 1885.<ref name="ebbing_book">{{cite book |url=https://books.google.com/books?id=oRSMDF6y3l8C |title=Memory: A Contribution to Experimental Psychology |last=Ebbinghaus |first=Hermann |author-link=Hermann Ebbinghaus |publisher=Columbia University |date=1913 |page=42, Figure 2|isbn=978-0-7222-2928-6 }}</ref><ref name="books.google.com">{{cite web |url=https://books.google.com/books?id=ikEMAAAAIAAJ&q=%22learning+curve%22 |title=The American Journal of Psychology |volume=14 |date=1903 |first1=Granville Stanley |last1=Hall |first2=Edward Bradford |last2=Titchene}}</ref> A power curve was used to describe this phenomenon in a 1936 discussion of the cost of airplanes.<ref>{{cite journal |last=Wright |first=T. P. |date=1936 |title=Factors Affecting the Cost of Airplanes |journal=Journal of the Aeronautical Sciences |volume=3 |issue=4 |pages=122–128|doi=10.2514/8.155 }}</ref>

''[[Edholm's law]]'' – Phil Edholm observed that the [[Bandwidth (signal processing)|bandwidth]] of [[telecommunication network]]s (including the Internet) is doubling every 18 months.<ref name="Cherry">{{cite journal |last1=Cherry |first1=Steven |title=Edholm's law of bandwidth |journal=IEEE Spectrum |date=2004 |volume=41 |issue=7 |pages=58–60 |doi=10.1109/MSPEC.2004.1309810|s2cid=27580722 }}</ref> The bandwidths of online [[communication networks]] has risen from [[bits per second]] to [[terabits per second]]. The rapid rise in online bandwidth is largely due to the same MOSFET scaling that enabled Moore's law, as telecommunications networks are built from MOSFETs.<ref name="Jindal">{{cite book |last1=Jindal |first1=R. P. |title=2009 2nd International Workshop on Electron Devices and Semiconductor Technology |date=2009 |isbn=978-1-4244-3831-0 |pages=1–6 |chapter=From millibits to terabits per second and beyond – over 60 years of innovation |doi=10.1109/EDST.2009.5166093 |chapter-url=https://events.vtools.ieee.org/m/195547 |s2cid=25112828}}</ref>

''[[Haitz's law]]'' predicts that the brightness of LEDs increases as their manufacturing cost goes down.{{cn|date=August 2025}}

''[[Swanson's law]]'' is the observation that the price of solar photovoltaic modules tends to drop 20 percent for every doubling of cumulative shipped volume. At present rates, costs go down 75% about every 10 years.{{cn|date=August 2025}}

== See also ==
* {{Annotated link|Accelerating change}}
* {{Annotated link|Beyond CMOS}}
* [[Quantum computing scaling laws]] – Scaling trends in quantum computing
* {{Annotated link|Ephemeralization}}
* {{Annotated link|Eroom's law}}
* {{Annotated link|Huang's law}}
* {{Annotated link|Koomey's law}}
* {{Annotated link|Limits of computation}}
* {{Annotated link|List of eponymous laws}}
* {{Section link|List of laws|Technology}}
* {{Annotated link|Microprocessor chronology}}
* {{Annotated link|Neural scaling law}}
* {{Annotated link|Power law}}
* {{Annotated link|Wirth's law}}
* {{Annotated link|Rent's rule}}

== Explanatory notes ==
{{notelist}}

== References ==
<references>
<ref name="Moore 1965">{{cite web|last1=Moore|first1=Gordon E.|title=Cramming more components onto integrated circuits|url=http://cva.stanford.edu/classes/cs99s/papers/moore-crammingmorecomponents.pdf |archive-url=https://web.archive.org/web/20190327213847/https://newsroom.intel.com/wp-content/uploads/sites/11/2018/05/moores-law-electronics.pdf |archive-date=2019-03-27 |url-status=live |website=intel.com |access-date=April 1, 2020 |author-link=Gordon Moore |publisher=[[Electronics Magazine]]  |date=1965-04-19}}</ref>
<ref name=Disco1998>
{{cite book
 | last1 = Disco
 | first1 = Cornelius
 | last2 = van der Meulen
 | first2 = Barend
 | year = 1998
 | title = Getting new technologies together
 | pages = 206–7
 | isbn = 978-3-11-015630-0
 | publisher = Walter de Gruyter
 | oclc = 39391108
 | url = https://books.google.com/books?id=1khslZ-jbgEC&pg=PA206
 | access-date = August 23, 2008
}}</ref>
<ref name="Moore 1975b" >{{cite web |last1=Moore |first1=Gordon |title=IEEE Technical Digest 1975 |date=1975 |url=http://www.eng.auburn.edu/~agrawvd/COURSE/E7770_Spr07/READ/Gordon_Moore_1975_Speech.pdf |archive-url=https://ghostarchive.org/archive/20221009/http://www.eng.auburn.edu/~agrawvd/COURSE/E7770_Spr07/READ/Gordon_Moore_1975_Speech.pdf |archive-date=2022-10-09 |url-status=live |access-date=April 7, 2015 |publisher=Intel Corp. |quote=... the rate of increase of complexity can be expected to change slope in the next few years as shown in Figure 5. The new slope might approximate a doubling every two years, rather than every year, by the end of the decade. }}</ref>
<ref name="Byrne2013a">{{cite conference |last1=Byrne |first1=David M. |last2=Oliner |first2=Stephen D. |last3=Sichel |first3=Daniel E. |title=Is the Information Technology Revolution Over? |url=http://www.federalreserve.gov/pubs/feds/2013/201336/201336pap.pdf |conference=Finance and Economics Discussion Series Divisions of Research & Statistics and Monetary Affairs Federal Reserve Board |publisher=Federal Reserve Board Finance and Economics Discussion Series (FEDS) |place=Washington, D.C. |date=March 2013 |url-status=live |archive-url=https://web.archive.org/web/20140609182110/http://www.federalreserve.gov/pubs/feds/2013/201336/201336pap.pdf |archive-date=2014-06-09 |quote=technical progress in the semiconductor industry has continued to proceed at a rapid pace ... Advances in semiconductor technology have driven down the constant-quality prices of MPUs and other chips at a rapid rate over the past several decades. }}</ref>
<ref name="Myhrvold">{{cite news | title = Moore's Law Corollary: Pixel Power | first = Nathan | last = Myhrvold | author-link = Nathan Myhrvold | work = [[The New York Times]] | date = June 7, 2006 | url = https://www.nytimes.com/2006/06/07/technology/circuits/07essay.html |access-date=2011-11-27}}</ref>
<ref name="Rauch">
{{cite news
 | first = Jonathan
 | last = Rauch
 | author-link = Jonathan Rauch
 | date = January 2001
 | title = The New Old Economy: Oil, Computers, and the Reinvention of the Earth
 | magazine = [[The Atlantic Monthly]]
 | url = https://www.theatlantic.com/issues/2001/01/rauch.htm
 | access-date = November 28, 2008
}}</ref>
<ref name="Keyes 2006">
{{cite journal
 | first = Robert W.
 | last = Keyes
 | date = September 2006
 | title = The Impact of Moore's Law
 | journal = IEEE Solid-State Circuits Society Newsletter
 | volume = 11
 | issue = 3
 | pages = 25–27
 | doi = 10.1109/N-SSC.2006.4785857
 }}</ref>
<ref name="Liddle 2006">
{{cite journal
 | first = David E.
 | last = Liddle
 | author-link = David Liddle
 | date = September 2006
 | title = The Wider Impact of Moore's Law
 | journal = IEEE Solid-State Circuits Society Newsletter
 | volume = 11
 | issue = 3
 | pages = 28–30
 | url = http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2165&path=sscs/06Sept&file=Liddle.xml
 | archive-url = https://web.archive.org/web/20070713083559/http://www.ieee.org/portal/site/sscs/menuitem.f07ee9e3b2a01d06bb9305765bac26c8/index.jsp?&pName=sscs_level1_article&TheCat=2165&path=sscs/06Sept&file=Liddle.xml
 | archive-date = 2007-07-13
 | access-date = March 25, 2023 | doi = 10.1109/N-SSC.2006.4785858
 | s2cid = 29759395
}}</ref>
<ref name="Kendrick 1961 3">
{{cite book
 |title=Productivity Trends in the United States
 |last=Kendrick
 |first=John W.
 |author-link=John Whitefield Kendrick
 |year=1961 |publisher= Princeton University Press for NBER|page= 3
}}</ref>
<ref name="Moore 2015a">
{{cite interview |last=Moore |first=Gordon |interviewer=Rachel Courtland |title=Gordon Moore: The Man Whose Name Means Progress, The visionary engineer reflects on 50 years of Moore's Law |magazine=IEEE Spectrum: Special Report: 50 Years of Moore's Law |url=https://spectrum.ieee.org/gordon-moore-the-man-whose-name-means-progress |quote=We won't have the rate of progress that we've had over the last few decades. I think that's inevitable with any technology; it eventually saturates out. I guess I see Moore's law dying here in the next decade or so, but that's not surprising. |date=March 30, 2015
}}</ref>
<ref name="Turing Award Lecture 2018" >{{cite web|url= https://iscaconf.org/isca2018/turing_lecture.html |title= A New Golden Age for Computer Architecture: Domain-Specific Hardware/Software Co-Design, Enhanced Security, Open Instruction Sets, and Agile Chip Development |author1= John L. Hennessy |author2= David A. Patterson |publisher= International Symposium on Computer Architecture – ISCA 2018| quote= In the later 1990s and 2000s, architectural innovation decreased, so performance came primarily from higher clock rates and larger caches. The ending of Dennard Scaling and Moore's Law also slowed this path; single core performance improved only 3% last year! |date = June 4, 2018 }}</ref>
<ref name="Bradshaw">{{cite news | title = Intel chief raises doubts over Moore's law | first = Tim | last = Bradshaw | work = Financial Times| date = July 16, 2015 | url = https://www.ft.com/content/36b722bc-2b49-11e5-8613-e7aedbb7bdb7 | access-date=2015-07-16}}</ref>
<ref name="Waters">{{cite news | title = As Intel co-founder's law slows, a rethinking of the chip is needed | first = Richard | last = Waters| work = Financial Times| date = July 16, 2015 | url = http://www.ft.com/intl/cms/s/0/4d8dabaa-2bd5-11e5-acfb-cbd2e1c81cca.html}}</ref>
<ref name="Niccolai">{{cite news | title = Intel pushes 10nm chip-making process to 2017, slowing Moore's Law | first = James | last = Niccolai | work = Infoworld | date = July 15, 2015 | url = http://www.infoworld.com/article/2949153/hardware/intel-pushes-10nm-chipmaking-process-to-2017-slowing-moores-law.html |quote=It's official: Moore's Law is slowing down.&nbsp;... "These transitions are a natural part of the history of Moore's Law and are a by-product of the technical challenges of shrinking transistors while ensuring they can be manufactured in high volume", Krzanich said.  |access-date=2015-07-16}}</ref>
</references>

== Further reading ==
* {{cite book |editor-last=Brock |editor-first=David C. |date=2006 |title=Understanding Moore's Law: Four Decades of Innovation |location=Philadelphia |publisher=Chemical Heritage Foundation |isbn=0-941901-41-6 |oclc=66463488}}
* {{cite book |last1=Mody |first1=Cyrus |title=The Long Arm of Moore's law: Microelectronics and American Science |date=2016 |location=Cambridge, Massachusetts |publisher=Massachusetts Institute of Technology Press |isbn=978-0-262-03549-1}}
* {{cite book |last1=Thackray |first1=Arnold |first2=David C. |last2=Brock |first3=Rachel |last3=Jones |date=2015 |title=Moore's Law: The Life of Gordon Moore, Silicon Valley's Quiet Revolutionary |location=New York |publisher=Basic Books |isbn=978-0-465-05564-7 |oclc=0465055648}}
* {{cite journal |last=Tuomi |first=Ilkka |date=November 2002 |title=The Lives and Death of Moore's Law |journal=First Monday |volume=7 |issue=11 |doi=10.5210/fm.v7i11.1000 |doi-access=free }}

== External links ==
{{Wikibooks|The Information Age}}
* [https://www.intel.com/pressroom/kits/events/moores_law_40th/index.htm Intel press kit] – released for Moore's Law's 40th anniversary, with a [https://www.intel.com/pressroom/kits/events/moores_law_40th/Images_Assets/graph.jpg 1965 sketch] by Moore
* [http://www.slideshare.net/Christiansandstrom/no-technology-has-been-more-disruptive-presentation/ No Technology has been more disruptive...] Slide show of microchip growth
* [https://web.archive.org/web/20090830042915/http://wi-fizzle.com/compsci/ Intel (IA-32) CPU speeds 1994–2005] – speed increases in recent years have seemed to slow with regard to percentage increase per year (available in PDF or PNG format)
* [https://web.archive.org/web/20151228041321/http://www.itrs.net/ International Technology Roadmap for Semiconductors (ITRS)]
* {{webarchive |date=2013-01-02 |url=https://archive.today/20130102082556/http://news.com.com/FAQ+Forty+years+of+Moores+Law/2100-1006_3-5647824.html?tag=nefd.lede |title=A C{{!}}net FAQ about Moore's Law}}
* [https://www.youtube.com/watch?v=EzyJxAP6AQo ASML's 'Our Stories', Gordon Moore about Moore's Law], [[ASML Holding]]
* {{cite web |title=Why Moore's Law Matters  |date=March 2023 |work=Asianometry |via=YouTube |url=https://www.youtube.com/watch?v=nRJgvX6P8dI }}
* [https://www.intel.com/content/www/us/en/newsroom/resources/moores-law.html Moore's Law] at Intel

{{Computer laws}}
{{Emerging technologies|topics=yes}}
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[[Category:1965 introductions]]
[[Category:Computer architecture statements]]
[[Category:Digital Revolution]]
[[Category:Eponymous rules]]
[[Category:History of computing hardware]]
[[Category:MOSFETs]]
[[Category:Prediction]]
[[Category:Rules of thumb]]
[[Category:Technological change]]