View source for OpenRISC

{{Short description|Microprocessor development project}}
{{Infobox CPU architecture
| name       = OpenRISC
| designer   = Originally Damjan Lampret, now the [https://openrisc.io/community OpenRISC Community] (Stafford Horne etc.)
| bits       = [[32-bit]], [[64-bit]]
| introduced = {{Start date and age|2000}}
| version    = 1.4<ref>{{cite web|url=https://openrisc.io/architecture#published-versions|title=Published versions|access-date=2021-03-28}}</ref>
| design     = [[Reduced instruction set computer|RISC]]
| type       = 
| encoding   = Fixed
| branching  = 
| endianness = Big; unimplemented stub for Little
| page size  = 8 KiB
| extensions = ORFPX32/64,<ref>{{cite web|url=https://openrisc.io/architecture#basic-features|title=Floating point extensions operating on 32-bit/64-bit|access-date=2021-03-28}}</ref> ORVDX64<ref>{{cite web|url=https://openrisc.io/architecture#basic-features|title=Vector/DSP extensions (SIMD) operating on 8-, 16-, 32- and 64-bit data|access-date=2021-03-28}}</ref>
| open       = Yes (LGPL / GPL), hence royalty free
| registers  = 
| gpr        = 16 or 32
| fpr        = Optional
}}

'''OpenRISC''' is a project to develop a series of [[open-source hardware]] based [[central processing unit]]s (CPUs) on established [[reduced instruction set computer]] (RISC) principles. It includes an [[instruction set architecture]] (ISA) using an [[open-source license]]. It is the original flagship project of the [[OpenCores]] community.

The first (and {{as of|2019|lc=y}} only) architectural description is for the OpenRISC 1000 ("OR1k"), describing a family of [[32-bit]] and [[64-bit]] processors with optional [[floating-point arithmetic]] and [[Vector processor|vector processing]] support.<ref>{{cite web|url=https://openrisc.io/architecture|website=OpenRisc.io|access-date=2021-04-17| title=Architecture - OpenRISC }}</ref>
The [[OpenRISC 1200]] implementation of this specification was designed by Damjan Lampret in 2000, written in the [[Verilog]] [[hardware description language]] (HDL).<ref>{{cite news |last=Clarke |first=Peter |date=2000-02-28 |title=Free 32-bit processor core hits the Net |url=https://www.eetimes.com/document.asp?doc_id=1214097 |work=Electronic Engineering Times ([[EE Times]]) |publisher=AspenCore Media |location=[[San Francisco]], California, United States |access-date=2019-03-21}}</ref> The later mor1kx implementation, which has some advantages compared to the OR 1200,<ref>{{cite web|url=https://openrisc.io/implementations#mor1kx|website=OpenRisc.io|access-date=2021-04-17| title=Implementations - OpenRISC }}</ref> was designed by Julius Baxter and is also written in Verilog. Software simulators also exist<ref>{{cite web|url=https://openrisc.io/implementations#system-simulators|website=OpenRisc.io|access-date=2021-04-17| title=Implementations - OpenRISC }}</ref> which implement the OR1k specification. 

The hardware design was released under the [[GNU Lesser General Public License]] (LGPL), while the models and firmware were released under the [[GNU General Public License]] (GPL).

A reference [[system on a chip]] (SoC) implementation based on the OpenRISC 1200 was developed, named the ''OpenRISC Reference Platform System-on-Chip'' (ORPSoC). Several groups have demonstrated ORPSoC and other OR1200 based designs running on [[field-programmable gate array]]s (FPGAs),<ref>{{cite web |last1=Pelgrims |first1=Patrick |last2=Tierens |first2=Tom |last3=Driessens |first3=Dries |date=2004 |url=http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf |title=Basic Custom OpenRISC System Hardware Tutorial: Embedded system design based upon Soft- and Hardcore FPGAs |version=1.0 |website=De Nayer Instituut |access-date=2009-03-03 |archive-url=https://web.archive.org/web/20061127055325/http://emsys.denayer.wenk.be/empro/openrisc-HW-tutorial-Xilinx.pdf |archive-date=2006-11-27}}</ref><ref>{{cite thesis |last1=Li |first1=Xiang |last2=Zuo |first2=Lin |title=Open source embedded platform based on OpenRISC and DE2-70 |type=Masters |publisher=[[KTH Royal Institute of Technology]] (KTH), Sweden |url=http://www.olivercamel.com/post/master_thesis.html |archive-url=https://web.archive.org/web/20111006172138/http://www.olivercamel.com/post/master_thesis.html |archive-date=2011-10-06 |url-status=dead }}, SoC program</ref> and there have been several commercial derivatives produced.

Later SoC designs, also based on an OpenRisc 1000 CPU implementation, are minSoC, OpTiMSoC and MiSoC.<ref>{{cite web|url=https://openrisc.io/soc|website=OpenRisc.io|access-date=2021-04-17| title=System-on-Chip - OpenRISC }}</ref>

==Instruction set==
The instruction set is a reasonably simple traditional RISC architecture reminiscent of [[MIPS architecture|MIPS]] using a 3-operand load-store architecture, with 16 or 32 general-purpose registers and a fixed 32-bit instruction length. The instruction set is mostly identical between the 32- and 64-bit versions of the specification, the main difference being the register width (32 or 64 bits) and page table layout. The OpenRISC specification includes all features common to modern desktop and server processors: a supervisor mode and virtual memory system, optional read, write, and execute control for memory pages, and instructions for synchronizing and interrupt handling between multiple processors.

Another notable feature is a rich set of ''single instruction, multiple data'' ([[SIMD]]) instructions intended for [[digital signal processing]].

==Implementations==
[[File:OpenRISC prototyped on Flextronics FPGA dev board. Running uClinux.jpg|thumbnail|OpenRISC prototyped on [[Flextronics]] (Flex) FPGA dev board, running uClinux]]

Most implementations are on [[field-programmable gate array]]s (FPGAs) which give the possibility to iterate on the design at the cost of performance.

By 2018, the OpenRISC 1000 was considered stable, so ORSoC (owner of OpenCores) began a [[crowdfunding]] project to build a cost-efficient [[application-specific integrated circuit]] (ASIC) to get improved performance. ORSoC faced criticism for this from the community.{{Citation needed|date=April 2018}} The project did not reach the goal.

{{As of|2024|05}}, no open-source ASIC had been produced.

===Commercial implementations===
Several commercial organizations have developed derivatives of the OpenRISC 1000 architecture, including the ORC32-1208 from ORSoC and the BA12, BA14, and BA22 from Beyond Semiconductor. Dynalith Systems provide the iNCITE [[FPGA prototyping]] board, which can run both the OpenRISC 1000 and BA12. [[Flextronics]] (Flex) and [[Jennic Limited]] manufactured the OpenRISC as part of an [[application-specific integrated circuit]] (ASIC). Samsung uses the OpenRISC 1000 in their DTV system-on-chips (SDP83 B-Series, SDP92 C-Series, SDP1001/SDP1002 D-Series, SDP1103/SDP1106 E-Series).<ref>[http://opensource.samsung.com/ Samsung Open Source Release Center], follow the links → TV & VIDEO → TV → DTV → ETC → OR1200.zip</ref> Allwinner Technology are reported to use an OpenRISC core in their AR100 power controller, which forms part of the A31 ARM-based SoC.<ref>Linux-sunxi project community wiki page on the [http://linux-sunxi.org/AR100 AR100 controller]. Retrieved on 20 July 2013.</ref>

[[Cadence Design Systems]] have begun using OpenRISC as a reference architecture in documenting tool chain flows (for example the UVM reference flow, now contributed to [[Accellera]]).<ref>[http://www.uvmworld.org/uvm-reference-flow.php UVM Reference Flow] {{Webarchive|url=https://web.archive.org/web/20111126230020/http://www.uvmworld.org/uvm-reference-flow.php |date=2011-11-26 }}, Accellera website (undated).</ref>

[[TechEdSat]], the first [[NASA]] OpenRISC architecture based Linux computer launched in July 2012, and was deployed in October 2012 to the International Space Station with hardware provided, built, and tested by ÅAC Microtec and ÅAC Microtec North America.<ref>Post to the openrisc mailing lists at lists.openrisc.net on 8 April 2012 by Fredrick Bruhn, CEO of ÅAC Microtec</ref><ref>{{cite press release |author=<!--Staff writer(s); no by-line.--> |title=Swedish breakthrough in space on NASA satellite with electronics from ÅAC Microtec |url=http://www.aacmicrotec.com/index.php/component/content/article/1-news-in-english/111-swedish-breakthrough-in-space-on-nasa-satellite-with-electronics-from-aac-microtec.html |website=ÅAC Microtec |date=2012-10-11 |access-date=2018-03-17 |archive-url=https://web.archive.org/web/20140118171835/http://aacmicrotec.com/index.php/component/content/article/1-news-in-english/111-swedish-breakthrough-in-space-on-nasa-satellite-with-electronics-from-aac-microtec.html |archive-date=2014-01-18 |url-status=dead }}</ref><ref>{{cite press release |author=<!--Staff writer(s); no by-line.--> |title=Svenskt genombrott i rymden på NASA-satellit med elektronik från ÅAC Microtec |trans-title=Swedish breakthrough in space on NASA satellite with electronics from ÅAC Microtec |url=http://www.aacmicrotec.com/index.php/component/content/article/2-news-in-swedish/112-svenskt-genombrott-i-rymden-pa-nasa-satellit-med-elektronik-fran-aac-microtec.html |language=sv |date=2012-10-11 |via=[[Mynewsdesk]] |access-date=2018-03-16}}{{dead link|date=August 2020|bot=medic}}{{cbignore|bot=medic}} [http://www.mynewsdesk.com/se/uppsala_innovation_centre_ab/pressreleases/svenskt-genombrott-i-rymden-paa-nasa-satellit-med-elektronik-fraan-aaac-microtec-803754 Alt URL]</ref>

===Academic and non-commercial use===
Being open source, OpenRISC has proved popular in academic and hobbyist circles. For example, Stefan Wallentowitz<ref>{{Cite web |url=http://www.lis.ei.tum.de/?id=wallentowitz |title=Dipl.-Ing. Dipl.-Wirt.-Ing. Stefan Wallentowitz |date=2009–2013 |archive-url=https://web.archive.org/web/20130413065707/http://www.lis.ei.tum.de/?id=wallentowitz |archive-date=2013-04-13}}</ref> and his team at the Institute for Integrated Systems at the [[Technische Universität München]] have used OpenRISC in research into [[multi-core processor]] architectures.<ref>{{cite web |title=Multicore Architecture and Programming Model Co-Optimization (MAPCO) |type=Research poster at the Sixth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems (ACACES), 11-17 July 2010 |place=Terrassa (Barcelona), Spain |last1=Wallentowitz |first1=Stefan |last2=Wild |first2=Thomas |last3=Herkersdorf |first3=Andreas |access-date=2018-10-29 |url-status=dead |url=http://www.lis.ei.tum.de/fileadmin/w00bdv/www/MAPCO/ACACES2010_Poster.pdf |archive-url=https://web.archive.org/web/20130210103934/http://www.lis.ei.tum.de/fileadmin/w00bdv/www/MAPCO/ACACES2010_Poster.pdf |archive-date=10 February 2013 }}</ref>
The ''Open Source Hardware User Group'' ([[OSHUG]]) in the UK has on two occasions<ref>[http://oshug.org/event/9 Chips (Programmable Logic, Computer Conservation with FPGAs, OpenCores & OpenRISC 1000)]. OSHUG meeting #9, Skills Matter, 116-120 Goswell Road, London, 21 April 2011.</ref><ref>[http://oshug.org/event/17 Practical System-on-Chip (Program your own open source FPGA SoC)]. OSHUG meeting #17, Centre for Creative Collaboration, 16 Acton Street, London, 29 March 2012.</ref> run sessions on OpenRISC, while hobbyist Sven-Åke Andersson has written a comprehensive blog on OpenRISC for beginners,<ref>[http://www.rte.se/blog/blogg-modesty-corex/openrisc-1200-soft-processor OpenRISC 1200 soft processor] {{Webarchive|url=https://web.archive.org/web/20120513023117/http://www.rte.se/blog/blogg-modesty-corex/openrisc-1200-soft-processor |date=2012-05-13 }}. Blog post by Sven-Åke Andersson, 2 March 2012.</ref> which attracted the interest of ''Electronic Engineering Times'' ([[EE Times]]).<ref>{{cite news |last=Maxfield |first=Clive |date=2012-05-03 |title=Comparing four 32-bit soft processor cores |url=https://www.eetimes.com/author.asp?section_id=14&doc_id=1286116 |work=Electronic Engineering Times ([[EE Times]]) |publisher=AspenCore Media |location=[[San Francisco]], California, United States |access-date=2019-03-21}}</ref>
Sebastian Macke has implemented jor1k, an OpenRISC 1000 emulator in [[JavaScript]], running [[Linux]] with [[X Window System]] and [[Wayland (display server protocol)|Wayland]] support.<ref>[https://www.phoronix.com/scan.php?page=news_item&px=MTQ4NDI OpenRISC Emulator in JavaScript Can Run Wayland]</ref>

==Toolchain support==
The OpenRISC community have ported the [[GNU toolchain]] to OpenRISC to support development in the [[programming language]]s [[C (programming language)|C]] and [[C++]]. Using this toolchain the [[newlib]], [[uClibc]], [[musl]] (as of release 1.1.4), and [[glibc]] libraries have been ported to the processor. Dynalith provides OpenIDEA, a graphical [[integrated development environment]] (IDE) based on this toolchain. A project to port [[LLVM]] to the OpenRISC 1000 architecture began in early 2012.<ref>{{cite web |url=https://github.com/openrisc/llvm-or1k |title=llvm-or1k |author=<!--Unstated--> |date=2018-04-06 |website=GitHub |access-date=2019-03-21}}</ref>

[[GNU Compiler Collection|GCC]] 9 released with OpenRISC support.<ref>{{cite web |url=https://gcc.gnu.org/gcc-9/changes.html#or1k |title=GCC 9 changelog |publisher=GNU |access-date=15 June 2022}}</ref>

The OR1K project provides an [[instruction set simulator]], or1ksim. The flagship implementation, the OR1200, is a [[register-transfer level]] (RTL) model in Verilog HDL, from which a [[SystemC]]-based cycle-accurate model can be built in ORPSoC. A high speed model of the OpenRISC 1200 is also available through the Open Virtual Platforms (OVP) initiative (see [[OVPsim]]), set up by Imperas.

==Operating system support==

===Linux support===
The mainline [[Linux kernel]] gained support for OpenRISC in version 3.1.<ref>{{cite web |title=git.kernel.org - linux/kernel/git/torvalds/linux-2.6.git/tree - arch/openrisc/|url=https://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=arch/openrisc;hb=HEAD |archive-url=https://archive.today/20120708204051/http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=tree;f=arch/openrisc;hb=HEAD |url-status=dead|archive-date=2012-07-08 |publisher=git.kernel.org |access-date=2011-10-17}}</ref>
The implementation merged in this release is the 32-bit OpenRISC 1000 family (or1k).<ref>{{cite web |title=Linux 3.1 |url=http://kernelnewbies.org/Linux_3.1#head-37c60fa1253db74ce7d224718a71f5836bd5be09 |website=Kernel Newbies |access-date=2011-10-17}}</ref> Formerly OpenRISC 1000 architecture, it has been superseded by the mainline port.

===RTOS support===
Several [[real-time operating system]]s (RTOS) have been ported to OpenRISC, including [[NuttX]], [[RTEMS]], [[FreeRTOS]], and [[eCos]].

==QEMU support==
Since version 1.2, [[QEMU]] supports emulating OpenRISC platforms.<ref>[http://wiki.qemu.org/ChangeLog/1.2 QEMU Changelog 1.2]</ref>

==See also==
{{Portal|Free and open-source software}}
* [[Amber (processor core)]] – ARM-Compatible OpenCores Project
* [[Free and Open Source Silicon Foundation]]
* [[SuperH#J_Core|J Core]] – SuperH-Compatible OpenCores Project
* [[OpenRISC 1200]]
* [[OVPsim]], Open Virtual Platforms
* [[OpenSPARC]] – SPARC-Compatible OpenCores Project
* [[LEON]]
* [[LatticeMico32]]
* [[RISC-V]]

==References==
{{Reflist}}

==External links==
* {{Official website|openrisc.io}}
* [http://jolt.law.harvard.edu/articles/pdf/v25/25HarvJLTech131.pdf Open Source Semiconductor Core Licensing, 25 Harvard Journal of Law & Technology 131 (2011)] Article analyzing the law, technology and business of open source semiconductor cores
* [http://www.beyondsemi.com/ Beyond Semiconductor] commercial [[fabless semiconductor company]] founded by the developers of OpenRISC
* [https://web.archive.org/web/20070717073636/http://www.dynalith.com/ Dynalith Systems] company website.
* [http://www.imperas.com/ Imperas] company website.
* [https://www.flextronics.com/ Flex] company website
* [http://www.jennic.com/ Jennic] company website
* [http://www.eetimes.com/story/OEG20000228S0007 Eetimes article]
* [https://web.archive.org/web/20120513023117/http://www.rte.se/blog/blogg-modesty-corex/openrisc-1200-soft-processor OpenRISC tutorial]
* {{GitHub|s-macke/jor1k}}, OpenRISC 1000 emulator in JavaScript

{{RISC architectures}}
{{Soft microprocessors}}
{{Programmable logic}}

{{DEFAULTSORT:Openrisc}}
[[Category:Open microprocessors]]
[[Category:Embedded microprocessors]]
[[Category:Soft microprocessors]]