View source for PCI-X

{{Short description|Computer bus and expansion card standard}}
{{Distinguish|text=[[PCI Express]] (PCI-E or PCIe)}}
{{Redirect|PCIX|the PC Unix port|Interactive Systems Corporation#PC/IX}}
{{Infobox Computer Hardware Bus
|name=PCI-X
|fullname=PCI Local Bus
|image=File:ZRAID at PCI-X at FSC Primtrgy TX200 S2.JPG
|caption=PCI-X motherboard, with one card installed.
|invent-date={{Start date and age|1998}}
|invent-name=[[IBM]], [[Hewlett-Packard|HP]], and [[Compaq]]
|super-date=ratified 2003, superseded before 2005
|super-name=[[PCI Express]]
|width=64
|numdev=
|speed=Half-duplex<ref>{{Cite web|title=PCIe (Peripheral Component Interconnect Express) {{!}} On the Motherboard {{!}} Pearson IT Certification|url=https://www.pearsonitcertification.com/articles/article.aspx?p=2731934&seqNum=24|access-date=2020-09-25|website=www.pearsonitcertification.com}}</ref>
266–4266&nbsp;MB/s
|hotplug=Optional
|style=p
}}

'''PCI-X''', short for '''Peripheral Component Interconnect eXtended''', is a [[computer bus]] and [[expansion card]] standard that enhances the 32-bit [[Conventional PCI|PCI]] [[local bus]] for higher [[Bandwidth (computing)|bandwidth]] demanded mostly by [[Server (computing)|servers]] and [[workstations]]. It uses a modified protocol to support higher [[Clock rate|clock speed]]s (up to 133&nbsp;MHz), but is otherwise similar in electrical implementation. PCI-X 2.0 added speeds up to 533&nbsp;MHz,{{r|PCIX2.0|p=23}} with a reduction in electrical signal levels.

The slot is physically a 3.3&nbsp;V PCI slot, with the same size, location and pin assignments. The electrical specifications are compatible, but stricter. However, while most conventional PCI slots are the 85&nbsp;mm long 32-bit version, most PCI-X devices use the 130&nbsp;mm long 64-bit slot, to the point that 64-bit PCI connectors and PCI-X support are seen as synonymous.

PCI-X is specified for both [[32-bit computing|32-]] and [[64-bit computing|64-bit]] PCI connectors,{{r|PCIX1.0a|p=14}} and PCI-X 2.0 added a [[16-bit computing|16-bit]] variant for embedded applications.{{r|PCIX2.0|p=22}}

PCI-X has been replaced in modern designs by the similar-sounding [[PCI Express]] (PCIe),<ref name="Andrews2010">{{cite book|author=Jean Andrews|title=A+ Guide to Managing and Maintaining Your PC|url=https://archive.org/details/labmanualtoaccom07edandr|url-access=registration|year=2010|publisher=Cengage Learning|isbn=978-1-4354-9778-8|page=[https://archive.org/details/labmanualtoaccom07edandr/page/187 187]}}</ref> with a different physical connector and a different electrical design, having one or more [[Serial communication|serial]] lanes instead of a number of slower [[Parallel communication|parallel]] connections.

==History==

===Background and motivation===
[[File:dualportintelmtpro1000mtserveradapterspc.jpg|thumb|A Dual Port [[Gigabit Ethernet]] [[Network Card]] for single PCI-X slot to save on PCI-X slots and use the full potential of the PCI-X [[64-bit computing|64-bit]] bus.]]
[[File:LSI Logic MegaRAID SATA 300-8X SATA RAID controller.jpg|thumb|A 8 port [[SATA]] [[host bus adapter]] for PCI-X from [[Lsi logic]].]]
[[File:HP VISUALIZE fx10 Pro (A1299-6503) front.jpg|thumb|HP VISUALIZE fx10 Pro [[video card]] for PCI-X]]
In PCI, a transaction that cannot be completed immediately is postponed by either the target or the initiator issuing retry-cycles, during which no other agents can use the PCI bus. Since PCI lacks a split-response mechanism to permit the target to return data at a later time, the bus remains occupied by the target issuing retry-cycles until the read data is ready. In PCI-X, after the master issues the request, it disconnects from the PCI bus, allowing other agents to use the bus. The split-response containing the requested data is generated only when the target is ready to return all of the requested data. Split-responses increase bus efficiency by eliminating retry-cycles, during which no data can be transferred across the bus.

PCI also suffered from the relative scarcity of unique interrupt lines. With only 4 interrupt pins (INT A/B/C/D), systems with many PCI devices require multiple functions to share an interrupt line, complicating host-side interrupt-handling. PCI-X added [[Message Signaled Interrupts]], an interrupt system using writes to host-memory. In MSI-mode, the function's interrupt is not signaled by asserting an INTx line. Instead, the function performs a memory-write to a system-configured region in host-memory. Since the content and address are configured on a per-function basis, MSI-mode interrupts are dedicated instead of shared. A PCI-X system allows both MSI-mode interrupts and legacy INTx interrupts to be used simultaneously (though not by the same function).

The lack of registered I/Os limited PCI to a maximum frequency of 66&nbsp;MHz. PCI-X I/Os are registered to the PCI clock, usually through means of a PLL to actively control I/O delay the bus pins. The improvement in setup time allows an increase in frequency to 133&nbsp;MHz.

Some devices, most notably Gigabit Ethernet cards, SCSI controllers (Fibre Channel and Ultra320), and cluster interconnects could by themselves saturate the PCI bus's 133&nbsp;MB/s bandwidth. Ports using a bus speed doubled to 66&nbsp;MHz and a bus width doubled to 64&nbsp;bits (with the pin count increased to 184 from 124), in combination or not, have been implemented. These extensions were loosely supported as optional parts of the PCI&nbsp;2.x standards, but device compatibility beyond the basic 133&nbsp;MB/s continued to be difficult.

Developers eventually used the combined 64-bit and 66-MHz extension as a foundation, and, anticipating future needs, established 66-MHz and 133-MHz variants with a maximum bandwidth of 532&nbsp;MB/s and 1064&nbsp;MB/s respectively. The joint result was submitted as PCI-X to the [[PCI-SIG|PCI Special Interest Group]] ([[Special Interest Group]] of the [[Association for Computing Machinery]]). Subsequent approval made it an [[open standard]] adoptable by all computer developers. The PCI SIG controls technical support, training, and compliance testing for PCI-X. IBM, Intel, Microelectronics, and [[Mylex]] were to develop supporting chipsets. [[3Com]] and [[Adaptec]] were to develop compatible peripherals. To accelerate PCI-X adoption by the industry, Compaq offered PCI-X development tools at their Web site.

===PCI-X 1.0===
The PCI-X standard was developed jointly by [[IBM]], [[Hewlett-Packard|HP]], and [[Compaq]] and submitted for approval in 1998. It was an effort to codify proprietary [[Server (computing)|server]] extensions to the [[PCI local bus]] to address several shortcomings in PCI, and increase performance of high bandwidth devices, such as Gigabit Ethernet, [[Fibre Channel]], and [[SCSI|Ultra3 SCSI]] cards, and allow processors to be interconnected in [[Computer cluster|clusters]].

Intel gave only a qualified welcome to PCI-X, stressing that the next generation bus would have to be a "fundamentally new architecture".<ref>{{cite news |title=PCI-X Gang of Three challenges Intel with Future I/O |url=https://www.theregister.co.uk/1999/01/13/pcix_gang_of_three_challenges/ |date=1999-01-13 |first= John |last=Lettice |journal=The Register}}</ref> Without Intel's support, PCI-X failed to be adopted in PCs. According to Rick Merritt of the EE Times, "A falling-out between the PCI SIG and a key Intel interconnect designer who spearheaded development on the [[Accelerated Graphics Port]] caused Intel to pull out of the initial PCI-X effort".<ref>{{cite news |url=http://www.eetimes.com/document.asp?doc_id=1204479 |title=Servers gas up with 4-Gbyte/s PCI-X 2.0 spec |first=Rick |last=Merritt |date=2001-11-21 |journal=EE Times}}</ref> The PCI-X interface was however briefly adopted by Apple, for the first few generations of the [[Power Macintosh G5]].

The first PCI-X products were manufactured in 1998, such as the Adaptec AHA-3950U2B dual Ultra2 Wide SCSI controller, however at that point the PCI-X connector was merely referred to as "64-bit ready PCI" on packaging, hinting at future [[forward compatibility]]. Actual PCI-X branding only became standard later, likely coinciding with widespread availability of PCI-X equipped motherboards. When more details of PCI Express were released in August 2001, PCI SIG chairman Roger Tipley expressed his belief that "PCI-X is going to be in servers forever because it serves a certain level of functionality, and it may not be compelling to switch to 3GIO [PCI Express] for that functionality. We learned that from not being able to get rid of ISA. ISA hung around because of all of these systems that weren't high-volume parts." Tipley also announced that (at the time) the PCI SIG was planning to fold PCI Express and PCI-X 2.0 into a single work tentatively called PCI 3.0,<ref>Jerry Ascierto (8/30/2001) "[http://www.eetimes.com/document.asp?doc_id=1228264 Intel details next-generation I/O spec]", ''EE Times''</ref> but that name was eventually used for a relatively minor revision of conventional PCI.<ref>{{Cite web |url=http://www.pcisig.com/news_room/faqs/faq_pci30/pci30_faq.pdf |title=Archived copy |access-date=2013-12-16 |archive-date=2014-02-11 |archive-url=https://web.archive.org/web/20140211033021/http://www.pcisig.com/news_room/faqs/faq_pci30/pci30_faq.pdf |url-status=dead }}</ref>

===PCI-X 2.0===
In 2003, the PCI SIG ratified PCI-X 2.0. It adds 266-MHz and 533-MHz variants, yielding roughly 2,132&nbsp;MB/s and 4,266&nbsp;MB/s throughput, respectively. PCI-X 2.0 makes additional protocol revisions that are designed to help system reliability and add [[Error-correcting code]]s to the bus to avoid re-sends.<ref name="PCI-SIG">{{cite web|url=http://www.pcisig.com/news_room/faqs/faq_20/|title=PCI-SIG&nbsp;— FAQ&nbsp;— PCI-X 2.0|access-date=2008-02-17|archive-date=2008-02-15|archive-url=https://web.archive.org/web/20080215215940/http://www.pcisig.com/news_room/faqs/faq_20/|url-status=dead}}</ref> To deal with one of the most common complaints of the PCI-X form factor, the 184-pin connector, 16-bit ports were developed to allow PCI-X to be used in devices with tight space constraints. Similar to PCI-Express, PtP functions were added to allow for devices on the bus to talk to each other without burdening the [[Central processing unit|CPU]] or bus controller.

Despite the various theoretical advantages of PCI-X 2.0 and its backward compatibility with PCI-X and PCI devices, it has not been implemented on a large scale ({{as of|2008|lc=y}}). This lack of implementation primarily is because hardware vendors have chosen to integrate [[PCI Express]] instead.

[[IBM]] was one of the (few) vendors which provided PCI-X 2.0 (266&nbsp;MHz) support in their [[IBM AS/400|System i5]] Model 515, 520 and 525; IBM advertised these slots as suitable for [[10 Gigabit Ethernet]] adapters, which they also provided.<ref>{{cite web|url=http://www.redbooks.ibm.com/redpapers/pdfs/redp4011.pdf|quote="A third generation of PCI is now offered with the introduction of the 1.9&nbsp;GHz System i5 Models 515, 520, and 525. These models have a PCI-X DDR (PCI-X&nbsp;2.0) slot that runs at a maximum of 266&nbsp;MHz and supports only adapters that can run without an IOP. This slot is ideally suited for ultra-high bandwidth adapters such as the new 266&nbsp;MHz (DDR) #5721/#5722 10 Gb Ethernet adapters."|page=7|title=PCI, PCI-X, PCI-X DDR, and PCIe Placement Rules for IBM System i Models}}</ref> [[Hewlett-Packard|HP]] offered PCI-X 2.0 in some [[ProLiant]] and [[HPE Integrity Servers|Integrity]] servers and offered dual-port 4&nbsp;Gbit/s [[Fibre Channel]] adapters, also operating at 266&nbsp;MHz.<ref>{{Cite web |url=http://h18004.www1.hp.com/products/quickspecs/12481_na/12481_na.PDF |title=HP FC2243 Dual Channel 4Gb PCI-X 2.0 HBA |access-date=2013-12-16 |archive-date=2013-12-16 |archive-url=https://web.archive.org/web/20131216060927/http://h18004.www1.hp.com/products/quickspecs/12481_na/12481_na.PDF |url-status=dead }}</ref> [[AMD]] supported PCI-X 2.0 (266&nbsp;MHz) via its 8132 [[Hypertransport]] to PCI-X 2.0 tunnel chip.<ref>{{cite web|url=http://www.theinquirer.net/inquirer/news/1016137/amd-rolls-out-8132-pci-x-tunnel-part |archive-url=https://web.archive.org/web/20131216104651/http://www.theinquirer.net/inquirer/news/1016137/amd-rolls-out-8132-pci-x-tunnel-part |url-status=unfit |archive-date=December 16, 2013 |title=AMD rolls out 8132 PCI-X tunnel part |publisher=The Inquirer |date=2004-06-14 |access-date=2014-02-13}}</ref><ref name="MuellerSoper2006">{{cite book|author1=Scott M. Mueller|author2=Mark Edward Soper|author3=Barrie Sosinsky|title=Upgrading and Repairing Servers|url=https://books.google.com/books?id=9cLFf_1PBnkC&pg=PT366|year=2006|publisher=Pearson Education|isbn=978-0-13-279698-9|page=366}}</ref> [[ServerWorks]] was a vocal supporter of PCI-X 2.0<ref>{{cite web |url=http://serverworks.com/technology/pdf/PCI-X_2-0_WhitePaper.pdf |title=Archived copy |website=serverworks.com |access-date=12 January 2022 |archive-url=https://web.archive.org/web/20030718015904/http://serverworks.com/technology/pdf/PCI-X_2-0_WhitePaper.pdf |archive-date=18 July 2003 |url-status=dead}}</ref> (to the detriment of the first generation PCI Express) particularly through its chief [[Raju Vegesna]],<ref>[http://www.eetimes.com/document.asp?doc_id=1144859 ServerWorks chief spurns first-generation PCI Express]</ref> who was however fired soon thereafter for roadmap disagreements with the Broadcom leadership.<ref>[http://news.cnet.com/Broadcom-ousts-ServerWorks-chief/2100-1006_3-994245.html Broadcom ousts ServerWorks chief]</ref>

In 2003, [[Dell]] announced it would skip PCI-X&nbsp;2.0 in favor of more rapid adoption of PCI Express solutions.<ref>[http://news.cnet.com/2100-1010-992769.html PCI-X marks the spot for IBM, HP]</ref> As reported by [[PC Magazine]], Intel began to sideline PCI-X in their 2004 roadmap, in favor of PCI Express, arguing that the latter had substantial advantages in terms of system latency and power consumption, more dramatically stated as avoiding "the 1,000-pin apocalypse" for their [[Intel Xeon chipsets#NetBurst-based Xeon chipsets|Tumwater]] chipset.<ref>[https://web.archive.org/web/20160304075654/https://www.pcmag.com/article2/0,2817,909447,00.asp Intel Begins Making Its Case Against PCI-X]</ref>

==Technical description==
PCI-X revised the [[conventional PCI]] standard by doubling the maximum clock speed (from 66&nbsp;MHz to 133&nbsp;MHz)<ref name="PCI-SIG" /> and hence the amount of data exchanged between the computer processor and peripherals. Conventional PCI supports up to [[64-bit computing|64 bits]] at 66&nbsp;MHz (though anything above 32&nbsp;bits at 33&nbsp;MHz is seen only in high-end systems). The theoretical maximum amount of data exchanged between the processor and peripherals with PCI-X is 1.06&nbsp;GB/s, compared to 133&nbsp;MB/s with standard PCI. PCI-X also improves the fault tolerance of PCI, allowing, for example, faulty cards to be reinitialized or taken offline.

PCI-X is backward compatible to PCI in the sense that the entire bus falls back to PCI if any card on the bus does not support PCI-X.

The two most fundamental changes are:
* The shortest time between a signal appearing on the PCI bus and a response to that signal occurring on the bus has been extended to 2 cycles, rather than 1. This allows much faster clock rates, but causes many protocol changes:
** The ability of the conventional PCI bus protocol to insert wait states on any cycle based on the IRDY# and TRDY# signals has been deleted; PCI-X only allows bursts to be interrupted at 128-byte boundaries.
** The initiator must deassert FRAME# ''two'' cycles before the end of the transaction.
** The initiator may not insert wait states. The target may, but only before any data is transferred, and wait states for writes are limited to multiples of 2 clock cycles.
** Likewise, the length of a burst is decided before it begins; it may not be halted on an arbitrary cycle using the FRAME# and STOP# signals.
** Subtractive decode DEVSEL# takes place two cycles after the "slow DEVSEL#" cycle rather than on the next cycle.
* After the address phase (and before any device has responded with DEVSEL#), there is an additional 1-cycle "attribute phase", during which 36 additional bits (both AD and C/BE# lines are used) of information about the operation are transmitted. These include 16&nbsp;bits of requester identification (PCI bus, device and function number), 12 bits of burst length, 5 bits of tag (for associating split transactions), and 3&nbsp;bits of additional status.

==Versions==
[[File:PCI Keying.svg|500px|thumb|3.3&nbsp;V and 5&nbsp;V keying of 64-bit PCI cards (both PCI and PCI-X). While most 64-bit PCI-X cards are universal and are backward compatible with common 32-bit 5&nbsp;V PCI slots, PCI-X slots are 3.3&nbsp;V and will not accept 5&nbsp;V-only PCI cards.]]

Essentially all PCI-X cards or slots have a 64-bit implementation and vary as follows:
* Cards
** 66&nbsp;MHz (added in Rev. 1.0)<ref name="PCI-SIG"/>
** 100&nbsp;MHz (works in 133&nbsp;MHz slots by forcing a downclock of the bus to 100&nbsp;MHz)<ref>{{cite web |url=http://www.it-enquirer.com/main/ite/more/pci_xpci_express/ |archive-url=https://web.archive.org/web/20050225092337/http://www.it-enquirer.com/main/ite/more/pci_xpci_express/ |archive-date=February 25, 2005 |title=PCI-X vs. PCI-Express |url-status=usurped |access-date=September 2, 2016 }}</ref>
** 133&nbsp;MHz (added in Rev. 1.0)<ref name="PCI-SIG" />
** 266&nbsp;MHz (added in Rev. 2.0)<ref name="PCI-SIG" />
** 533&nbsp;MHz (added in Rev. 2.0)<ref name="PCI-SIG" />
* Slots
** 66&nbsp;MHz (speed as 66&nbsp;MHz 64-bit PCI, can be found on older servers)
** 133&nbsp;MHz (most common)
** 266&nbsp;MHz (rare on x86, main bus on IBM [[IBM System p|pSeries]] from the era)
** 533&nbsp;MHz (rare)

==Mixing of 32-bit and 64-bit PCI cards in different width slots==
[[File:PCI-X in a 32-bit slot.jpg|thumb|64-bit PCI-X card partially inserted in 32-bit PCI slot, showing compatibility]]
Most 32-bit PCI cards will function properly in 64-bit PCI-X slots, but the bus speed will be limited to the clock frequency of the slowest card, an inherent limitation of PCI's shared bus topology. For example, when a PCI 2.3 66-MHz card is installed into a PCI-X bus capable of 133&nbsp;MHz, the entire bus backplane will be limited to 66&nbsp;MHz. To get around this limitation, many motherboards have multiple PCI/PCI-X buses, with one bus intended for use with high-speed PCI-X peripherals, and the other bus intended for general-purpose peripherals.

Many 64-bit PCI-X cards are designed to work in 32-bit mode if inserted in shorter 32-bit connectors, with some loss of speed.<ref>{{cite web
 |url          = http://docs.znyx.com/products/hardware/zx370.htm
 |title        = ZX370 Series
 |access-date  = July 13, 2012
 |author       = ZNYX Networks
 |date         = June 16, 2009
 |quote        = The ZX370 Series is a true 64-bit adapter, widening the network pipeline to achieve higher throughput, while offering backward compatibility with standard 32-bit PCI slots.
 |archive-url  = https://web.archive.org/web/20110502042329/http://docs.znyx.com/products/hardware/zx370.htm
 |archive-date = May 2, 2011
 |url-status   = dead
}}</ref><ref>{{cite web
| url          = http://docs.znyx.com/products/pdf/ZX370_Datasheet_02_web.pdf
| title        = ZX370 Series Multi-Channel PCI Fast Ethernet Adapter
| access-date  = July 13, 2012
| author       = ZNYX Networks
| quote        = Backward compatible with 32 bit, 33 MHz PCI slots
| archive-url  = https://web.archive.org/web/20130720174917/http://docs.znyx.com/products/pdf/ZX370_Datasheet_02_web.pdf
| archive-date = July 20, 2013
| url-status   = dead
}}</ref> An example of this is the Adaptec 29160 64-bit [[SCSI]] interface card.<ref>{{cite web
| url         = http://www.adaptec.com/en-us/support/scsi/u160/asc-29160/_docs/29160_users_reference_pdf.htm?nc=/en-us/support/scsi/u160/asc-29160/_docs/29160_users_reference_pdf.htm
| title       = Adaptec SCSI Card 29160 Ultra160 SCSI Controller User's Reference
| access-date = July 13, 2012
| author      = Adaptec
|date=January 2000
| format      = PDF
| page        = 1
| quote       = Although the Adaptec SCSI Card 29160 is a 64-bit PCI card, it also works in a 32-bit PCI slot. When installed in a 32-bit PCI slot, the card automatically runs in the slower 32-bit mode.
}}</ref> However some 64-bit PCI-X cards do not work in standard 32-bit PCI slots.<ref>{{cite web
 |url=http://www.lacie.com/support/support_manifest.htm?id=10525&article=1164
 |title=LaCie support: Identify a variety of PCI slots
 |access-date=July 13, 2012
 |author=LaCie
 |url-status=dead
 |archive-url=https://web.archive.org/web/20120404080344/http://www.lacie.com/support/support_manifest.htm?id=10525&article=1164
 |archive-date=April 4, 2012
}}</ref>{{Unreliable source?|date=July 2012}} Even if it would work, installing a 64-bit PCI-X card in a 32-bit slot will leave the 64-bit portion of the card edge connector not connected and overhanging, which requires that there be no motherboard components positioned so as to mechanically obstruct the overhanging portion of the card edge connector.

==Comparison with PCI-Express==
[[File:MOTU PCIX-424 7825.jpg|thumb|A MOTU PCIX-424 audio interface card, which was also released in standard PCI and PCIe variations.]]
PCI-X should not be confused with the similar-sounding but incompatible [[PCI Express]], commonly abbreviated as PCI-E or PCIe. While both are high-speed computer buses for internal peripherals, they differ in looks and technology. PCI-X is a 64-bit parallel interface, backward compatible with 32-bit PCI. PCIe is a serial point-to-point connection with a different physical interface that was designed to supersede both PCI and PCI-X along with a variety of other contemporary interfaces such as [[Accelerated_Graphics_Port|AGP]] (Accelerated Graphics Port) and [[Communications_and_networking_riser|CNR]].

PCI-X and standard PCI buses may run on a PCIe bridge, similar to the way [[Industry Standard Architecture|ISA]] buses ran on standard PCI buses in some computers. PCIe also matches PCI-X and even PCI-X 2.0 in maximum bandwidth. PCIe 1.0 x1 offers 250&nbsp;MB/s in each direction (lane), and up to 16 lanes (x16) are currently supported each direction, in [[Full-duplex#Full-duplex|full-duplex]], giving for PCIe 1.0 a maximum of 4&nbsp;GB/s bandwidth in each direction. PCI-X&nbsp;2.0 offers (at its maximum 64-bit 533-MHz variant) a maximum bandwidth of 4,266&nbsp;MB/s (≈4.3&nbsp;GB/s), although only in [[half-duplex]].

PCI-X has technological and economical disadvantages compared to PCI Express. The 64-bit parallel interface requires difficult trace routing, because, as with all parallel interfaces, the signals from the bus must arrive simultaneously or within a very short window, and noise from adjacent slots may cause interference. The serial interface of PCIe suffers fewer such problems and therefore does not require such complex and expensive designs. PCI-X buses, like standard PCI, are [[half-duplex]] bidirectional, whereas PCIe buses are [[full-duplex]] bidirectional. PCI-X buses run only as fast as the slowest device, whereas PCIe devices are able to independently negotiate the bus speed. Also, PCI-X slots are longer than PCIe 1x through PCIe 16x, which makes it impossible to make short cards for PCI-X. PCI-X slots take quite a bit of space on motherboards, which can be a problem for [[ATX]] and smaller [[Motherboard form factor|form factors]].

==See also==
{{Portal|Electronics}}
* [[PCI configuration space]]
* [[List of interface bit rates]]

==References==
{{Reflist|30em|refs=
<ref name=PCIX1.0a>{{Citation |mode=cs1 |title=PCI-X Addendum to the PCI Local Bus Specification |version=Revision 1.0a |date=24 July 2000 |publisher=PCI Special Interest Group}}
</ref>
<ref name=PCIX2.0>{{Citation |mode=cs1 |title=PCI-X Protocol Addendum to the PCI Local Bus Specification |version=Revision 2.0 |date=29 July 2002 |publisher=PCI Special Interest Group}}
</ref>}}

==Further reading==
<!-- WARNING: DO NOT POST LINKS TO ANY PIRATED PCI SPECS. See DMCA take-down notice at [[wmf:File:DMCA_PCI.pdf]] -->
* ''PCI Bus Demystified''; 2nd Ed; Doug Abbott; 250 pages; 2004; {{ISBN|978-0-7506-7739-4}}.
* ''PCI-X System Architecture''; 1st Ed; Tom Shanley; 752 pages; 2000; {{ISBN|978-0-201-72682-4}}.
* ''PCI & PCI-X Hardware and Software Architecture & Design''; 5th Ed; Ed Solari; 1140 pages; 2001; {{ISBN|978-0-929392-63-9}}.
* Ray Weiss, (6/9/2000) "[http://www.eetimes.com/document.asp?doc_id=1255127 PCI-X Exposed]", ''[[EE Times]]''

==External links==
<!-- WARNING: DO NOT POST LINKS TO ANY PIRATED PCI SPECS. See DMCA take-down notice at [[wmf:File:DMCA_PCI.pdf]] -->
* [http://hsi.web.cern.ch/HSI/s-link/devices/s32pci64/slottypes.html How to recognise a 3.3 Volt PCI slot?]

{{Computer-bus}}

{{DEFAULTSORT:Pci-X}}
[[Category:Peripheral Component Interconnect]]
[[Category:Motherboard expansion slot]]
[[Category:Open standards]]