View source for PDP-10

{{Short description|36-bit computer by Digital (1966–1983)}}
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{{Use mdy dates|date=November 2019}}
{{Infobox information appliance
| name         = PDP-10
| title        =
| aka          = DECsystem-10
| logo         = decsystem.svg
| logo_size    = 250px
| logo caption =
| image        = DEC PDP-10 (from ca. 1970 named decsystem-10) mainframe computer system, 1970s (edited, white background).jpg
| image_size   = 250px
| caption      = Working DEC KI-10 System formerly at Living Computers: Museum + Labs
| developer    = [[Digital Equipment Corporation]]
| manufacturer =
| family       = [[Programmed Data Processor]]
| type         = [[Mainframe computer]] 
| generation   =
| releasedate  = {{Start date and age|1966}}
| lifespan     =
| price        =
| discontinued = {{End date and age|1983}}
| unitssold    =
| unitsshipped =
| media        =
| os           = [[Incompatible Timesharing System|ITS]], [[TOPS-10]], [[TENEX (operating system)|TENEX]], [[WAITS]], [[CompuServe]] time-sharing system
| power        =
| soc          =
| cpu          =
| memory       =
| storage      =
| memory card  =
| display      =
| graphics     =
| sound        =
| input        =
| controllers  =
| camera       =
| touchpad     =
| connectivity =
| platform     = [[Programmed Data Processor|PDP]] 36-bit
| service      =
| dimensions   =
| topgame      =
| compatibility=
| predecessor  = [[PDP-6]]
| successor    =
| related      = [[DECSYSTEM-20]]
| website      =
}}
[[File:Arpanet logical map, march 1977 PDP-10.png|thumb|right|300px|PDP-10 systems on the ARPANET highlighted in yellow]]
[[Digital Equipment Corporation]] (DEC)'s '''PDP-10''', later marketed as the '''DECsystem-10''', is a [[mainframe computer]] family<ref>{{harvnb|Ceruzzi|2003|p=208}}: "It was large&mdash;even DEC's own literature called [the PDP-10] a mainframe."</ref> manufactured from 1966,<ref>{{harvnb|Ceruzzi|2003|p=139}}</ref> delivered from December 1967,<ref name="computerworld19671213">{{ cite magazine | url=https://archive.org/details/sim_computerworld_1967-12-13_1_18/page/7/mode/1up | title=Bet They Still Have To Pay For It! | magazine=Computerworld | date=13 December 1967 | access-date=23 September 2025 | pages=7 }}</ref> and discontinued in 1983.<ref>{{cite book |last=Winstanley |first=Graham |date=1991 |title=Artificial intelligence in engineering |location=West Sussex, England |publisher=Wiley, Chichester |page=391 |isbn=9780471926030 |quote=PDP-10...was discontinued in 1983}}</ref><ref>{{cite web
|title=PDP-10 was discontinued in 1983, but PDP-11 wasn't discontinued until 1997 |url=https://news.ycombinator.com/item?id=13469933 |quote=... with third-parties continuing to sell parts, so it's really not that ...}}</ref><ref>{{cite web  |title=Definitions for pdp-10 |url=https://www.definitions.net/definition/pdp-10 |website=definitions.net |quote=The PDP-10 was a mainframe computer family manufactured ... the cancellation of the PDP-10 line was announced in 1983.}}</ref> 1970s models and beyond were marketed under the DECsystem-10 name, especially as the [[TOPS-10]] operating system became widely used.{{efn|The TOPS-10 name was announced 1970.}}

The PDP-10's architecture is almost identical to that of DEC's earlier [[PDP-6]], sharing the same [[36-bit]] [[Word (computer architecture)|word]] length and slightly extending the instruction set. The main difference was a greatly improved hardware implementation. Some aspects of the [[instruction set]] are unusual, most notably the ''[[byte]]'' instructions, which operate on [[bit field]]s of any size from 1 to 36 bits inclusive, according to the general definition of a byte as ''a contiguous sequence of a fixed number of bits''.

The PDP-10 was found in many university computing facilities and research labs during the 1970s, the most notable being [[Harvard University]]'s Aiken Computation Laboratory, [[Massachusetts Institute of Technology|MIT]]'s [[MIT Computer Science and Artificial Intelligence Laboratory#LCS and AI Lab|AI Lab]] and [[MIT Computer Science and Artificial Intelligence Laboratory#Project MAC|Project MAC]], [[Stanford University|Stanford]]'s [[Stanford AI Lab|SAIL]], [[Computer Center Corporation]] (CCC), [[ETH]] (ZIR), and [[Carnegie Mellon University]]. Its main [[operating system]]s, TOPS-10 and [[TENEX (operating system)|TENEX]], were used to build out the early [[ARPANET]]. For these reasons, the PDP-10 looms large in early [[Hacker culture|hacker folklore]].

Projects to extend the PDP-10 line were eclipsed by the success of DEC's unrelated [[VAX]] [[superminicomputer]], and the cancellation of the PDP-10 line was announced in 1983. According to reports, DEC sold "about 1500 DECsystem-10s by the end of 1980".<ref name=Foonly.MMSmag1980>{{cite magazine |magazine=Mini-Micro Systems |title=Foonly challenges DEC patents with emulator |author=Larry Lettieri |date=November 1980 |pages=15, 17}}</ref>

==Models and technical evolution==
[[File:KA10 mod end.jpg|thumb|[[Flip-Chip module]] from a DEC KA10, containing 9 transistors, 1971]]
[[File:DEC-10 Memory Bus Terminator H866 top view.jpg|thumb|Quick-latch memory-bus terminator, used on KI10, 1973]]
[[File:KL10-backplane.jpg|thumb|KL10 wire-wrap CPU backplane]]

The original PDP-10 processor is the KA10, introduced in 1968.<ref>{{Cite book |url=http://www.bitsavers.org/www.computer.museum.uq.edu.au/pdf/DEC-10-HMAA-D%20PDP-10%20KA10%20Central%20Processor%20Maintenance%20Manual%20Volume%20I.pdf |title=PDP-10 KA10 Central Processor Maintenance Manual Volume I |id=DEC-10-HMAA-D |date=December 1968}}</ref> It uses discrete [[transistor]]s packaged in DEC's [[Flip-Chip module|Flip-Chip]] technology, with backplanes [[wire-wrap]]ped via a semi-automated manufacturing process. Its [[Magnetic-core memory|cycle time]] is 1&nbsp;μs and its add time 2.1&nbsp;μs.<ref>Digital Equipment Corporation, ''The digital [[Small Computer Handbook|small computer handbook]]'', p.&nbsp;376.</ref> In 1973, the KA10 was replaced by the KI10, which uses [[transistor–transistor logic]] (TTL) [[Integrated circuit#SSI|SSI]]. This was joined in 1975 by the faster KL10 which is built from [[emitter-coupled logic]] (ECL), [[microprogram]]med, and has [[CPU cache|cache]] memory. The KL10's performance was about 1&nbsp;megaflops using 36-bit floating-point numbers on matrix row reduction. It was slightly faster than the newer [[VAX-11/750]], although more limited in memory.

A smaller, less expensive model, the KS10, was introduced in 1978, using TTL and [[AMD Am2900|Am2901]] [[bit-slice]] components and including the [[PDP-11]] [[Unibus]] to connect peripherals. The KS10 was marketed as the DECSYSTEM-2020, part of the DECSYSTEM-20 range; it was DEC's entry in the [[Distributed computing|distributed processing]] arena, and it was introduced as "the world's lowest cost mainframe computer system".<ref>{{Cite web |url=http://gordonbell.azurewebsites.net/digital/timeline/1978-2.htm |title=DECSYSTEM-2020 |work=DIGITAL Computing Timeline |date=21 April 1998}}</ref>

===KA10===
The KA10 has a maximum main memory capacity (both virtual and physical) of 256&nbsp;[[kiloword]]s (equivalent to 1152&nbsp;[[kilobyte]]s); the minimum main memory required is 16&nbsp;kilowords. As supplied by DEC, it did not include [[paging]] hardware; [[memory management]] consists of two sets of protection and relocation registers, called ''[[base and bounds]]'' registers. This allows each half of a user's [[address space]] to be limited to a set section of [[main memory]], designated by the base physical address and size. This allows the model of separate read-only shareable code segment (normally the high segment) and [[read-write]] data/[[Stack (data structure)|stack]] segment (normally the low segment) used by [[TOPS-10]] and later adopted by [[Unix]]. Some KA10 machines, first at MIT, and later at [[BBN Technologies|Bolt, Beranek and Newman]] (BBN), were modified to add [[virtual memory]]<ref>{{cite web |url=http://bitsavers.org/pdf/bbn/pager/Technical_Details_of_the_BBN_Pager_Model_701_197007.pdf |title=Technical Details of the BBN Pager Model 701 |first1=Theodore R. |last1=Strollo |first2=Jerry D. |last2=Burchflel |first3=Raymond S. |last3=Tomlinson |author3-link=Ray Tomlinson |date=July 22, 1970 |publisher=[[BBN Technologies|Bolt, Beranek and Newman]]}}</ref><ref>{{cite web |title=A Virtual Memory System for the PDP-10 KA10 Processor |url=https://apps.dtic.mil/sti/citations/ADA028987 |last=McNamee |first=L. P. |date=1976}}</ref> and support for [[demand paging]],<ref>{{cite journal
|title=TENEX, a Paged Time Sharing System for the PDP-10
|journal=[[Communications of the ACM]]
|volume=15 |issue=3
|url=https://cseweb.ucsd.edu//classes/wi19/cse221-b/papers/bobrow72.pdf
|citeseerx=10.1.1.509.1454
|last1=Bobrow |first1=Daniel G. |author1-link=Daniel Bobrow
|last2=Burchfiel |first2=Jerry D.
|last3=Murphy |first3=Daniel L. |author3-link=Daniel Murphy (computer scientist)
|last4=Tomlinson |first4=Raymond S. |author4-link=Ray Tomlinson
|date=March 1972 
|pages=135–143
|doi=10.1145/361268.361271
|s2cid=52848167
|quote=PDP-10 processor augmented by special paging hardware}}</ref><ref>{{cite web
|date=June 1, 1982
|title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual
|url=http://pdp10.nocrew.org/docs/ad-h391a-t1.pdf
|quote=DECsystem-10&nbsp;... dynamic paging and working set management}}</ref> and more physical memory.

The KA10 weighs about {{convert|1920|lb|kg}}.<ref>{{cite book |title=PDP-10 Installation Manual |url=http://www.bitsavers.org/pdf/dec/pdp10/KA10/PDP-10_InstallationMan.pdf |page=5 |publisher=Digital Equipment Corporation}}</ref>

The 10/50 was the top-of-the-line uniprocessor KA machine<ref name=JSYS104>{{cite web |url=http://tenex.opost.com/hbook.html |title=Origins and Development of TOPS-20 |last=Murphy |first=Dan |date=1989}}</ref> at the time when the ''PA1050'' software package was introduced. Two other KA10 models were the uniprocessor 10/40, and the dual-processor 10/55.<ref>{{cite web  |title=PDP-10 models |date=June 30, 2001 |url=http://www.inwap.com/pdp10/models.txt |quote=PDP 1055 Dual processor (1050) system ...  early DEC-10 monitors}}</ref>{{efn|Also marketed as 1040, 1050, 1055, as per the KI/KL models as 1060, 1070, etc.}}

===KI10===
The KI10 introduced support for paged memory management and for a larger physical address space of 4&nbsp;[[Word (data type)|megawords]]. KI10 models include 1060, 1070 and 1077, the latter incorporating two CPUs.

===KL10===
[[File:PDP-10 1090.jpg|thumb|KL10-DA 1090 [[CPU]] and 6 memory modules]]
The original KL10 PDP-10 (also marketed as DECsystem-10) models (1080, 1088, etc.) use the original PDP-10 memory bus, with external memory modules. Module in this context meant a cabinet, dimensions roughly {{nobr|30 in × 75 in × 30 in}} {{nobr|(W × H × D).}} with a capacity of 32 to 256&nbsp;kWords of [[magnetic-core memory]]. The processors used in the [[DECSYSTEM-20]] (2040, 2050, 2060, 2065), commonly but incorrectly called "KL20", use internal memory, mounted in the same cabinet as the [[Central processing unit|CPU]]. The 10xx models also have different packaging; they come in the original tall PDP-10 cabinets, rather than the short ones used later on for the DECSYSTEM-20. The differences between the 10xx and 20xx models were primarily which operating system they ran, either TOPS-10 or [[TOPS-20]]. Apart from that, differences are more cosmetic than real; some 10xx systems have "20-style" internal memory and I/O, and some 20xx systems have "10-style" external memory and an I/O bus. In particular, all ARPAnet TOPS-20 systems had an I/O bus because the AN20 [[Interface Message Processor|IMP]] interface was an I/O bus device. Both could run either TOPS-10 or TOPS-20 microcode and thus the corresponding operating system.

====Model B====
The later Model B version of the 2060 processors removes the 256&nbsp;[[binary prefix|kilo]][[Word (data type)|word]] limit on the virtual address space by supporting up to 32 "sections" of up to 256&nbsp;kilowords each, along with substantial changes to the instruction set. The two versions are effectively different CPUs. The first operating system that takes advantage of the Model&nbsp;B's capabilities is TOPS-20 release&nbsp;3, and user mode extended addressing is offered in TOPS-20 release&nbsp;4. TOPS-20 versions after release&nbsp;4.1 only run on a Model&nbsp;B.

TOPS-10 versions 7.02 and 7.03 also use extended addressing when run on a 1090 (or 1091) Model&nbsp;B processor running TOPS-20 microcode.

====MCA25====
The final upgrade to the KL10 was the MCA25 upgrade of a 2060 to 2065 (or a 1091 to 1095), which gave some performance increases for programs running in multiple sections.

====Massbus====
The I/O architecture of the 20xx series KL machines is based on a DEC bus design called the [[Massbus]]. While many attributed the success of the PDP-11 to DEC's decision to make the PDP-11 Unibus an open architecture, DEC reverted to prior philosophy with the KL, making Massbus both unique and proprietary. Consequently, there were no aftermarket peripheral manufacturers who made devices for the Massbus, and DEC chose to price their own Massbus devices, notably the RP06 disk drive, at a substantial premium above comparable IBM-compatible devices. [[CompuServe]] for one, designed its own alternative disk controller that could operate on the Massbus, but connect to IBM style 3330 disk subsystems.

====Front-end processors====
[[File:KL10-front-end.jpg|thumb|KL10 frontend PDP-11/40]]
The KL class machines have a PDP-11/40 [[front-end processor]] for system start-up and monitoring. The PDP-11 is booted from a dual-ported RP06 disk drive (or alternatively from an 8" [[floppy disk]] drive or [[DECtape]]), and then commands can be given to the PDP-11 to start the main processor, which is typically booted from the same RP06 disk drive as the PDP-11. The PDP-11 performs watchdog functions once the main processor is running.

Communication with IBM mainframes, including [[Remote job entry|Remote Job Entry]] (RJE), was accomplished via a DN61 or DN-64 front-end processor, using a PDP-11/40 or PDP-11/34a.<ref>{{Cite web |url=http://www.inwap.com/pdp10/usenet/decnet |title=USENET alt.sys.pdp10 postings about PDP-10 front end processors}}</ref><ref>{{cite web |url=http://pdp-10.trailing-edge.com/BB-J724A-SM_1980/01/documentation/dn60m.man.html |title=DN60 Maintenance Manual |id=JBS-77-001-02-U |date=October 31, 1978 |publisher=Digital Equipment Corporation}}</ref>

===KS10===
[[File:KS10-open.jpg|thumb|KS10]]
The KS10 is a lower-cost PDP-10 built using [[AMD Am2900|AMD 2901]] [[bit-slicing|bit-slice]] chips, with an [[Intel 8080]]A microprocessor as a control processor.<ref>{{cite book |url=http://www.bitsavers.org/pdf/dec/pdp10/KS10/EK-OKS10-TM-002_tech_Sep79.pdf |title=KS10-Based DECSYSTEM-2020 Technical Manual |id=EK-0KS10-TM-002 |date=September 1979 |edition=Second |publisher=Digital Equipment Corporation}}</ref> The KS10 design was crippled to be a Model&nbsp;A, even though most of the necessary data paths needed to support the Model&nbsp;B architecture are present. This was no doubt intended to [[market segmentation|segment the market]], but it greatly shortened the KS10's product life.

The KS system uses a similar boot procedure to the KL10. The 8080 control processor loads the microcode from an RM03, RM80, or RP06 disk or magnetic tape and then starts the main processor. The 8080 switches modes after the operating system boots and controls the console and remote diagnostic serial ports.

===Magnetic tape drives===
Two models of [[tape drive]]s were supported by the TM10 Magnetic Tape Control subsystem:
* TU20 Magnetic Tape Transport – 45 ips (inches per second)
* TU30 Magnetic Tape Transport – 75 ips (inches per second)
* TU45 Magnetic Tape Transport – 75 ips (inches per second)
A mix of up to eight of these could be supported, using [[IBM 7-track|7-track]] or [[9-track tape|9-track]] devices. The TU20 and TU30 each came in A (9-track) and B (7-track) versions, and all of the aforementioned tape drives could read/write from/to 200&nbsp;[[Bits per inch|BPI]], 556&nbsp;BPI and 800&nbsp;BPI IBM-compatible tapes.

The TM10 Magtape controller was available in two submodels:
* TM10A did cycle-stealing to/from PDP-10 memory using the KA10 Arithmetic Processor
* TM10B accessed PDP-10 memory using a DF10 Data Channel, without "cycle stealing" from the KA10 Arithmetic Processor<ref name=HW10.KA10>{{cite book |url=http://bitsavers.trailing-edge.com/pdf/dec/pdp10/KA10/DEC_10-HAAB-D_SitePrep_May70.pdf |title=PDP-10 Site Preparation Guide |publisher=Digital Equipment Corporation |date=May 1970}}</ref>{{rp|49}}

==Instruction set architecture==
From the first PDP-6s to the KL-10 and KS-10, the user-mode [[instruction set architecture]] is largely the same. This section covers that architecture.  The only major change to the architecture is the addition of multi-section extended addressing in the KL-10; extended addressing, which changes the process of generating the effective address of an instruction, is briefly discussed at the end. Generally, the system has 36-bit words and instructions, and 18-bit addresses.

=== Registers ===
{| class="infobox" style="font-size:88%;width:36em;"
|-
|+ DEC PDP-10 registers
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:120px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:120px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>3</sup><sub>5</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- 
|colspan="7" | '''General registers'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="6"| <div style="display:inline-block; width:12px">&nbsp;</div> AC0
| style="background:white; color:black;"| '''R'''egister 0
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC1
| style="background:white; color:black;"| '''R'''egister 1
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC2
| style="background:white; color:black;"| '''R'''egister 2
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC3
| style="background:white; color:black;"| '''R'''egister 3
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC4
| style="background:white; color:black;"| '''R'''egister 4
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC5
| style="background:white; color:black;"| '''R'''egister 5
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC6
| style="background:white; color:black;"| '''R'''egister 6
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC7
| style="background:white; color:black;"| '''R'''egister 7
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC10
| style="background:white; color:black;"| '''R'''egister 8
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC11
| style="background:white; color:black;"| '''R'''egister 9
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC12
| style="background:white; color:black;"| '''R'''egister 10
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC13
| style="background:white; color:black;"| '''R'''egister 11
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC14
| style="background:white; color:black;"| '''R'''egister 12
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC15
| style="background:white; color:black;"| '''R'''egister 13
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC16
| style="background:white; color:black;"| '''R'''egister 14
|- style="background:silver;color:black"
| style="text-align:right" colspan="3"| &nbsp;
| style="text-align:left;" colspan="3"| AC17
| style="background:white; color:black;"| '''R'''egister 15
|- 
|colspan="7" | '''Program counter and status flags'''
|- style="background:silver;color:black"
| style="text-align:left;" colspan="2"| Program Flags
| style="text-align:right;"| '''00000'''
| style="text-align:center" colspan="3"| PC
| style="background:white; color:black;"| '''P'''rogram '''C'''ounter
|} 
Note that the bit numbering order is different from some other DEC processors, and many newer processors.
|}

There are 16 general-purpose, 36-bit registers.  The right half of these registers (other than register 0) may be used for indexing. A few instructions operate on pairs of registers. The "PC Word" register is split in half; the right 18 bits contains the [[program counter]] and the left 13 bits contains the [[status register|processor status flag]]s, with five zeros between the two sections. The condition register bits, which record the results of arithmetic operations (''e.g.'' overflow), can be accessed by only a few instructions.

In the original KA-10 systems, these registers are simply the first 16 words of [[main memory]]. The "fast registers" hardware option implements them as registers in the CPU, still addressable as the first 16 words of memory. Some software takes advantage of this by using the registers as an [[CPU cache|instruction cache]] by loading code into the registers and then jumping to the appropriate address; this is used, for example, in [[Maclisp]] to implement one version of the [[Garbage collection (computer science)|garbage collector]].<ref>{{cite web |url=http://www.paulgraham.com/thist.html|title=History of T|first=Olin|last=Shivers|access-date=October 25, 2019|quote=Maclisp on the -10 had used a mark&sweep GC (one version of which famously "ran in the register set," though that is another story)}}</ref> Later models all have registers in the CPU.

=== Supervisor mode ===
There are two operational modes, supervisor and user mode. Besides the difference in memory referencing described above, supervisor-mode programs can execute input/output operations.

Communication from user-mode to supervisor-mode is done through Unimplemented User Operations (UUOs): instructions which are not defined by the hardware, and are trapped by the supervisor. This mechanism is also used to emulate operations which may not have hardware implementations in cheaper models.

=== Data types ===
The major datatypes which are directly supported by the architecture are [[two's complement]] 36-bit integer arithmetic (including bitwise operations), 36-bit floating-point, and halfwords. Extended, 72-bit, floating point is supported through special instructions designed to be used in multi-instruction sequences. Byte pointers are supported by special instructions. A word structured as a "count" half and a "pointer" half facilitates the use of bounded regions of memory, notably [[Stack-based memory allocation|stacks]].

=== Instructions ===
{| class="infobox" style="font-size:88%;width:36em;"
|-
|+ DEC PDP-10 instruction formats
|-
|
{| style="font-size:88%;"
|- 
| style="width:10px; text-align:center;"| <sup>0</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>8</sub>
| style="width:10px; text-align:center;"| <sup>0</sup><sub>9</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>0</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>1</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>2</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>3</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>4</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>5</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>6</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>7</sub>
| style="width:10px; text-align:center;"| <sup>1</sup><sub>8</sub>
| style="width:60px; text-align:center;"| . . .
| style="width:10px; text-align:center;"| <sup>3</sup><sub>5</sub>
| style="width:auto; background:white; color:black" | ''(bit position)''
|- 
|colspan="20" | '''General instructions'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="9"| <div style="display:inline-block; width:12px">&nbsp;</div> Opcode
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:6px">&nbsp;</div> Acc #
| style="text-align:center" colspan="1"| <div style="display:inline-block; width:0px">&nbsp;</div> I
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:0px">&nbsp;</div> Index #
| style="text-align:center" colspan="17"| <div style="display:inline-block; width:12px">&nbsp;</div> Memory address
|- 
|colspan="12" | '''I/O instructions'''
|- style="background:silver;color:black"
| style="text-align:center" colspan="3"| <div style="display:inline-block; width:8px">&nbsp;</div> 7
| style="text-align:center" colspan="7"| <div style="display:inline-block; width:12px">&nbsp;</div> Device #
| style="text-align:center" colspan="3"| Opcode
| style="text-align:center" colspan="1"| <div style="display:inline-block; width:0px">&nbsp;</div> I
| style="text-align:center" colspan="4"| <div style="display:inline-block; width:0px">&nbsp;</div> Index #
| style="text-align:center" colspan="17"| <div style="display:inline-block; width:12px">&nbsp;</div> Memory address
|} 
|}
Instructions are stored in 36-bit words. There are two formats, general instructions and [[input/output]] instructions.{{sfn|Programming|1970|p=13}}

In general instructions, the leftmost 9 bits, 0 to 8, contain an instruction [[opcode]]. Many of the possible 512 codes are not defined in the base model machines and are reserved for expansion like the addition of a hardware [[floating point unit]]. Following the opcode in bits 9 to 12 is the number of a register which will be used for the instruction. The input/output instructions all start with bits 0 through 2 being set to 1 (decimal value 7), bits 3 through 9 containing a device number, and 10 through 12 the instruction opcode.{{sfn|Programming|1970|p=13}}

In both formats, bits 13 through 35 are used to form the "effective address", E. Bits 18 through 35 contain a numerical constant address, Y. This address may be modified by adding the 18-bit value in a register, X, the register number indicated in bits 14 to 17. If these are set to zero, no indexing is used, meaning register 0 cannot be used for indexing. Bit 13, I, indicates indirection, meaning the ultimate effective address used by the instruction is not E, but the address stored in memory location E. When using indirection, the data in word E is interpreted in the same way as the layout of the instruction; bits 0 to 12 are ignored, and 13 through 35 form I, X and Y as above.

Instruction execution begins by calculating E. It adds the contents of the given register X (if not 0) to the offset Y; then, if the indirect bit is 1, the value at E is fetched and the effective address calculation is repeated. If I is 1 in the stored value at E in memory, the system will then indirect through that address as well, possibly following many such steps.{{sfn|Programming|1970|p=13}} This process continues until an indirect word with a zero indirect bit is reached. Indirection of this sort was a common feature of processor designs of this era.

In supervisor mode, addresses correspond directly to physical memory. In user mode, addresses are translated to physical memory. Earlier models give a user process a "high" and a "low" memory: addresses with a 0 top bit use one base register and those with a 1 use another. Each segment is contiguous.  Later architectures have paged memory access, allowing non-contiguous address spaces. The CPU's general-purpose registers can also be addressed as memory locations 0–15.

====General instructions====
There are three main classes of general instructions: arithmetic, logical, and move; conditional jump; conditional skip (which may have side effects). There are also several smaller classes.

The arithmetic, logical, and move operations include variants which operate immediate-to-register, memory-to-register, register-to-memory, register-and-memory-to-both or memory-to-memory. Since registers may be addressed as part of memory, register-to-register operations are also defined. (Not all variants are useful, though they are well-defined.) For example, the ADD operation has as variants ADDI (add an 18-bit ''I''mmediate constant to a register), ADDM (add register contents to a ''M''emory location), ADDB (add to ''B''oth, that is, add register contents to memory and put the result in the register). A more elaborate example is HLROM (''H''alf ''L''eft to ''R''ight, ''O''nes to ''M''emory), which takes the Left half of the register contents, places them in the Right half of the memory location, and replaces the left half of the memory location with Ones. Halfword instructions are also used for linked lists: HLRZ is the Lisp CAR operator; HRRZ is CDR.

The conditional jump operations examine register contents and jump to a given location depending on the result of the comparison. The mnemonics for these instructions all start with JUMP, JUMPA meaning "jump always" and JUMP meaning "jump never" – as a consequence of the symmetric design of the instruction set, it contains several no-ops such as JUMP. For an example of a conditional jump, JUMPN A,LOC jumps to the address LOC if the contents of register A is non-zero. There are also conditional jumps based on the processor's condition register using the JRST instruction. On the KA10 and KI10, JRST is faster than JUMPA, so the standard unconditional jump is JRST.

The conditional skip operations compare register and memory contents and skip the next instruction (which is often an unconditional jump) depending on the result of the comparison. A simple example is CAMN A,LOC which compares the contents of register A with the contents of location LOC and skips the next instruction if they are not equal.  A more elaborate example is TLCE A,LOC (read "Test Left Complement, skip if Equal"), which using the contents of LOC as a mask, selects the corresponding bits in the left half of register A. If all those bits are ''E''qual to zero, skip the next instruction; and in any case, replace those bits by their Boolean complement.

Some smaller instruction classes include the shift/rotate instructions and the procedure call instructions. Particularly notable are the stack instructions PUSH and POP, and the corresponding stack call instructions PUSHJ and POPJ. The byte instructions use a special format of indirect word to extract and store arbitrary-sized bit fields, possibly advancing a pointer to the next unit.{{efn|cf. {{section link|Byte addressing|Hybrid systems}}}}

====Input/output instructions====
The PDP-10 does not use [[Memory-mapped I/O and port-mapped I/O|memory-mapped devices]], in contrast to the [[PDP-11]] and later DEC machines. A separate set of instructions is used to move data to and from devices defined by a device number in the instruction. Bits 3 to 9 contain the device number, with the 7 bits allowing a total of 128 devices. Instructions allow for the movement of data to and from devices in word-at-a-time (DATAO and DATAI) or block-at-a-time (BLKO, BLKI).{{sfn|Programming|1970|pp=87-88}}

In block mode, the value pointed to by E is a word in memory that is split in two, the right 18 bits indicate a starting address in memory where the data is located (or written into) and the left 18 bits are a counter. The block instructions increment both values every time they are called, thereby increasing the counter as well as moving to the next location in memory. It then performs a DATAO or DATAI. Finally, it checks the counter side of the value at E, if it is non-zero, it skips the next instruction. If it is zero, it performs the next instruction, normally a JUMP back to the top of the loop.{{sfn|Programming|1970|p=88}} The BLK instructions are effectively small programs that loop over a DATA and increment instructions, but by having this implemented in the processor itself, it avoids the need to repeatedly read the series of instructions from main memory and thus performs the loop much more rapidly.{{sfn|Programming|1970|p=89}}

The final set of I/O instructions are used to write and read condition codes on the device, CONO and CONI.{{sfn|Programming|1970|p=86}} Additionally, CONSZ will perform a CONI, bitmask the retrieved data against the value in E, and then skip the next instruction if it is zero, used in a fashion similar to the BLK commands. Only the right 18 bits are tested in CONSZ.{{sfn|Programming|1970|p=87}}

===Interrupt handling===
A second use of the CONO instruction is to set the device's priority level for [[interrupt]] handling. There are three bits in the CONO instruction, 33 through 35, allowing the device to be set to level 0 through 7. Level 1 is the highest, meaning that if two devices raise an interrupt at the same time, the lowest-numbered device will begin processing. Level 0 means "no interrupts", so a device set to level 0 will not stop the processor even if it does raise an interrupt.{{sfn|Programming|1970|p=92}}

Each device channel has two memory locations associated with it, one at 40+2N and the other at 41+2N, where N is the channel number. Thus, channel 1 uses locations 42 and 43. When the interrupt is received and accepted, meaning no higher-priority interrupt is already running, the system stops at the next memory read part of the [[instruction cycle]] and instead begins processing at the address stored in the first of those two locations. It is up to the [[interrupt handler]] to turn off the interrupt level when it is complete, which it can do by running a CONO, DATA or BLK instruction.{{sfn|Programming|1970|p=92}} As a special case, if the instruction is BLKI or BLKO, and the incremented count is not zero, the interrupt is dismissed immediately, otherwise the second instruction is executed to process the interrupt. This provided a low-cost medium performance version of direct memory access.

Two of the device numbers are set aside for special purposes. Device 0 is the computer's front-panel console; reading that device retrieves the settings of the panel switches while writing lights up the status lamps. Device 4 is the "priority interrupt", which can be read using CONI to gain additional information about an interrupt that has occurred.{{sfn|Programming|1970|p=94}}

===Extended addressing===
In processors supporting extended addressing, the address space is divided into "sections".  An 18-bit address is a "local address", containing an offset within a section, and a "global address" is 30 bits, divided into a 12-bit section number at the bottom of the left 18 bits and an 18-bit offset within that section in the right 18 bits.  A register can contain either a "local index", with an 18-bit unsigned displacement or local address in the right 18 bits, or a "global index", with a 30-bit unsigned displacement or global address in the right 30 bits.  An indirect word can either be a "local indirect word", with its uppermost bit set, the next 12 bits reserved, and the remaining bits being an indirect bit, a 4-bit register code, and an 18-bit displacement, or a "global indirect word", with its uppermost bit clear, the next bit being an indirect bit, the next 4 bits being a register code, and the remaining 30 bits being a displacement.<ref name=referencemanual>{{cite web |title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual|id=AA-H391A-TK, AD-H391A-T1|url=http://www.36bit.org/dec/manual/ad-h391a-t1.pdf |publisher=Digital Equipment Corporation |date=June 1982 |access-date=November 14, 2015 |url-status=dead |archive-url=https://web.archive.org/web/20151011152807/http://www.36bit.org/dec/manual/ad-h391a-t1.pdf |archive-date=October 11, 2015}}</ref>{{rp|1-26&ndash;1-30}}

The process of calculating the effective address generates a 12-bit section number and an 18-bit offset within that segment.<ref name="referencemanual"/>{{rp|1-26&ndash;1-30}}

==Software==

===Operating systems===
The original PDP-10 [[operating system]] was simply called "Monitor", but was later renamed [[TOPS-10]].  Eventually the PDP-10 system itself was renamed the DECsystem-10. Early versions of Monitor and TOPS-10 formed the basis of Stanford's [[WAITS]] operating system and the [[CompuServe]] time-sharing system.

Over time, some PDP-10 operators began running operating systems assembled from major components developed outside DEC. For example, the main Scheduler might come from one university, the Disk Service from another, and so on. The commercial timesharing services such as [[CompuServe]], [[Embarq#History|On-Line Systems, Inc.]] (OLS), and [[Time-sharing#Rapidata as an example|Rapidata]] maintained sophisticated inhouse systems programming groups so that they could modify the operating system as needed for their own businesses without being dependent on DEC or others. There are also strong user communities such as [[DECUS]] through which users can share software that they have developed.

[[BBN Technologies|BBN]] developed their own alternative operating system, [[TENEX (operating system)|TENEX]], which fairly quickly became popular in the research community. DEC later ported TENEX to the KL10, enhanced it considerably, and named it [[TOPS-20]], forming the DECSYSTEM-20 line.

[[MIT]], which had developed CTSS, [[Compatible Time-Sharing System]] to run on their [[IBM 709]] (and later a modified [[IBM 7094]] system), also developed ITS, [[Incompatible Timesharing System]]<ref>{{cite web 
|title=A Brief History of Hackerdom: The Early Hackers
|quote=MIT ... built their own operating system, the fabled .. Incompatible Timesharing System
|url=http://catb.org/esr/writings/hacker-history/hacker-history-3.html}}</ref> to run on their [[PDP-6]] (and later a modified PDP-10);{{citation needed|date=August 2023}}

[[Tymshare]] developed [[Tymnet#Organization|TYMCOM-X]], derived from TOPS-10 but using a page-based file system like TOPS-20.<ref>{{Cite web |title=Tymshare Software |url=http://inwap.com/pdp10/tymshare/software/ |access-date=2023-09-24 |website=inwap.com}}</ref>

===Programming languages===
DEC maintained DECsystem-10 [[Fortran#FORTRAN IV|FORTRAN IV]] (F40) for the PDP-10 from 1967 to 1975<ref>{{cite web |last1=Digital Equipment Corp |title=DECsystem-10 FORTRAN IV (F40) Programmers Reference Manual |url=https://github.com/PDP-10/f40/blob/master/doc/DEC-10-LFLMA-B-D%20FORTRAN%20IV%20(F40)%20Programmer's%20Reference%20Manual.pdf |website=Github |publisher=Digital Equipment Corporation |access-date=15 April 2022}}</ref>

MACRO-10 (assembly language macro compiler), COBOL, BASIC and AID were supported under the multi processing and swapping monitors.<ref>{{Cite web |last=Equipment |first=Digital |date=1968 |title=PDP-10 Reference Handbook |url=https://bitsavers.org/pdf/dec/pdp10/1970_PDP-10_Ref/1970PDP10Ref_Part0.pdf |website=bitsavers.org }}</ref>

In practice a number of other programming environments were available including LISP and SNOBOL at the Hatfield Polytechnic site around 1970.

== Clones ==
In 1971 to 1972, researchers at [[Xerox PARC]] were frustrated by top company management's refusal to let them buy a PDP-10. Xerox had just bought [[Scientific Data Systems]] (SDS) in 1969, and wanted PARC to use an SDS machine. Instead, a group led by [[Charles P. Thacker]] designed and constructed two PDP-10 clone systems named MAXC (pronounced as Max, in honour of [[Max Palevsky]], who had sold SDS to Xerox) for their own use. MAXC was also a [[backronym]] for Multiple Access Xerox Computer. MAXC ran a modified version of TENEX.<ref>{{cite interview |title=Oral History of Charles (Chuck) Thacker |interviewer-last=Kossow |interviewer-first=Al |last=Thacker |first=Charles |subject-link=Charles P. Thacker |date=August 29, 2007 |website=[[Computer History Museum]] |url=http://archive.computerhistory.org/resources/text/Oral_History/Thacker_Charles/Thacker_Charles_1.oral_history.2007.1026581226.pdf |access-date=November 15, 2019}}</ref>

Third-party attempts to sell PDP-10 clones were relatively unsuccessful; see [[Foonly]], [[Systems Concepts]], and [[XKL]].

== Use by CompuServe ==
One of the largest collections of DECsystem-10 architecture systems ever assembled was at [[CompuServe]], which, at its peak, operated over 200 loosely coupled systems in three data centers in [[Columbus, Ohio]]. CompuServe used these systems as 'hosts', providing access to commercial applications, and the CompuServe Information Service. While the first such systems were bought from DEC, when DEC abandoned the PDP-10 architecture in favor of the [[VAX]], CompuServe and other PDP-10 customers began buying [[plug compatible]] computers from Systems Concepts. {{As of|January 2007}}, CompuServe was operating a small number of PDP-10 architecture machines to perform some billing and routing functions.

The main power supplies used in the KL-series machines were so inefficient that CompuServe engineers designed a replacement supply that used about half the energy. CompuServe offered to license the design for its KL supply to DEC for free if DEC would promise that any new KL bought by CompuServe would have the more efficient supply installed. DEC declined the offer.
[[File:MF10-Panel.jpg|thumb|right|250px|MF10 Light Panel with [[LED lamps]]]]

Another modification made to the PDP-10 by CompuServe engineers was replacing the hundreds of incandescent indicator lamps on the KI10 processor cabinet with LED lamp modules. The cost of conversion was easily offset by cost savings in electricity use, reduced heat, and labor needed to replace burned-out lamps. Digital followed this step all over the world. The picture on the right hand side shows the light panel of the MF10 memory which is contemporary with the KI10 CPU. This item is part of a computer museum, and was populated with LEDs in 2008 for demonstration purposes only. There were no similar banks of indicator lamps on KL and KS processors themselves - only on legacy memory and peripheral devices.

==Cancellation and influence==
The PDP-10 was eventually eclipsed by the [[VAX]] [[superminicomputer]] machines (descendants of the [[PDP-11]]) when DEC recognized that the PDP-10 and VAX product lines were competing with each other and decided to concentrate its software development effort on the more profitable VAX.  The PDP-10 product line cancellation was announced in 1983, including cancelling the ongoing [[Jupiter project]] to produce a new high-end PDP-10 processor (despite that project being in good shape at the time of the cancellation) and the Minnow project to produce a desktop PDP-10, which may then have been at the prototyping stage.<ref>{{cite web|url=http://www.36bit.org/dec/|title=DEC 36-bit Computers|access-date=April 4, 2009|archive-url=https://web.archive.org/web/20091216153820/http://www.36bit.org/dec/|archive-date=December 16, 2009}}</ref>

This event spelled the doom of [[Incompatible Timesharing System|ITS]] and the technical cultures that had spawned the original [[jargon file]], but by the 1990s it had become something of a badge of honor among old-time hackers to have cut one's teeth on a PDP-10.

The PDP-10 [[assembly language]] instructions LDB and DPB (load/deposit [[byte]]) live on as functions in the [[programming language]] [[Common Lisp]]. See [[Lisp (programming language)#References|the "References" section on the LISP article]]. The 36-bit word size of the PDP-6 and PDP-10 was influenced by the programming convenience of having 2 LISP pointers, each 18 bits, in one word.

[[Will Crowther]] created ''[[Colossal Cave Adventure|Adventure]]'', the prototypical computer adventure game, for a PDP-10. [[Don Daglow]] created the first computer [[baseball]] game (1971) and ''[[Dungeon (video game)|Dungeon]]'' (1975), the first [[role-playing video game]] on a PDP-10. [[Walter Bright]] originally created ''[[Empire (1977 video game)|Empire]]'' for the PDP-10. [[Roy Trubshaw]] and [[Richard Bartle]] created the first [[Multi-user dungeon|MUD]] on a PDP-10. ''[[Zork]]'' was written on the PDP-10. [[Infocom]] used PDP-10s for game development and testing.<ref>{{cite web |url=https://www.filfre.net/2012/01/zork-on-the-pdp-10 |title=Zork on the PDP-10 |quote=Infocom would develop Zork .. PDP-10 .. hosted .. Incompatible Timesharing System ... ARPANET ...  DMG’s machine ... community .. a sort of extended beta-testing team}}</ref>

[[Bill Gates]] and [[Paul Allen]] originally wrote [[Altair BASIC]] using an [[Intel 8080]] simulator running on a PDP-10 at [[Harvard University]]. Allen repurposed the PDP-10 assembler as a [[cross assembler]] for the 8080 chip.<ref>{{Cite book |title=Idea Man: A Memoir by the Cofounder of Microsoft |last=Allen |first=Paul |publisher=Portfolio/Penguin |year=2012 |isbn=978-1-101-47645-1 |pages=74}}</ref> They founded [[Microsoft]] shortly after.

== Emulation or simulation ==
The software for simulation of historical computers, [[SIMH]], contains modules to emulate all the PDP-10 CPU models on a Windows or Unix-based machine. Copies of DEC's original distribution tapes are available as downloads from the Internet so that a running TOPS-10 or TOPS-20 system may be established. ITS and WAITS are also available for SIMH.<ref>{{Cite web|url=http://github.com/PDP-10/its|title = Incompatible Timesharing System|website = [[GitHub]]|date = January 5, 2022}}</ref><ref>{{Cite web|url=http://sky-visions.com/dec/waits/|title=Index of /Dec/Waits}}</ref> A PDP-10 front panel<ref>{{Cite web|url=https://obsolescence.wixsite.com/obsolescence/pidp10|title = PiDP-10: Recreating the PDP-10 at the MIT Lab|date = September 23, 2024}}</ref> replica for the KA10 processor is available for the [[SIMH]] emulation running on a [[Raspberry Pi]].

Ken Harrenstien's KLH10 software for Unix-like systems emulates a KL10B processor with extended addressing and 4 MW of memory or a KS10 processor with 512 KW of memory. The KL10 emulation supports v.442 of the KL10 microcode, which enables it to run the final versions of both TOPS-10 and TOPS-20. The KS10 emulation supports both ITS v.262 microcode for the final version of KS10 ITS and DEC v.130 microcode for the final versions of KS TOPS-10 and TOPS-20.<ref>Tim Shoppa [http://www.columbia.edu/kermit/ftp/e/klh10.txt "Announcing KLH10"], November 10, 2001. Retrieved April 4, 2009.</ref>

{{JargonFile}}

==See also==
*[[Incompatible Timesharing System|ITS]]
*[[TENEX (operating system)]]
*[[TOPS-10]]
*[[TOPS-20]]
*[[WAITS]]

== Notes ==
{{Notelist}}

== References ==
{{Reflist}}

===Sources===
{{Refbegin}}
* {{cite book
 |title=DECsystem10 System Reference Manual
 |publisher=DEC
 |date=1974
 |url=https://www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf
 |archive-date=August 31, 2007
 |access-date=July 26, 2017
 |archive-url=https://web.archive.org/web/20070831041149/https://www.computer.museum.uq.edu.au/pdf/DEC-10-XSRMA-A-D%20DECsystem10%20System%20Reference%20Manual.pdf
 |url-status=dead
 }}
* {{cite book
 |title=DECsystem-10/DECSYSTEM-20 Processor Reference Manual
 |publisher=DEC
 |date=1982
 |url=http://bitsavers.org/pdf/dec/pdp10/TOPS10_softwareNotebooks/vol05/AA-H391A-TK_DECsystem-10_DECSYSTEM-20_Processor_Reference_Jun1982.pdf
 }}
* {{cite book
 |title=Programming with the PDP-10 Instruction Set
 |publisher=DEC
 |date=1970
 |url=http://www.bitsavers.org/pdf/dec/pdp10/1970_PDP-10_Ref/1970PDP10Ref_Part1.pdf
 |ref=CITEREFProgramming1970
 }}
* {{cite book
  | last = Ceruzzi
  | first = Paul E.
  | title = A History of Modern Computing
  | publisher = MIT Press
  | year = 2003
  | edition = 2
  | isbn = 0-262-53203-4
  | url = https://archive.org/details/historyofmodernc00ceru_0
  | url-access = registration
  }}
{{Refend}}

== Further reading ==
*[[C. Gordon Bell]], [[Alan Kotok]], Thomas N. Hastings, Richard Hill, "The Evolution of the DECsystem 10", ''Communications of the ACM'' '''21''':1:44 (January 1978) {{doi|10.1145/359327.359335}}, [http://research.microsoft.com/users/GBell/Computer_Engineering/00000511.htm reprint] in C. Gordon Bell, J. Craig Mudge, John E. McNamara, ''Computer Engineering: A DEC View of Hardware Systems Design'' (Digital Press, 1978, {{isbn|0932376002}})

== External links ==
{{Commons category}}
*[http://www.inwap.com/pdp10/ 36 Bits Forever!]
*[http://www.inwap.com/pdp10/models.txt PDP-10 Models] — Shows CPUs and models
*[http://pdp10.nocrew.org/ PDP-10 stuff]
*[http://www.ultimate.com/phil/pdp10/ PDP10 Miscellany Page]
*[http://www.ultimate.com/phil/pdp10/Fast-ACs Life in the Fast AC's]
*[https://www.columbia.edu/cu/computinghistory/pdp10.html Columbia University DEC PDP-10 page]
*[https://web.archive.org/web/20060103002833/https://panda.com/tops-20/ Panda Programming TOPS-20 page]
*[https://wiki.sdf.org/doku.php?id=vintage_systems:start Online PDP-10 and related systems] at [[SDF Public Access Unix System|SDF's]] [https://icm.museum Interim Computer Museum] (includes some systems that were originally part of the [[Paul Allen]] collection at [[Living Computers: Museum + Labs]]).
*[https://web.archive.org/web/20140803040442/https://ftp.classicempire.com/pdp10.zip Empire] for the PDP-10 (zip file of [[FORTRAN]]-10 source code download) from [http://www.classicempire.com Classic Empire]
*[http://pdp-10.trailing-edge.com/ PDP-10 software archive at Trailing Edge]
*[http://computerworld.com.edgesuite.net/digital_mainframe_11981.jpg The Personal Mainframe ad] {{Webarchive|url=https://web.archive.org/web/20181106024524/http://computerworld.com.edgesuite.net/digital_mainframe_11981.jpg |date=November 6, 2018 }}
*Computer World [https://web.archive.org/web/20070627020521/http://www.computerworld.com/action/article.do?command=viewArticleBasic&articleId=9024559&pageNumber=6  ad for Personal Mainframe] 
*[http://bitsavers.informatik.uni-stuttgart.de/pdf/dec/pdp10/ PDP-10 documentation at Bitsavers]

=== Newsgroups ===
*[news:alt.sys.pdp10 alt.sys.pdp10]

{{DEC hardware}}
{{Authority control}}

[[Category:DEC mainframe computers]]
[[Category:36-bit computers]]
[[Category:Computer-related introductions in 1966]]
[[Category:Computers using bit-slice designs]]