View source for Pentium Pro

{{Short description|Sixth-generation x86 microprocessor by Intel}}
{{Use mdy dates|date=January 2023}}
{{Infobox CPU
|image = Intel Pentium Pro logo.svg
|image_size = 150px
|caption =
|produced-start = {{start date and age|1995|11|01|br=y|p=y}}
|produced-end = 1998
|slowest = 150 | slow-unit = MHz
|fastest = 200 | fast-unit = MHz
|fsb-slowest = 60 | fsb-slow-unit = MT/s
|fsb-fastest = 66 | fsb-fast-unit = MT/s
|manuf1 = Intel
|arch = x86
|size-from = 500 nm
|size-to = 350 nm
|microarch = [[P6 (microarchitecture)|P6]]
|sock1 = [[Socket 8]]
|numcores = 1
|predecessor = [[Pentium (original)|Pentium]]
|successor=[[Pentium II]], [[Pentium II Xeon]]
| support status = Unsupported
|designfirm=Intel|soldby=[[Intel]]|code=80521|l2cache=256 KB – 1 MB|data-width=64 bits|address-width=36 bits|virtual-width=32 bits|l1cache=16 KB (8 KB instructions + 8 KB data)|transistors1=5.5 million|application=[[Server (computing)|Server]]<br />[[Workstation]]|cpuid=0F619h}}
The '''Pentium Pro''' is the first sixth-generation [[x86]]-based [[microprocessor]] developed and manufactured by [[Intel]] and introduced on November 1, 1995.{{r|Fisher_19951102|p=D-2}} It implements the [[P6 (microarchitecture)|P6]] microarchitecture (sometimes termed i686), and was the first x86 Intel CPU to do so.

The Pentium Pro was originally intended to replace the original [[Pentium (original)|Pentium]] in a full range of applications. Later, it was reduced to a more narrow role as a server and high-end desktop processor. The Pentium Pro was also used in [[supercomputer]]s, most notably [[ASCI Red]], which was the first computer to reach over one [[teraFLOPS]] in 1996 and held the number one spot in the [[TOP500]] list from 1997 to 2000. ASCI Red used two Pentium Pro CPUs on each computing node.{{r|ASCI_Red}}

While the Pentium and Pentium MMX had 3.1 and 4.5&nbsp;million [[transistor]]s, respectively, the Pentium Pro contained 5.5&nbsp;million transistors.{{r|Brey_2003|p=[https://archive.org/details/intelmicroproces0000brey_x6t8/page/12 12]}} It was capable of both dual- and quad-processor configurations and only came in one form factor, the relatively large rectangular [[Socket 8]]. The Pentium Pro was succeeded by the [[Pentium II Xeon]] in 1998.

==Microarchitecture==
[[File:Intel Pentium Pro Microarchitecture Block Diagram.svg|thumb|266px|right|Block Diagram of the Pentium Pro's Microarchitecture]]
[[File:Ppro512K.jpg|thumb|upright|200&nbsp;MHz Pentium Pro with a 512&nbsp;KB L2 cache in [[Pin grid array|PGA]] package]]
[[File:Pentium Pro Black Edition Front.jpg|thumb|upright|200&nbsp;MHz Pentium Pro with a 1&nbsp;MB L2 cache in [[Pin grid array|PPGA]] package]]
[[File:Pentiumpro moshen.jpg|thumb|upright|[[Decapping|Decapped]] Pentium Pro 256&nbsp;KB]]

The lead architect of Pentium Pro was [[Fred Pollack]] who was specialized in [[superscalar]]ity and had also worked as the lead engineer of the [[Intel iAPX 432]].{{r|dvorak}}

===Summary===
{{More citations needed section|date=March 2014}}

The Pentium Pro incorporated a new [[microarchitecture]], different from the Pentium's [[P5 (microarchitecture)|P5]] microarchitecture. It has a decoupled, 14-stage superpipelined architecture which used an instruction pool.
The Pentium Pro ([[P6 (microarchitecture)|P6]]) implemented many radical architectural differences mirroring other contemporary [[x86]] designs such as the [[NexGen]] [[Nx586]] and [[Cyrix]] [[6x86]]. The Pentium Pro pipeline had extra decode stages to dynamically translate [[IA-32]] instructions into buffered [[micro-operation]] sequences which could then be analysed, reordered, and renamed in order to detect parallelizable operations that may be issued to more than one [[execution unit]] at once. The Pentium Pro thus featured [[out-of-order execution]], including [[speculative execution]] via [[register renaming]]. It also had a wider 36-bit [[address bus]], usable by [[Physical Address Extension]] (PAE), allowing it to access up to 64 GB ({{nowrap|64{{nbsp}}×{{nbsp}}1024<sup>3</sup> bytes)}} of memory.

The Pentium Pro has an 8&nbsp;KB [[instruction cache]], from which up to 16 bytes are [[Instruction cycle#Summary of stages|fetched]] on each cycle and sent to the [[instruction decoder]]s. There are three instruction decoders. The decoders are unequal in ability: only one can decode any x86 instruction, while the other two can only decode simple x86 instructions. This restricts the Pentium Pro's ability to decode multiple instructions simultaneously, limiting superscalar execution. x86 instructions are decoded into 118-bit [[micro-operation]]s (micro-ops). The micro-ops are [[reduced instruction set computer]] (RISC)-like; that is, they encode an operation, two sources, and a destination. The general decoder can generate up to four micro-ops per cycle, whereas the simple decoders can generate one micro-op each per cycle. Thus, x86 instructions that operate on the memory (e.g., add this register to this location in the memory) can only be processed by the general decoder, as this operation requires a minimum of three micro-ops. Likewise, the simple decoders are limited to instructions that can be translated into one micro-op. Instructions that require more micro-ops than four are translated with the assistance of a sequencer, which generates the required micro-ops over multiple clock cycles. The Pentium Pro was the first processor in the x86 family to support upgradeable [[microcode]] under [[BIOS]] and/or [[operating system]] (OS) control.{{r|Stiller_1996}}

Micro-ops exit the [[re-order buffer]] (ROB) and enter a [[reservation station]] (RS), where they await dispatch to the execution units. In each clock cycle, up to five micro-ops can be dispatched to five execution units. The Pentium Pro has a total of six execution units: two integer units, one [[floating-point unit]] (FPU), a load unit, store address unit, and a store data unit.<ref name="iaopt">{{cite web |url=http://download.intel.com/design/PentiumII/manuals/24281603.PDF |archive-url=https://web.archive.org/web/20070121103522/http://download.intel.com/design/PentiumII/manuals/24281603.PDF |archive-date=2007-01-21 |url-status=dead |title=Intel Architecture Optimization Manual |page=2{{hyp}}8 |date=1997 }}</ref> One of the integer units shares the same ports as the FPU, and therefore the Pentium Pro can only dispatch one integer micro-op and one floating-point micro-op, or two integer micro-ops per a cycle, in addition to micro-ops for the other three execution units. Of the two integer units, only the one that shares the path with the FPU on port 0 has the full complement of functions such as a [[barrel shifter]], multiplier, divider, and support for LEA instructions. The second integer unit, which is connected to port 1, does not have these facilities and is limited to simple operations such as add, subtract, and the calculation of branch target addresses.<ref name="iaopt"/>

The FPU executes floating-point operations. Addition and multiplication are pipelined and have a latency of three and five cycles, respectively. Division and square-root are not pipelined and are executed in separate units that share the FPU's ports. Division and square root have a latency of 18-36 and 29-69 cycles, respectively. The smallest number is for single precision (32-bit) floating-point numbers and the largest for extended precision (80-bit) numbers. Division and square root can operate simultaneously with adds and multiplies, preventing them from executing only when the result has to be stored in the ROB.

After the microprocessor was released, a bug was discovered in the [[floating point unit]], commonly called the "Pentium Pro and Pentium II FPU bug" and by Intel as the "flag erratum". The bug occurs under some circumstances during floating point-to-integer conversion when the floating point number will not fit into the smaller integer format, causing the FPU to deviate from its documented behaviour. The bug is considered to be minor and occurs under such special circumstances that very few, if any, software programs are affected.

The Pentium Pro [[P6 (microarchitecture)|P6 microarchitecture]] was used in one form or another by Intel for more than a decade. The pipeline would scale from its initial 150&nbsp;MHz start, all the way up to 1.4&nbsp;GHz with the "Tualatin" [[Pentium III]]. The design's various traits would continue after that in the derivative core called "[[Banias (microprocessor)|Banias]]" in [[Pentium M]] and [[Intel Core]] ([[Yonah (microprocessor)|Yonah]]), which itself would evolve into the [[Intel Core (microarchitecture)|Core microarchitecture]] ([[Core 2]] processor) in 2006 and onward.{{r|Stokes_20060405}}

===Instruction set===

The Pentium Pro (P6) introduced new 'conditional move' instructions into the Intel range; the <code>CMOV''cc''</code> and <code>FCMOV''cc''</code> ('conditional move') instructions fetch a source value from a register or memory, and optionally write that value to a destination register according to a condition ''cc''  on the flags register, the same conditions used by the conditional jump (<code>J''cc''</code>) instructions. For example, <code>CMOVNE</code> moves a specified value into a register if the flags register matches the NE (not-equal) condition, i.e. the [[zero flag]] is unset.  If the zero flag is set, the condition in false, and the destination register keeps its value.  This allows simple if-then-else operations (such as commonly used by the [[Ternary conditional operator|<code>? :</code> operation]] in [[C (programming language)|C]]) without a costly conditional branch.  The <code>FCMOV''cc''</code> variant provides the same functionality for floating-point registers.  Unfortunately, <code>CMOV</code> does not support immediate (in-line constant) source values nor memory destinations.

A second development was the documentation of the <code>UD2</code> illegal instruction. This op code is reserved and guaranteed to cause an illegal instruction exception on the P6 and all later processors. This allows developers to easily crash the current program in a future-proof fashion when a bug is detected by software.

===Performance===
Despite being advanced for the time, the Pentium Pro's out-of-order register renaming architecture had trouble running [[16-bit computing|16-bit]] code and mixed code ([[8-bit computing|8-bit]] with 16-bit (8/16), or 16-bit with [[32-bit computing|32-bit]] (16/32), as using partial registers caused frequent pipeline flushing.<ref>{{cite web |url=http://qcd.phys.cmu.edu/QCDcluster/intel/vtune/reference/LipsPro_Partial_Stall.htm |title=Partial Register Stall Warning |work=VTune Performance Analyzer online help |archive-url=https://web.archive.org/web/20170830055933/http://qcd.phys.cmu.edu/QCDcluster/intel/vtune/reference/LipsPro_Partial_Stall.htm |archive-date=August 30, 2017 |url-status=dead}}</ref> Specific use of partial registers was then a common performance optimization, as it incurred no performance penalty on pre-P6 Intel processors; also, the dominant operating systems at the time of the Pentium Pro's release were 16-bit [[MS-DOS]], and mixed 16/32-bit [[Windows 3.1x]] and [[Windows 95]] (although the latter requires a 32-bit [[i386|80386]] CPU as a minimum, much of its code is still 16-bit for performance reasons, such as the 16-bit [[Windows USER]] [[dynamic link library]], [[Windows USER#Implementation|user.exe]]). This, along with the high cost of Pentium Pro systems, led to tepid sales among PC buyers at the time. To fully use the Pentium Pro's [[P6 (microarchitecture)|P6 microarchitecture]], a fully 32-bit operating system is needed, such as [[Windows NT]], [[Linux]], [[Unix]], or [[OS/2]]. The performance issues on legacy code were later partly mitigated by Intel with the Pentium II.

Compared to RISC microprocessors, the Pentium Pro, when introduced, slightly outperformed the fastest RISC microprocessors on integer performance when running the [[SPECint]]95 benchmark,{{r|MPR 1995-11-13|p=2}} but floating-point performance was significantly lower, half that of some RISC microprocessors.{{r|MPR 1995-11-13|p=3}} The Pentium Pro's integer performance lead disappeared rapidly, first overtaken by the [[MIPS Technologies]] [[R10000]] in January 1996, and then by [[Digital Equipment Corporation]]'s EV56 variant of the [[Alpha 21164]].<ref name="MPR 1996-07-08">{{cite magazine |last=Gwennap |first=Linley |date=July 8, 1996 |title=Digital's 21164 Reaches 500 MHz |magazine=[[Microprocessor Report]]}}</ref>

Reviewers quickly noted the very slow writes to video memory as the weak spot of the P6 platform, with performance here being as low as 10% of an identically clocked Pentium system in benchmarks such as VIDSPEED. Methods to circumvent this included setting VESA drawing to system memory instead of video memory in games such as ''[[Quake (video game)|Quake]]'',<ref>{{Cite web|url=https://github.com/id-Software/Quake/blob/master/WinQuake/data/TECHINFO.TXT|title=Quake/TECHINFO.TXT at master · id-Software/Quake|website=[[GitHub]]|date=November 25, 2022|access-date=February 10, 2019|archive-date=June 10, 2017|archive-url=https://web.archive.org/web/20170610101303/https://github.com/id-Software/Quake/blob/master/WinQuake/data/TECHINFO.TXT|url-status=live}}</ref> and later on utilities such as FASTVID emerged, which could double performance in certain games by enabling the [[write combining]] features of the CPU.<ref>{{Cite web|url=http://www.gamers.org/dEngine/quake/info/techinfo.09|title=Quake Technical Information file}}{{Dead link|date=September 2025 |bot=InternetArchiveBot }}</ref><ref>{{Cite web|url=https://www.mdgx.com/umb.htm#FAS|title=MDGx Complete UMBPCI.SYS Guide|at=Fast Video|website=MDGx MAX Speed WinDOwS Tricks + Secrets|access-date=January 7, 2023|archive-date=January 7, 2023|archive-url=https://web.archive.org/web/20230107204339/https://www.mdgx.com/umb.htm#FAS|url-status=live}}</ref> [[Memory type range register]]s (MTRRs) are set automatically by Windows video drivers starting from 1997, and from there the improved cache/memory subsystem and FPU performance caused it to outclass the Pentium clock-for-clock in the emerging 3D games of the mid–to–late 1990s, particularly when using [[Windows NT 4.0]]. However, its lack of [[MMX (instruction set)|MMX]] implementation reduces performance in multimedia applications that made use of those instructions.

===Caching===
Likely Pentium Pro's most noticeable addition was its on-package [[L2 cache]], which ranged from 256&nbsp;KB at introduction to 1&nbsp;MB in 1997. At the time, manufacturing technology did not feasibly allow a large L2 cache to be integrated into the processor core. Intel instead placed the L2 die(s) separately in the package which still allowed it to run at the same clock speed as the CPU core. Additionally, unlike most motherboard-based cache schemes that shared the main system bus with the CPU, the Pentium Pro's cache had its own [[back-side bus]] (called ''[[dual independent bus]]'' by Intel). Because of this, the CPU could read main memory and cache concurrently, greatly reducing a traditional bottleneck.<ref>{{cite magazine |title=Accelerated Graphics Port |magazine=[[Next Generation (magazine)|Next Generation]]|issue=37|publisher=[[Imagine Media]] |date=January 1998 |pages=94–96}}</ref> The cache was also "non-blocking", meaning that the processor could issue more than one cache request at a time (up to 4), reducing cache-miss penalties; an example of [[memory-level parallelism]] (MLP). These properties combined to produce an L2 cache that was immensely faster than the motherboard-based caches of older processors. This cache alone gave the CPU an advantage in input/output performance over older [[x86]] CPUs. In multiprocessor configurations, Pentium Pro's integrated cache skyrocketed performance in comparison to architectures which had each CPU sharing a central cache.

However, this far faster L2 cache did come with some complications. The Pentium Pro's "on-package cache" arrangement was unique. The processor and the cache were on separate dies in the same package and connected closely by a full-speed bus. The two or three dies had to be bonded together early in the production process, before testing was possible. This meant that a single, tiny flaw in either die made it necessary to discard the entire assembly, which was one of the reasons for the Pentium Pro's relatively low production yield and high cost. All versions of the chip were expensive, those with 1024&nbsp;KB being particularly so, since it required two 512&nbsp;KB cache dies as well as the processor die.

==Available models==
Pentium Pro clock speeds were 150, 166, 180 or 200&nbsp;MHz with a 60 or 66&nbsp;MHz [[Front-side bus|external bus]] clock. A prototype 133&nbsp;MHz Pentium Pro was developed in its earliest stages of development but was never released. Some users chose to [[overclock]] their Pentium Pro chips, with the 200&nbsp;MHz version often being run at 233&nbsp;MHz, the 180&nbsp;MHz version often being run at 200&nbsp;MHz, and the 150&nbsp;MHz version often being run at 166&nbsp;MHz. The chip was popular in [[symmetric multiprocessing]] configurations, with dual and quad SMP server and workstation setups being commonplace.

The first computer system to ship with a Pentium Pro was released by [[Advanced Logic Research]] in April 1996 with the Revolution Quad6; as the name suggests, it supports up to four Pentium Pros running in a SMP configuration.<ref>{{cite magazine | last=Damore | first=Kelley | date=July 8, 1996 | url=https://www.proquest.com/docview/227489880 | title=Revolution Quad6: Two-month lead over other vendors | magazine=Computer Reseller News | publisher=CMP Publications | page=65 | id={{ProQuest|227489880}} }}</ref> Intel skipped out on providing a [[mobile processor|mobile]] version of the original Pentium Pro due to power draw and heat concerns.<ref>{{cite journal |last=April |first=Carolyn A. |date=December 16, 1996 |url=https://books.google.com/books?id=FjoEAAAAMBAJ&pg=PA14 |title=Intel postpones Pentium Pro notebook drive |journal=InfoWorld |publisher=IDG Publications |volume=18 |issue=51 |page=14 |via=Google Books |access-date=June 2, 2023 |archive-date=June 2, 2023 |archive-url=https://web.archive.org/web/20230602182102/https://books.google.com/books?id=FjoEAAAAMBAJ&pg=PA14 |url-status=live }}</ref> At least one vendor sold a [[portable computer]] with a Pentium Pro: Imperial Computer's 6200TLP.<ref>{{cite journal |last=O'Brien |first=Bill |date=November 1996 |url=https://link.gale.com/apps/doc/A18794682/GPS?sid=wikipedia |title=Pentium Pro built to go |journal=Computer Shopper |publisher=SX2 Media Labs |volume=16 |issue=11 |page=420 |via=Gale}}</ref>

In Intel's "Family/Model/Stepping" scheme, the Pentium Pro is family 6, model 1, and its Intel Product code is 80521.

{| class="wikitable sortable"
|-
! Clock
! Bus
! L2-Cache
! Max TDP
|-
| 150&nbsp;MHz || 60&nbsp;MHz || {{0}}256 KB || 29.2 W
|-
| 166&nbsp;MHz || 66&nbsp;MHz || {{0}}512 KB || 35.0 W
|-
| 180&nbsp;MHz || 60&nbsp;MHz || rowspan="2" | {{0}}256 KB || 31.7 W
|-
| rowspan="3" | 200&nbsp;MHz || rowspan="3" | 66&nbsp;MHz || 35.0 W
|-
| {{0}}512 KB || 37.9 W
|-
| 1024 KB || 44.0 W
|}

==Fabrication==
The process used to fabricate the Pentium Pro processor die and its separate cache memory die changed, leading to a combination of processes used in the same package:
* The 133&nbsp;MHz Pentium Pro prototype processor die was fabricated in a 0.6&nbsp;μm BiCMOS process.<ref>Papworth, David B. (April 1996). "Tuning the Pentium Pro Microarchitecture". ''[[IEEE Micro]]'', pp. 14–15.</ref><ref name="FAB1">{{cite web |url=http://www.intel.com/support/processors/pentiumpro/sb/cs-011161.htm |title=Intel Pentium Pro Processors - Fact Sheet |archive-url=https://web.archive.org/web/20131207042845/http://www.intel.com/support/processors/pentiumpro/sb/cs-011161.htm |archive-date=December 7, 2013 |publisher=Intel}}</ref>
* The 150&nbsp;MHz Pentium Pro processor die was fabricated in a 0.50&nbsp;μm [[BiCMOS]] process.<ref name="FAB1"/><ref name="MPR 1995-11-13"/>
* The 166, 180, and 200&nbsp;MHz Pentium Pro processor die was fabricated in a 0.35&nbsp;μm BiCMOS process.<ref name="FAB1"/><ref name="MPR 1995-11-13"/>
* The 256&nbsp;KB L2 cache die was fabricated in a 0.50&nbsp;μm BiCMOS process.<ref name="FAB1"/><ref name="MPR 1995-11-13"/>
* The 512 and 1024&nbsp;KB L2 cache die was fabricated in a 0.35&nbsp;μm BiCMOS process.<ref name="FAB1"/><ref name="MPR 1995-11-13"/>

==Packaging==
The Pentium Pro (up to 512&nbsp;KB cache) is packaged in a ceramic multi-chip module (MCM). The MCM has 387&nbsp;pins, of which approximately half are arranged in a pin grid array (PGA) and half in an interstitial pin grid array (IPGA). The packaging was designed for [[Socket 8]]. The MCM contains two underside cavities in which the microprocessor die and its companion cache die reside. The dies are bonded to a heat slug, whose exposed top helps the heat from the dies to be transferred more directly to cooling apparatus such as a heat sink. The dies are connected to the package using conventional wire bonding. The cavities are capped with a ceramic plate. The Pentium Pro with 1&nbsp;MB of cache uses a plastic MCM. Instead of two cavities, there is only one, in which the three dies reside, bonded to the package instead of a heat slug. The cavities are filled in with epoxy.

==Upgrade paths==
In 1998, the 300/333&nbsp;MHz [[Pentium OverDrive#Socket 8|Pentium II OverDrive]] processor for Socket&nbsp;8 was released. Based on some of the technology used in the ''Deschutes'' [[Pentium II Xeon]], it featured double L1 and 512&nbsp;KB of full-speed L2 cache with [[MMX (instruction set)|MMX]] capabilities, and was produced by Intel as a drop-in upgrade option for owners of Pentium Pro systems. However, it only supported two-way [[glueless]] multiprocessing and not four-way or higher, which did not make it a usable upgrade for quad-processor systems. Despite this, some users have unofficially upgraded their quad- and even hexa-processor systems (especially the ALR 6x6) with varying degrees of success.<ref>{{Cite web|url=https://arstechnica.com/civis/threads/re-my-custom-alr-6x6-is-now-finished.878654/|title=Re: My Custom ALR 6x6 is now FINISHED!!!!!!|date=December 5, 2001|website=Ars OpenForum|access-date=April 13, 2025}}</ref>

The ASCI Red supercomputer also utilized these specially packaged Pentium II OverDrive processors in 1999 to make it the first computer overall to exceed the two teraFLOPS performance mark that year, further maintaining its position on the TOP500 list until it was surpassed by the [[ASCI White]] supercomputer in 2000. The original dual Pentium Pro processors used since its inception in 1996 were replaced with dual Pentium II OverDrive processors on each computing node. ASCI Red then continued to use dual Pentium II OverDrive processors for the remainder of its lifespan before being decommissioned in 2006.

As [[Slot 1]] motherboards became prevalent, several manufacturers released [[slotket]] (or slocket) adapters in the form of [[Socket 8]] to Slot 1 adapters, which includes the Tyan M2020, Asus C-P6S1, Tekram P6SL1, and the Abit KP6. These slotkets allowed Pentium Pro processors to be used with Slot&nbsp;1 motherboards, however only a few number of chipsets supported these slotkets and so did not see widespread use. For instance, the [[Intel 440FX]] chipset explicitly supported both Pentium Pro and Pentium II processors but the [[Intel 440BX]] and later Slot&nbsp;1 chipsets only explicitly supported the Pentium II and not the Pentium Pro.

Slotkets eventually saw renewed popularity in the form of [[Socket 370]] to Slot&nbsp;1 adapters, when Intel introduced Socket&nbsp;370 [[Celeron]] and [[Pentium III]] processors in the late 1990s. These form of slotkets allowed for lower costs for computer builders, especially with dual-processor machines, and gave Slot 1 motherboards the ability to continue receiving CPU upgrades beyond the then-currently available Slot 1 CPUs. They also came equipped with their own voltage regulator modules, in order to supply the new CPU with a lower core voltage, which the motherboard would not otherwise allow.

==Core specifications==
===Pentium Pro===
* [[L1 cache]]: 8, 8&nbsp;KB (data, instructions)
* [[L2 cache]]: 256, 512&nbsp;KB (one die) or 1024&nbsp;KB (two 512&nbsp;KB dies) in a [[multi-chip module]] clocked at CPU-speed
* Socket: [[Socket 8]]
* [[Front-side bus]]: 60 and 66&nbsp;MHz
* VCore: 3.1–3.3&nbsp;V
* Fabrication: 0.50&nbsp;μm or 0.35 [[BiCMOS]]<ref>[http://www.sandpile.org/impl/p6.htm sandpile.org] {{webarchive |url=https://archive.today/19990901230543/http://www.sandpile.org/impl/p6.htm |date=September 1, 1999}} - IA-32 implementation - Intel P6</ref>
* Clockrate: 150, 166, 180, 200&nbsp;MHz, (capable of 233&nbsp;MHz on some motherboards)
* First release: November 1995

===Pentium II Overdrive===
[[File:KL Intel PPro Overdrive P6T Top.jpg|thumb|upright|Pentium II Overdrive with heatsink removed. Flip-chip Deschutes core is on the left. 512&nbsp;KB cache is on the right.<ref>{{cite web |url=http://www.heise.de/ct/english/98/18/020/ |title=Next Exit: Mendocino |last=Schnurer |first=Georg |access-date=April 24, 2009 |archive-url=https://web.archive.org/web/20060219205645/http://www.heise.de/ct/english/98/18/020/ |archive-date=February 19, 2006 |url-status=dead}}</ref>]]
* L1 cache: 16, 16&nbsp;KB (data + instructions)
* L2 cache: 512&nbsp;KB external chip on CPU module clocked at CPU-speed
* Socket: Socket&nbsp;8
* Multiplier: Locked at 5×
* Front-side bus: 60 and 66&nbsp;MHz
* VCore: 3.1–3.3&nbsp;V (has on-board voltage regulator)
* Fabrication: 0.25&nbsp;μm
* Clockrate: Based on the [[Pentium II#Deschutes (80523)|Deschutes]]-generation Pentium II
* First release: 1997
* Supports [[MMX (instruction set)|MMX]] technology

== Bus and multiprocessor capabilities ==
The design of the Pentium Pro bus was influenced by [[Futurebus]], the [[Intel iAPX 432]] bus, and elements of the [[Intel i960]] bus.<ref name="Hard1997">{{cite web |url=https://www.drdobbs.com/back-to-the-futurebus/184410391 |access-date=September 19, 2020 |title=Back to the Futurebus |last=Hardenberg |first=Hal W. |date=June 1, 1997 |website=drdobbs.com |publisher=[[Dr. Dobb's Journal]] |archive-date=January 28, 2021 |archive-url=https://web.archive.org/web/20210128155545/https://www.drdobbs.com/back-to-the-futurebus/184410391 |url-status=live }}</ref> Futurebus was intended to replace the [[VMEbus]] used by the [[Motorola 68000]] from the late 1970s as the main standardized advanced bus, however it remained in stagnation within the standardization committee for many decades.<ref name="Hard1997"/> Intel's iAPX 432 initiative was also a [[commercial failure]], however they did learn how to build a split-transaction bus to support a cacheless multiprocessor system afterwards. The i960 had further developed the split-transaction iAPX 432 bus to include a cache coherency protocol, ending up with a feature set highly reminiscent of Futurebus' ambitions.<ref name="Hard1997"/>

The Pentium Pro used [[GTL+]] signaling in its front-side bus.<ref name="Shanley1998">{{cite book |last=Shanley |first=Tom |date=1998 |title=Pentium Pro and Pentium II System Architecture |url=https://books.google.com/books?id=MLJClvCYh34C&pg=PA199 |publisher=[[Addison-Wesley Professional]] |isbn=978-0-201-30973-7 |page=199}}</ref> The Pentium Pro could be used by itself on up to four-way designs. Eight-way Pentium Pro computers were also built, however these used multiple buses.<ref name="Guruge2000">{{cite book |last=Guruge |first=Anura |date=May 17, 2000 |title=Web-to-Host Connectivity |url=https://books.google.com/books?id=OoVaRlU8Um0C&pg=PA405 |publisher=[[CRC Press]] |isbn=978-0-203-99747-5 |page=405}}</ref> The Pentium Pro was also designed to include the four-way SMP split-transaction cache-coherent bus as a mandatory feature of every chip produced,<ref name="Hard1997"/> which also serves as a way to deny competition access to the socket using cloned processors.<ref name="Hard1997"/>

While the Pentium Pro was not successful as a machine for the masses due to poor 16-bit support for Windows 95 and many other 16-bit and mixed 16/32-bit operating systems (as mentioned above), it did see significant successes in the [[file server]] space due to its advanced, integrated bus design,<ref name="Hard1997"/> introducing many advanced features that had formerly only been available in the pricey workstation segment into the commodity marketplace.

==Pentium Pro/6th generation competitors==
* [[AMD K5]] and [[AMD K6|K6]]
* [[Cyrix 6x86]] and [[Cyrix 6x86|MII]]
* IDT [[WinChip]]
* Intel [[P5 (microarchitecture)|P5]] [[Pentium]], co-existed with Pentium Pro for several years

==See also==
* [[List of Intel Pentium II microprocessors]]
* [[List of Intel Pentium Pro microprocessors]]

==References==
{{Reflist|30em|refs=

<ref name="Fisher_19951102">{{cite news |last1=Fisher |first1=Lawrence M. |date=November 2, 1995 |title=Intel Offers Its Pentium Pro For Work Station Market |url=https://www.nytimes.com/1995/11/02/business/intel-offers-its-pentium-pro-for-work-station-market.html |url-status=live |url-access=subscription |work=[[The New York Times]] |language=en-us |edition=New York |page=D-2 |eissn=1553-8095 |issn=0362-4331 |archive-url=https://web.archive.org/web/20090804001226/https://www.nytimes.com/1995/11/02/business/intel-offers-its-pentium-pro-for-work-station-market.html |archive-date=August 4, 2009 |access-date=December 28, 2022 |quote=The Intel Corporation today introduced its new microprocessor, the Pentium Pro. But although the chip's performance is higher than expected, and its price lower, analysts said its immediate impact was not likely to match that of its predecessor, the Pentium. |df=dmy-all }}</ref>

<ref name="Brey_2003">{{cite book |last1=Brey |first1=Barry B. |date=2003 |chapter=Introduction to the Microprocessor and Computer |chapter-url=https://archive.org/details/intelmicroproces0000brey_x6t8/page/1 |chapter-url-access=registration |title=The Intel Microprocessors 8086/8088, 80186, 80286, 80386, 80486: Architecture, Programming, and Interfacing |url=https://archive.org/details/intelmicroproces0000brey_x6t8/page/1 |url-access=registration |edition=Sixth (International) |publisher=[[Pearson Education]] |page=12 |isbn=978-0130487209 |lccn=93021801 |oclc=224097450 |ol=OL1412841M |access-date=December 15, 2022 |df=dmy-all }}</ref>

<ref name="ASCI_Red">{{cite web |url=https://www.top500.org/resources/top-systems/asci-red-sandia-national-laboratory/ |date=n.d. |title=ASCI Red: Sandia National Laboratory |website=[[TOP500]] |access-date=January 7, 2023 |quote=Intel's ASCI Red supercomputer was the first teraflop/s computer, taking the No.1 spot on the 9th TOP500 list in June 1997 with a Linpack performance of 1.068 teraflop/s. [...] It was a mesh-based (38 X 32 X 2) MIMD massively parallel machine initially consisting of 7,264 compute nodes, 1,212 gigabytes of total distributed memory and 12.5 terabytes of disk storage. The original incarnation of this machine used Intel Pentium Pro processors, each clocked at 200 MHz. These were later upgraded to Pentium II OverDrive processors. The system was upgraded to a total of 9,632 Pentium II Over-Drive processors, each clocked at 333 MHz. |archive-date=January 7, 2023 |archive-url=https://web.archive.org/web/20230107213536/https://www.top500.org/resources/top-systems/asci-red-sandia-national-laboratory/ |url-status=live }}</ref>

<ref name="dvorak">{{cite web |url=http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/ |date=November 25, 2006 |title=Whatever Happened to The iAPX432 – Intel's Dream Chip? |last1=Dvorak |first1=John C. |author-link1=John C. Dvorak |website=Dvorak Uncensored |access-date=December 28, 2022 |archive-url=https://web.archive.org/web/20081213193013/http://www.dvorak.org/blog/whatever-happened-to-the-intel-iapx432/ |language=en-us |archive-date=December 13, 2008 |url-status=live |quote=There were a lot of pieces involved in this chip but today's Pentium Pro consists of two chips and other needed support chips too. Curiously the lead engineer for the 432 was superstar designer Fred Pollack who became the lead architect for the Pentium Pro. |df=dmy-all}}</ref>

<ref name="Stiller_1996">{{cite magazine |last1=Stiller |first1=Andreas |last2=Paul |first2=Matthias R. <!-- contributor on processor internals --> |date=May 12, 1996 |title=Trends & News {{!}} Prozessorgeflüster |trans-title=Trends & News {{!}} Processor whisper |url=https://www.heise.de/blog/Prozessorgefluester-284546.html <!-- old url https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html --> |url-access=subscription |url-status=live |magazine=[[c't|c't {{!}} magazin für computertechnik]] |language=de |publisher=[[Heinz Heise]] |issn=0724-8679 |oclc=314471122 |archive-url=https://web.archive.org/web/20221228162604/https://www.heise.de/blog/Prozessorgefluester-284546.html <!-- old url https://web.archive.org/web/20170828172141/https://www.heise.de/ct/artikel/Prozessorgefluester-284546.html -->| archive-date=December 28, 2022 |access-date=December 28, 2022 |quote=Offenbar hat der PPro einen ladbaren Microcode, für den das Board-BIOS zwei Funktionen im Interrupt 15h zum Auslesen und Laden bereithält (näheres im nächsten Update der Interrupt-Liste). Gedacht ist das für Patches, doch wer weiß, welch ungeahnte Möglichkeiten noch darinstecken. Somit hat man es beim PPro in Zukunft nicht nur mit zwei Masken-Versionen (für CPU und Cache), sondern auch noch mit der Update-Version des Microcode-BIOS zu tun (zum Beispiel beim aktuellen 200-MHz-'P6S' mit der Kennung SY013: CPU-Step A0, Cache-Step B1, BIOS: sA0C05). |trans-quote=Apparently the PPro has a loadable microcode, for which the board BIOS provides two functions in interrupt 15h for reading and loading (more information in the next update of the interrupt list). This is intended for patches, but who knows what undreamt-of possibilities are still there. In the future, therefore, the PPro will not only have to deal with two mask versions (for CPU and cache), but also with the update version of the microcode BIOS (e.g. with the current 200 MHz 'P6S' with the Identifier SY013: CPU step A0, cache step B1, BIOS: sA0C05). |df=dmy-all }}</ref>

<ref name="Stokes_20060405">{{cite news |last1=Stokes |first1=Jon |date=April 5, 2006 |title=Into the Core: Intel's next-generation microarchitecture |url=https://arstechnica.com/gadgets/2006/04/core/ |url-status=live |department=Tech |work=[[Ars Technica]] |language=en-us |oclc=52157687 |archive-url=https://web.archive.org/web/20221218114751/https://arstechnica.com/gadgets/2006/04/core/ |archive-date=December 18, 2022 |access-date=December 28, 2022 |quote=The P6 lineage from the Pentium Pro to the Pentium M [...] One of the most distinctive features of the P6 line is its issue port structure. (Intel calls these "dispatch ports," but for the sake of consistency with the rest of my work I'll be using the terms "dispatch" and "issue" differently than Intel.) Core uses a similar structure in its execution core, although there are some major differences between Core's issue port and RS combination and that of the P6. |df=dmy-all }}</ref>

<ref name="MPR 1995-11-13">{{cite magazine |last1=Slater |first1=Michael |date=November 13, 1995 |title=Intel Boosts Pentium Pro to 200 MHz |url=https://www.ardent-tool.com/CPU/docs/MPR/091501.pdf |magazine=[[Microprocessor Report]] |volume=9 |number=15 |series=MicroDesign Resources |archive-url=https://web.archive.org/web/20211202223030/https://www.ardent-tool.com/CPU/docs/MPR/091501.pdf |access-date=December 28, 2022 |archive-date=December 2, 2021 |url-status=live |quote=Integer Leads, FP Lags RISC Chips |via=Ardent Tool of Capitalism (ardent-tool.com) |df=dmy-all }}</ref>

}}

==External links==
* [http://searchstorage.techtarget.com/sDefinition/0,,sid5_gci213804,00.html Backside Bus] {{Webarchive|url=https://web.archive.org/web/20060411203823/http://searchstorage.techtarget.com/sDefinition/0%2C%2Csid5_gci213804%2C00.html |date=April 11, 2006 }}, searchstorage.techtarget.com
* [http://www.cpu-collection.de/?tn=0&l0=co&l1=Intel&l2=Pentium%20Pro Intel Pentium Pro images and descriptions], cpu-collection.de
* [https://web.archive.org/web/20071012181825/http://cpu-info.com/index2.php?mainid=html%2Fcpu%2FiPPro.php CPU-INFO: Intel Pentium Pro, indepth processor history], web.archive.org

{{Intel processors|p6}}

[[Category:Computer-related introductions in 1995]]
[[Category:Intel x86 microprocessors]]
[[Category:Superscalar microprocessors]]
[[Category:32-bit microprocessors]]