View source for Side-channel attack

{{short description|Any attack based on information gained from the implementation of a computer system}}
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[[File:Power attack.png|thumb|An attempt to decode [[RSA (algorithm)|RSA]] key bits using [[power analysis]]. The left pulse represents the CPU power variations during the step of the [[Exponentiation by squaring|algorithm]] without multiplication, the broader right pulse – step with multiplication, allowing an attacker to read bits 0, 1.]]

In [[computer security]], a '''side-channel attack''' is a type of security exploit that leverages information inadvertently leaked by a system—such as timing, power consumption, or electromagnetic or acoustic emissions—to gain unauthorized access to sensitive information. These attacks differ from those targeting flaws in the design of [[cryptography|cryptographic]] [[computer protocol|protocols]] or [[algorithm|algorithms]] (notwithstanding the fact that [[cryptanalysis]] may identify vulnerabilities relevant to both types of attacks).

Some side-channel attacks require technical knowledge of the internal operation of the system, others such as [[differential power analysis]] are effective as [[Black-box testing|black-box]] attacks. The rise of [[Web 2.0]] applications and [[software-as-a-service]] has also significantly raised the possibility of side-channel attacks on the web, even when transmissions between a web browser and server are encrypted (e.g. through [[HTTPS]] or [[WiFi]] encryption), according to researchers from [[Microsoft Research]] and [[Indiana University]].<ref>{{cite journal|url=http://research.microsoft.com/pubs/119060/WebAppSideChannel-final.pdf|title=Side-Channel Leaks in Web Applications: a Reality Today, a Challenge Tomorrow|journal=Microsoft Research|publisher=IEEE Symposium on Security & Privacy 2010|date=May 2010|author1=Shuo Chen|author2=Rui Wang|author3=XiaoFeng Wang|author4=Kehuan Zhang|name-list-style=amp|access-date=2011-12-16|archive-date=2016-06-17|archive-url=https://web.archive.org/web/20160617004603/http://research.microsoft.com/pubs/119060/WebAppSideChannel-final.pdf|url-status=live}}</ref> 

Attempts to break a cryptosystem by deceiving or coercing people with legitimate access are not typically considered side-channel attacks: see [[social engineering (security)|social engineering]] and [[rubber-hose cryptanalysis]].
 
General classes of side-channel attack include:

* [[Cache timing attack|Cache attack]]&nbsp;&ndash; attacks based on attacker's ability to monitor [[Cache (computing)|cache]] accesses made by the victim in a shared physical system as in virtualized environment or a type of cloud service.
* [[Timing attack]]&nbsp;&ndash; attacks based on measuring how much time various computations (such as, say, comparing an attacker's given password with the victim's unknown one) take to perform.
* [[Power analysis|Power-monitoring attack]]&nbsp;&ndash; attacks that make use of varying power consumption by the hardware during computation.
* [[Electromagnetic attack]]&nbsp;&ndash; attacks based on leaked electromagnetic radiation, which can directly provide plaintexts and other information.  Such measurements can be used to infer cryptographic keys using techniques equivalent to those in power analysis or can be used in non-cryptographic attacks, e.g. [[Tempest (codename)|TEMPEST]] (aka [[van Eck phreaking]] or radiation monitoring) attacks.
* [[Acoustic cryptanalysis]]&nbsp;&ndash; attacks that exploit sound produced during a computation (rather like power analysis).
* [[Differential fault analysis]]&nbsp;&ndash; in which secrets are discovered by introducing faults in a computation.
* [[Data remanence]]&nbsp;&ndash; in which sensitive data are read after supposedly having been deleted. (e.g. [[Cold boot attack]])
* Software-initiated fault attacks&nbsp;&ndash; Currently a rare class of side channels, [[Row hammer]] is an example in which off-limits memory can be changed by accessing adjacent memory too often (causing state retention loss).
* [[Whitelist]]&nbsp;&ndash; attacks based on the fact that the whitelisting devices will behave differently when communicating with whitelisted (sending back the responses) and non-whitelisted (not responding to the devices at all) devices. Whitelist-based side channel may be used to track Bluetooth MAC addresses.
* Optical&nbsp;&ndash; in which secrets and sensitive data can be read by visual recording using a high resolution camera, or other devices that have such capabilities (see examples below).

In all cases, the underlying principle is that physical effects caused by the operation of a [[cryptosystem]] (''on the side'') can provide useful extra information about secrets in the system, for example, the [[cryptographic key]], partial state information, full or partial [[plaintext]]s and so forth. The term cryptophthora (secret degradation) is sometimes used to express the degradation of secret key material resulting from side-channel leakage.

==Examples==
A '''{{visible anchor|cache side-channel attack}}''' works by monitoring security critical operations such as [[Advanced Encryption Standard|AES]] T-table entry<ref>{{cite book | chapter=Highly Efficient Algorithms for AES Key Retrieval in Cache Access Attacks | year=2016 | author1=Ashokkumar C. | title=2016 IEEE European Symposium on Security and Privacy (EuroS&P) | pages=261–275 | author2=Ravi Prakash Giri | author3=Bernard Menezes| doi=10.1109/EuroSP.2016.29 | isbn=978-1-5090-1751-5 | s2cid=11251391 }}</ref><ref>{{citation |url=http://eprint.iacr.org/2014/435.pdf |title=Wait a minute! A fast, Cross-VM attack on AES |author1=Gorka Irazoqui |author2=Mehmet Sinan Inci |author3=Thomas Eisenbarth |author4=Berk Sunar |access-date=2018-01-07 |archive-date=2017-08-11 |archive-url=https://web.archive.org/web/20170811001129/https://eprint.iacr.org/2014/435.pdf |url-status=live }}</ref><ref>{{citation |url=http://eprint.iacr.org/2013/448.pdf |title=Flush+Reload: a High Resolution, Low Noise, L3 Cache Side-Channel Attack |author1=Yuval Yarom |author2=Katrina Falkner |access-date=2018-01-07 |archive-date=2017-07-05 |archive-url=https://web.archive.org/web/20170705164835/http://eprint.iacr.org/2013/448.pdf |url-status=live }}</ref> or modular exponentiation or multiplication or memory accesses.<ref>{{citation |url=http://eprint.iacr.org/2016/596.pdf |title=Cache Attacks Enable Bulk Key Recovery on the Cloud |author1=Mehmet S. Inci |author2=Berk Gulmezoglu |author3=Gorka Irazoqui |author4=Thomas Eisenbarth |author5=Berk Sunar |access-date=2018-01-07 |archive-date=2016-07-17 |archive-url=https://web.archive.org/web/20160717084327/http://eprint.iacr.org/2016/596.pdf |url-status=live }}</ref> The attacker then is able to recover the secret key depending on the accesses made (or not made) by the victim, deducing the encryption key. Also, unlike some of the other side-channel attacks, this method does not create a fault in the ongoing cryptographic operation and is invisible to the victim.

In 2017, two [[Central processing unit|CPU]] vulnerabilities (dubbed [[Meltdown (security vulnerability)|Meltdown]] and [[Spectre (security vulnerability)|Spectre]]) were discovered, which can use a cache-based side channel to allow an attacker to leak memory contents of other processes and the operating system itself.

''[[Timing attack]]s'' monitor data movement into and out of the CPU or memory on the hardware running the cryptosystem or algorithm. Simply by observing variations in how long it takes to perform cryptographic operations, it might be possible to determine the entire secret key.<ref name=":0" /> Such attacks involve statistical analysis of timing measurements and have even been demonstrated across networks.<ref name=":1">{{cite web|url=http://crypto.stanford.edu/~dabo/papers/ssl-timing.pdf|title=Remote timing attacks are practical|author1=David Brumley|author2=Dan Boneh|year=2003|access-date=2010-11-05|archive-date=2011-07-28|archive-url=https://web.archive.org/web/20110728122336/http://crypto.stanford.edu/~dabo/papers/ssl-timing.pdf|url-status=live}}</ref>

A ''[[power-analysis]]'' attack can provide even more detailed information by observing the power consumption of a hardware device such as CPU or cryptographic circuit.  These attacks are roughly categorized into simple power analysis (SPA) and differential power analysis (DPA). One example is Collide+Power, which affects nearly all CPUs.<ref>{{Cite web |last=Kovacs |first=Eduard |date=2023-08-01 |title=Nearly All Modern CPUs Leak Data to New Collide+Power Side-Channel Attack |url=https://www.securityweek.com/nearly-all-modern-cpus-leak-data-to-new-collidepower-side-channel-attack/ |access-date=2023-08-02 |website=SecurityWeek |language=en-US |archive-date=2024-07-11 |archive-url=https://web.archive.org/web/20240711072553/https://www.securityweek.com/nearly-all-modern-cpus-leak-data-to-new-collidepower-side-channel-attack/ |url-status=live }}</ref><ref name=":3">{{Cite web |last=Claburn |first=Thomas |title=Another CPU data-leak flaw found. Luckily, it's impractical |url=https://www.theregister.com/2023/08/01/collide_power_cpu_attack/ |access-date=2023-08-02 |website=www.theregister.com |language=en}}</ref><ref>{{Citation |title=Collide+Power |date=2023-08-01 |url=https://github.com/IAIK/CollidePower |access-date=2023-08-02 |publisher=Institute of Applied Information Processing and Communications (IAIK) |archive-date=2023-08-01 |archive-url=https://web.archive.org/web/20230801200906/https://github.com/iaik/CollidePower |url-status=live }}</ref> Other examples use [[machine learning]] approaches.<ref>{{cite journal |last1=Lerman |first1=Liran |last2=Bontempi |first2=Gianluca |last3=Markowitch |first3=Olivier |title=Power analysis attack: an approach based on machine learning |journal=International Journal of Applied Cryptography |date=1 January 2014 |volume=3 |issue=2 |pages=97–115 |doi=10.1504/IJACT.2014.062722 |url=https://www.inderscienceonline.com/doi/abs/10.1504/IJACT.2014.062722 |issn=1753-0563 |access-date=25 September 2020 |archive-date=25 January 2021 |archive-url=https://web.archive.org/web/20210125184717/https://www.inderscienceonline.com/doi/abs/10.1504/IJACT.2014.062722 |url-status=live |url-access=subscription }}</ref>

Fluctuations in current also generate [[electromagnetic radiation|radio waves]], enabling attacks that analyze measurements of electromagnetic (EM) emanations.  These attacks typically involve similar statistical techniques as power-analysis attacks.

A ''deep-learning-based side-channel attack'',<ref>{{cite journal |last1=Timon |first1=Benjamin |date=2019-02-28 |title=Non-Profiled Deep Learning-based Side-Channel attacks with Sensitivity Analysis |url=https://tches.iacr.org/index.php/TCHES/article/view/7387 |journal=IACR Transactions on Cryptographic Hardware and Embedded Systems |volume= |issn=2569-2925 |pages=107–131 |doi=10.13154/tches.v2019.i2.107-131 |s2cid=4052139 |access-date=2021-11-19 |archive-date=2021-11-12 |archive-url=https://web.archive.org/web/20211112113503/https://tches.iacr.org/index.php/TCHES/article/view/7387 |url-status=live }}</ref><ref>{{cite web | url=https://ieeexplore.ieee.org/document/8806883 | title=X-DeepSCA: Cross-Device Deep Learning Side Channel Attack | date=June 2019 | pages=1–6 }}</ref><ref>{{cite journal | doi=10.1109/TVLSI.2019.2926324 | title=Practical Approaches Toward Deep-Learning-Based Cross-Device Power Side-Channel Attack | date=2019 | last1=Golder | first1=Anupam | last2=Das | first2=Debayan | last3=Danial | first3=Josef | last4=Ghosh | first4=Santosh | last5=Sen | first5=Shreyas | last6=Raychowdhury | first6=Arijit | journal=IEEE Transactions on Very Large Scale Integration (VLSI) Systems | volume=27 | issue=12 | pages=2720–2733 | arxiv=1907.02674 | bibcode=2019ITVL...27.2720G }}</ref> using the power and EM information across multiple devices has been demonstrated with the potential to break the secret key of a different but identical device in as low as a single trace.

Historical analogues to modern side-channel attacks are known.  A recently declassified [[National Security Agency|NSA]] document reveals that as far back as 1943, an engineer with [[Bell Telephone Company|Bell telephone]] observed decipherable spikes on an oscilloscope associated with the decrypted output of a certain encrypting teletype.<ref>{{cite magazine|url=https://www.wired.com/2008/04/nsa-releases-se/|title=Declassified NSA document reveals the secret history of TEMPEST|magazine=Wired|publisher=Wired.com|date=April 29, 2008|access-date=May 2, 2008|archive-date=May 1, 2008|archive-url=https://web.archive.org/web/20080501092403/http://blog.wired.com/27bstroke6/2008/04/nsa-releases-se.html|url-status=live}}</ref> According to former [[MI5]] officer [[Peter Wright (MI5 officer)|Peter Wright]], the British Security Service analyzed emissions from French cipher equipment in the 1960s.<ref>{{Cite web|url=https://www.sans.org/reading-room/whitepapers/privacy/introduction-tempest-981|title=An Introduction to TEMPEST &#124; SANS Institute|access-date=2015-10-06|archive-date=2017-09-05|archive-url=https://web.archive.org/web/20170905172700/https://www.sans.org/reading-room/whitepapers/privacy/introduction-tempest-981|url-status=live}}</ref> In the 1980s, [[KGB|Soviet]] eavesdroppers were suspected of having planted [[Surveillance bug|bugs]] inside IBM [[Selectric]] typewriters to monitor the electrical noise generated as the type ball rotated and pitched to strike the paper; the characteristics of those signals could determine which key was pressed.<ref>{{cite magazine|url=http://www.time.com/time/magazine/article/0,9171,964052-2,00.html|archive-url=https://web.archive.org/web/20110604062749/http://www.time.com/time/magazine/article/0,9171,964052-2,00.html|archive-date=June 4, 2011|title=The Art of High-Tech Snooping|magazine=Time| last= Church |first= George|date=April 20, 1987|access-date=January 21, 2010}}</ref>

Power consumption of devices causes heating, which is offset by cooling effects.  Temperature changes create thermally induced mechanical stress. This stress can create low level [[acoustics|acoustic]] emissions from operating CPUs (about 10&nbsp;kHz in some cases). Recent research by [[Adi Shamir|Shamir]] et al. has suggested that information about the operation of cryptosystems and algorithms can be obtained in this way as well. This is an ''acoustic cryptanalysis attack''.

If the surface of the CPU chip, or in some cases the CPU package, can be observed, [[infrared]] images can also provide information about the code being executed on the CPU, known as a ''thermal-imaging attack''.{{citation needed|date=July 2016}}

An ''optical side-channel attack'' examples include gleaning information from the hard disk activity indicator<ref>{{citation |url=http://www.securityweek.com/hard-drive-led-allows-data-theft-air-gapped-pcs |title=Hard Drive LED Allows Data Theft From Air-Gapped PCs |author=Eduard Kovacs |date=February 23, 2017 |access-date=2018-03-18 |work=Security Week |archive-date=2017-10-07 |archive-url=https://web.archive.org/web/20171007112737/http://www.securityweek.com/hard-drive-led-allows-data-theft-air-gapped-pcs |url-status=live }}</ref> to reading a small number of photons emitted by transistors as they change state.<ref>{{cite journal|url=http://digital-library.theiet.org/content/journals/10.1049/iet-ifs_20080038 |title=When AES blinks: introducing optical side channel |author1=J. Ferrigno |author2=M. Hlaváč |journal=IET Information Security |volume=2 |issue=3 |date=September 2008 |pages=94–98 |doi=10.1049/iet-ifs:20080038 |access-date=2017-03-16 |archive-date=2018-01-11 |archive-url=https://web.archive.org/web/20180111224141/http://digital-library.theiet.org/content/journals/10.1049/iet-ifs_20080038 |url-status=live |url-access=subscription }}</ref>

''Allocation-based side channels'' also exist and refer to the information that leaks from the allocation (as opposed to the use) of a resource such as network bandwidth to clients that are concurrently requesting the contended resource.<ref>{{cite book |url=https://eprint.iacr.org/2020/287.pdf |archive-date=2020-06-24 |archive-url=https://web.archive.org/web/20200624113142/https://eprint.iacr.org/2020/287.pdf |doi=10.1109/SP40000.2020.00065 |chapter=Private resource allocators and their applications |title=2020 IEEE Symposium on Security and Privacy (SP) |date=2020 |last1=Angel |first1=Sebastian |last2=Kannan |first2=Sampath |last3=Ratliff |first3=Zachary |pages=372–391 |isbn=978-1-7281-3497-0 }}</ref>

==Countermeasures==
There are two primary categories of measures to counter side-channel attacks:

# Eliminating or reducing emissions: This involves minimizing the unintended release of signals, such as electromagnetic radiation or timing variations, that attackers could exploit.
# Transforming the secret data: Typically achieved through randomization, this approach ensures:
#* The cryptographic operation does not leak information that could be correlated with the secret data.
#* A subsequent transformation restores the intended result after the cryptographic operation.

Under the first category, displays with special shielding to lessen electromagnetic emissions, reducing susceptibility to [[Tempest (codename)|TEMPEST]] attacks, are now commercially available. Power line conditioning and filtering can help deter power-monitoring attacks, although such measures must be used cautiously, since even very small correlations can remain and compromise security.  Physical enclosures can reduce the risk of surreptitious installation of microphones (to counter acoustic attacks) and other micro-monitoring devices (against CPU power-draw or thermal-imaging attacks).

Another countermeasure (still in the first category) is to jam the emitted channel with noise. For instance, a random delay can be added to deter timing attacks, although adversaries can compensate for these delays by averaging multiple measurements (or, more generally, using more measurements in the analysis). When the amount of noise in the side channel increases, the adversary needs to collect more measurements.

Another countermeasure under the first category is to use security analysis software to identify certain classes of side-channel attacks that can be found during the design stages of the underlying hardware itself. Timing attacks and cache attacks are both identifiable through certain commercially available security analysis software platforms, which allow for testing to identify the attack vulnerability itself, as well as the effectiveness of the architectural change to circumvent the vulnerability. The most comprehensive method to employ this countermeasure is to create a Secure Development Lifecycle for hardware, which includes utilizing all available security analysis platforms at their respective stages of the hardware development lifecycle.<ref>{{cite web|url=http://www.tortugalogic.com/isolation/|title=Identifying Isolation Issues in Modern Microprocessor Architectures|author1=Tortuga Logic|year=2018|access-date=2018-02-23|archive-date=2018-02-24|archive-url=https://web.archive.org/web/20180224113055/http://www.tortugalogic.com/isolation/}}</ref>

In the case of timing attacks against targets whose computation times are quantized into discrete clock cycle counts, an effective countermeasure against is to design the software to be isochronous, that is to run in an exactly constant amount of time, independently of secret values.  This makes timing attacks impossible.<ref name="Spadavecchia" >[http://www.era.lib.ed.ac.uk/bitstream/1842/860/1/Spadavecchia_thesis.pdf "A Network-based Asynchronous Architecture for Cryptographic Devices"] {{Webarchive|url=https://web.archive.org/web/20110929081236/http://www.era.lib.ed.ac.uk/bitstream/1842/860/1/Spadavecchia_thesis.pdf |date=2011-09-29 }}
by Ljiljana Spadavecchia
2005
in sections "3.2.3 Countermeasures", "3.4.2 Countermeasures",
"3.5.6 Countermeasures", "3.5.7 Software countermeasures",
"3.5.8 Hardware countermeasures", and "4.10 Side-channel analysis of asynchronous architectures".</ref>  Such countermeasures can be difficult to implement in practice, since even individual instructions can have variable timing on some CPUs.

One partial countermeasure against simple power attacks, but not differential power-analysis attacks, is to design the software so that it is "PC-secure" in the "program counter security model". In a PC-secure program, the execution path does not depend on secret values. In other words, all conditional branches depend only on public information. (This is a more restrictive condition than isochronous code, but a less restrictive condition than branch-free code.) Even though multiply operations draw more power than [[NOP (code)|NOP]] on practically all CPUs, using a constant execution path prevents such operation-dependent power differences (differences in power from choosing one branch over another) from leaking any secret information.<ref name="Spadavecchia"/> On architectures where the instruction execution time is not data-dependent, a PC-secure program is also immune to timing attacks.<ref>[https://www.cs.berkeley.edu/~daw/papers/pcmodel-long.pdf "The Program Counter Security Model: Automatic Detection and Removal of Control-Flow Side Channel Attacks"] {{Webarchive|url=https://web.archive.org/web/20090419094523/http://www.cs.berkeley.edu/~daw/papers/pcmodel-long.pdf |date=2009-04-19 }} by David Molnar, Matt Piotrowski, David Schultz, David Wagner (2005).</ref><ref>{{Cite web |url=https://www.usenix.org/legacy/events/sec05/wips/molnar.pdf |title="The Program Counter Security Model: Automatic Detection and Removal of Control-Flow Side Channel Attacks" USENIX Work-in-Progress presentation of paper |access-date=2014-10-04 |archive-date=2017-08-14 |archive-url=https://web.archive.org/web/20170814055923/https://www.usenix.org/legacy/events/sec05/wips/molnar.pdf |url-status=live }}</ref>

Another way in which code can be non-isochronous is that modern CPUs have a memory cache: accessing infrequently used information incurs a large timing penalty, revealing some information about the frequency of use of memory blocks. Cryptographic code designed to resist cache attacks attempts to use memory in only a predictable fashion (like accessing only the input, outputs and program data, and doing so according to a fixed pattern). For example, data-dependent [[lookup table|table lookups]] must be avoided because the cache could reveal which part of the lookup table was accessed.

Other partial countermeasures attempt to reduce the amount of information leaked from data-dependent power differences. Some operations use power that is correlated to the number of 1 bits in a secret value. Using a [[constant-weight code]] (such as using [[Fredkin gate]]s or dual-rail encoding) can reduce the leakage of information about the [[Hamming weight]] of the secret value, although exploitable correlations are likely to remain unless the balancing is perfect.  This "balanced design" can be approximated in software by manipulating both the data and its complement together.<ref name="Spadavecchia" />

Several "secure CPUs" have been built as [[asynchronous circuit#Asynchronous CPU|asynchronous CPU]]s; they have no global timing reference. While these CPUs were intended to make timing and power attacks more difficult,<ref name="Spadavecchia" /> subsequent research found that timing variations in asynchronous circuits are harder to remove.<ref>{{Cite book|last1=Jeong|first1=C.|last2=Nowick|first2=S. M.|title=2007 Asia and South Pacific Design Automation Conference |chapter=Optimization of Robust Asynchronous Circuits by Local Input Completeness Relaxation |date=January 2007|pages=622–627|doi=10.1109/ASPDAC.2007.358055|isbn=978-1-4244-0629-6|s2cid=14219703}}</ref>

A typical example of the second category (decorrelation) is a technique known as ''[[blinding (cryptography)|blinding]]''. In the case of [[RSA (cryptosystem)|RSA]] decryption<ref name=":0">{{Cite book |last=Kocher |first=Paul C. |date=1996 |editor-last=Koblitz |editor-first=Neal |title= Advances in Cryptology — CRYPTO '96|chapter=Timing Attacks on Implementations of Diffie-Hellman, RSA, DSS, and Other Systems |series=Lecture Notes in Computer Science |volume=1109 |chapter-url=https://link.springer.com/chapter/10.1007/3-540-68697-5_9  |language=en |location=Berlin, Heidelberg |publisher=Springer |pages=104–113 |doi=10.1007/3-540-68697-5_9 |isbn=978-3-540-68697-2}}</ref><ref name=":1" /> with secret exponent <math>d</math> and corresponding encryption exponent <math>e</math> and modulus <math>m</math>, the technique applies as follows (for simplicity, the modular reduction by ''m'' is omitted in the formulas): before decrypting, that is, before computing the result of <math>y^d</math> for a given ciphertext <math>y</math>, the system picks a random number <math>r</math> and encrypts it with public exponent <math>e</math> to obtain <math>r^e</math>. Then, the decryption is done on <math>y \cdot r^e</math> to 
obtain <math>{(y \cdot r^e)}^d = y^d \cdot r^{e\cdot d} = y^d \cdot r</math>. Since the decrypting system chose <math>r</math>, it can compute its inverse modulo <math>m</math> to cancel out the factor <math>r</math> in the result and obtain <math>y^d</math>, the actual result of the decryption. For attacks that require collecting side-channel information from operations with data ''controlled by the attacker'', blinding is an effective countermeasure, since the actual operation is executed on a randomized version of the data, over which the attacker has no control or even knowledge.

As a countermeasure for message encryption, ''masking'' is effective against all side-channel attacks. The principle of masking is to avoid manipulating any sensitive value <math>y</math> directly, but rather manipulate a sharing of it: a set of variables (called "shares") <math>y_1, ..., y_d</math> such that <math>y = y_1 \oplus ... \oplus y_d</math> (where <math>\oplus</math> is the [[XOR gate|XOR]] operation). An attacker must recover all the values of the shares to get any meaningful information.<ref>{{cite book |doi=10.1007/978-3-642-38348-9_9 |url=https://www.iacr.org/archive/eurocrypt2013/78810139/78810139.pdf |archive-url=https://web.archive.org/web/20170811210617/https://www.iacr.org/archive/eurocrypt2013/78810139/78810139.pdf|archive-date=11 August 2017 |chapter=Masking against Side-Channel Attacks: A Formal Security Proof |title=Advances in Cryptology – EUROCRYPT 2013 |series=Lecture Notes in Computer Science |date=2013 |last1=Prouff |first1=Emmanuel |last2=Rivain |first2=Matthieu |volume=7881 |pages=142–159 |isbn=978-3-642-38347-2 }}</ref>

Recently, white-box modeling was utilized to develop a low-overhead generic circuit-level countermeasure<ref>{{cite book | doi=10.1109/ISSCC19947.2020.9062997 | chapter=27.3 EM and Power SCA-Resilient AES-256 in 65nm CMOS Through >350× Current-Domain Signature Attenuation | title=2020 IEEE International Solid- State Circuits Conference – (ISSCC) | date=2020 | last1=Das | first1=Debayan | last2=Danial | first2=Josef | last3=Golder | first3=Anupam | last4=Modak | first4=Nirmoy | last5=Maity | first5=Shovan | last6=Chatterjee | first6=Baibhab | last7=Seo | first7=Donghyun | last8=Chang | first8=Muya | last9=Varna | first9=Avinash | last10=Krishnamurthy | first10=Harish | last11=Mathew | first11=Sanu | last12=Ghosh | first12=Santosh | last13=Raychowdhury | first13=Arijit | last14=Sen | first14=Shreyas | pages=424–426 | isbn=978-1-7281-3205-1 }}</ref> against both EM as well as power side-channel attacks. To minimize the effects of the higher-level metal layers in an IC acting as more efficient antennas,<ref>{{cite book | doi=10.1109/HST.2019.8740839 | chapter=STELLAR: A Generic EM Side-Channel Attack Protection through Ground-Up Root-cause Analysis | title=2019 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) | date=2019 | last1=Das | first1=Debayan | last2=Nath | first2=Mayukh | last3=Chatterjee | first3=Baibhab | last4=Ghosh | first4=Santosh | last5=Sen | first5=Shreyas | pages=11–20 | isbn=978-1-5386-8064-3 }}</ref> the idea is to embed the crypto core with a signature suppression circuit,<ref>{{cite journal | doi=10.1109/TCSI.2018.2819499 | title=ASNI: Attenuated Signature Noise Injection for Low-Overhead Power Side-Channel Attack Immunity | date=2018 | last1=Das | first1=Debayan | last2=Maity | first2=Shovan | last3=Nasir | first3=Saad Bin | last4=Ghosh | first4=Santosh | last5=Raychowdhury | first5=Arijit | last6=Sen | first6=Shreyas | journal=IEEE Transactions on Circuits and Systems I: Regular Papers | volume=65 | issue=10 | pages=3300–3311 | bibcode=2018ITCSR..65.3300D }}</ref><ref>{{cite book | doi=10.1109/HST.2017.7951799 | chapter=High efficiency power side-channel attack immunity using noise injection in attenuated signature domain | title=2017 IEEE International Symposium on Hardware Oriented Security and Trust (HOST) | date=2017 | last1=Das | first1=Debayan | last2=Maity | first2=Shovan | last3=Nasir | first3=Saad Bin | last4=Ghosh | first4=Santosh | last5=Raychowdhury | first5=Arijit | last6=Sen | first6=Shreyas | pages=62–67 | arxiv=1703.10328 | isbn=978-1-5386-3929-0 }}</ref> routed locally within the lower-level metal layers, leading towards both power and EM side-channel attack immunity.

==See also==
* [[Brute-force attack]]
* [[Computer and network surveillance]]
* [[Covert channel]]
* [[Side effect (computer science)|Side effect]]
* [[Wire data]]

==References==
{{reflist}}

==Further reading==
===Books===
* {{cite book|author=Ambrose, Jude|title=Power Analysis Side Channel Attacks: The Processor Design-level Context|publisher=VDM Verlag|year=2010|isbn=978-3-8364-8508-1|url=https://books.google.com/books?id=n9wsQwAACAAJ|display-authors=etal}}

* {{cite book|author=Mangard, Stefan|title=Power Analysis Attacks: Revealing the Secrets of Smart Cards|publisher=Springer Verlag|year=2007|isbn=978-0-387-38162-6|url=https://link.springer.com/book/10.1007/978-0-387-38162-6|display-authors=etal |doi=10.1007/978-0-387-38162-6 }}

===Articles===
* [http://www.rambus.com/differential-power-analysis/ Differential Power Analysis], P. Kocher, J. Jaffe, B. Jun, appeared in CRYPTO'99.
* [https://www.researchgate.net/publication/269463480_Side_channel_attack_An_approach_based_on_machine_learning Side channel attack: an approach based on machine learning], 2011, L Lerman, G Bontempi, O Markowitch.
* [http://www.rambus.com/introduction-to-differential-power-analysis-and-related-attacks/ Introduction to Differential Power Analysis and Related attacks], 1998, P Kocher, J Jaffe, B Jun.
* [https://web.archive.org/web/20000816072517/http://csrc.nist.gov/encryption/aes/round1/conf2/papers/chari.pdf Nist.gov], a cautionary Note Regarding Evaluation of AES Candidates on Smart Cards, 1999, S Chari, C Jutla, J R Rao, P Rohatgi
* DES and Differential Power Analysis, L Goubin and  J Patarin, in Proceedings of CHES'99, Lecture Notes in Computer Science Nr 1717, Springer-Verlag
* {{cite book|author=Grabher, Philipp|chapter=Cryptographic Side-Channels from Low-power Cache Memory|editor=Galbraith, Steven D.|title=Cryptography and coding: 11th IMA International Conference, Cirencester, UK, December 18-20, 2007: proceedings, Volume 11|publisher=Springer|year=2007|isbn=978-3-540-77271-2|chapter-url=https://books.google.com/books?id=V0L2Ki72osoC&pg=PA170|display-authors=etal}}
*{{cite journal |first1=Abdel Alim |last1=Kamal |first2=Amr M. |last2=Youssef |title=Fault analysis of the NTRUSign digital signature scheme |journal=Cryptography and Communications |volume=4 |issue=2 |pages=131–144 |year=2012 |doi=10.1007/s12095-011-0061-3 |s2cid=2901175 }}
* {{cite web |url=http://www.tau.ac.il/~tromer/acoustic/ |title=RSA Key Extraction via Low-Bandwidth Acoustic Cryptanalysis |author1=Daniel Genkin |author2=Adi Shamir |author3=Eran Tromer |date=December 18, 2013 |website=[[Tel Aviv University]] |access-date=October 15, 2014}}

==External links==
* Sima, Mihai; Brisson, André  (2015), [http://www.wnlabs.com/pdf/WN_Paper_2015_DRAFT.pdf Whitenoise Encryption Implementation with Increased Robustness against Side-Channel Attacks]
* Brisson, André  (2015),[http://www.wnlabs.com/technology/SideChannelAttackResearch.php University of Victoria, British Columbia Side Channel Attack Resistance study of Whitenoise]
* [http://www.scientificamerican.com/article.cfm?id=hackers-can-steal-from-reflections New side channel attack techniques]
* [http://cosade.org/ COSADE Workshop] International Workshop on Constructive Side-Channel Analysis and Secure Design

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