View source for X86-64

{{Short description|64-bit version of x86 architecture}}
{{Redirect|Intel 64|the Intel 64-bit architecture in Itanium chips|IA-64}}
{{Redirect|x64|the New York City bus route|X64 (New York City bus)}}
{{Use mdy dates|date=October 2018}}
{{Lowercase title}}
[[File:AMD Opteron 146 Venus, 2005.jpg|thumb|[[AMD]] [[Opteron]], the first CPU to introduce the x86-64 extensions in April 2003]]
[[File:AMD_x86-64_Architecture_Programmers_Manuals.jpg|thumb|right|The five-volume set of the ''x86-64 Architecture Programmer's Manual'', as published and distributed by AMD in 2002]]

'''x86-64''' (also known as '''x64''', '''x86_64''', '''AMD64''', and '''Intel 64'''){{#tag:ref|Various names are used for the instruction set. Prior to the launch, x86-64 and x86_64 were used, while upon the release AMD named it AMD64.<ref name="inq-amd64">{{cite web|title = Debian AMD64 FAQ|url = http://wiki.debian.org/DebianAMD64Faq|work = Debian Wiki|access-date = May 3, 2012|archive-date = September 26, 2019|archive-url = https://web.archive.org/web/20190926163758/https://wiki.debian.org/DebianAMD64Faq|url-status = live}}</ref> Intel initially used the names '''IA-32e''' and '''EM64T''' before finally settling on "Intel 64" for its implementation. Some in the industry, including [[Apple Inc.|Apple]],<ref name="apple-x86-64">{{cite web|title = x86-64 Code Model|url = https://developer.apple.com/library/mac/#documentation/developertools/Conceptual/MachOTopics/1-Articles/x86_64_code.html|publisher= Apple|access-date = November 23, 2012|archive-date = June 2, 2012|archive-url = https://web.archive.org/web/20120602013413/https://developer.apple.com/library/mac/#documentation/developertools/Conceptual/MachOTopics/1-Articles/x86_64_code.html|url-status = live}}</ref><ref name="apple-x86_64-arch-manpage">{{man|1|arch|Darwin}}</ref><ref name="apple-x86_64-email">{{cite web|url = http://lists.apple.com/archives/Darwin-dev/2006/Aug/msg00095.html|title = re: Intel XNU bug report|access-date = October 5, 2006|author = Kevin Van Vechten|date = August 9, 2006|work = Darwin-dev mailing list|publisher = [[Apple Computer]]|quote = The kernel and developer tools have standardized on "x86_64" for the name of the Mach-O architecture|archive-date = February 1, 2020|archive-url = https://web.archive.org/web/20200201090447/https://lists.apple.com/archives/Darwin-dev/2006/Aug/msg00095.html|url-status = dead}}</ref> use x86-64 and x86_64, while others, notably [[Sun Microsystems]]<ref name="solaris-x64">{{cite web|title = Solaris 10 on AMD Opteron|url = http://www.oracle.com/technetwork/server-storage/solaris/overview/solaris10amdopteron-jsp-140575.html|publisher = Oracle|access-date = December 9, 2010|archive-date = July 25, 2017|archive-url = https://web.archive.org/web/20170725114435/http://www.oracle.com/technetwork/server-storage/solaris/overview/solaris10amdopteron-jsp-140575.html|url-status = live}}</ref> (now [[Oracle Corporation]]) and [[Microsoft]],<ref name="ms-x64">{{cite web|title = Microsoft 64-Bit Computing|url = http://www.microsoft.com/windowsserver2008/en/us/64bit-computing.aspx|publisher = Microsoft|access-date = December 9, 2010|archive-url = https://web.archive.org/web/20101212040212/http://www.microsoft.com/windowsserver2008/en/us/64bit-computing.aspx|archive-date = December 12, 2010|url-status = dead|df = mdy-all}}</ref> use x64. The [[BSD]] family of OSs and several [[Linux distribution]]s<ref>{{cite web|title = AMD64 Port|url = http://www.debian.org/ports/amd64/|publisher = Debian|access-date = November 23, 2012|archive-date = September 26, 2019|archive-url = https://web.archive.org/web/20190926060654/https://www.debian.org/ports/amd64/|url-status = live}}</ref><ref>{{cite web|title = Gentoo/AMD64 Project|url = http://www.gentoo.org/proj/en/base/amd64/|publisher = Gentoo Project|access-date = May 27, 2013|archive-date = June 3, 2013|archive-url = https://web.archive.org/web/20130603152916/http://www.gentoo.org/proj/en/base/amd64/|url-status = live}}</ref> use AMD64, as does Microsoft Windows internally.<ref>{{cite web|url=https://msdn.microsoft.com/en-us/library/windows/desktop/aa384274(v=vs.85).aspx|title=WOW64 Implementation Details|access-date=January 24, 2016|archive-date=April 13, 2018|archive-url=https://web.archive.org/web/20180413001932/https://msdn.microsoft.com/en-us/library/windows/desktop/aa384274(v=vs.85).aspx|url-status=live}}</ref><ref>{{cite web|url=https://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture.aspx|title=ProcessorArchitecture Class|access-date=January 24, 2016|archive-date=June 3, 2017|archive-url=https://web.archive.org/web/20170603232543/https://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture.aspx|url-status=live}}</ref>|group=note}} is a [[64-bit]] extension of the [[x86]] [[instruction set architecture|instruction set.]] It was announced in 1999 and first available in the [[AMD Opteron]] family in 2003. It introduces two new operating modes: 64-bit mode and compatibility mode, along with a new four-level [[paging]] mechanism.

In 64-bit mode, x86-64 supports significantly larger amounts of [[virtual memory]] and [[physical memory]] compared to its [[32-bit computing|32-bit]] predecessors, allowing programs to utilize more memory for data storage. The architecture expands the number of [[general-purpose register]]s from 8 to 16, all fully general-purpose, and extends their width to 64 bits.

[[Floating-point arithmetic]] is supported through mandatory [[SSE2]] instructions in 64-bit mode. While the older [[x87]] FPU and MMX registers are still available, they are generally superseded by a set of sixteen 128-bit [[Processor register|vector registers]] (XMM registers). Each of these vector registers can store one or two [[Double-precision floating-point format|double-precision floating-point numbers]], up to four [[Single-precision floating-point format|single-precision]] floating-point numbers, or various integer formats.

In 64-bit mode, instructions are modified to support 64-bit [[operands]] and 64-bit [[addressing mode]].

The x86-64 architecture defines a compatibility mode that allows 16-bit and 32-bit [[user space|user applications]] to run unmodified alongside 64-bit applications, provided the 64-bit operating system supports them.<ref name="amd-24593">{{cite web|url = http://support.amd.com/TechDocs/24593.pdf|title = Volume 2: System Programming|author = AMD Corporation|date = December 2016|work = AMD64 Architecture Programmer's Manual|publisher = AMD Corporation|access-date = March 25, 2017|archive-date = July 13, 2018|archive-url = https://web.archive.org/web/20180713145424/https://support.amd.com/TechDocs/24593.pdf|url-status = live}}</ref>{{refn|group=note|In practice, 64-bit operating systems generally do not support 16-bit applications, although modern versions of Microsoft Windows contain a limited workaround that effectively supports 16-bit [[InstallShield]] and Microsoft ACME installers by silently substituting them with 32-bit code.<ref>{{cite web|url=https://devblogs.microsoft.com/oldnewthing/20131031-00/?p=2783|title=If there is no 16-bit emulation layer in 64-bit Windows, how come certain 16-bit installers are allowed to run?|author=Raymond Chen|date=October 31, 2013|access-date=July 14, 2021|archive-date=July 14, 2021|archive-url=https://web.archive.org/web/20210714084610/https://devblogs.microsoft.com/oldnewthing/20131031-00/?p=2783|url-status=live}}</ref>}} Since the full x86-32 instruction sets remain implemented in hardware without the need for emulation, these older [[executable]]s can run with little or no performance penalty,<ref name="x86-compat-perf">{{cite web|url = https://public.dhe.ibm.com/software/webserver/appserv/was/64bitPerf.pdf|title = IBM WebSphere Application Server 64-bit Performance Demystified|page = 14|quote = "Figures 5, 6 and 7 also show the 32-bit version of WAS runs applications at full native hardware performance on the POWER and x86-64 platforms. Unlike some 64-bit processor architectures, the POWER and x86-64 hardware does not emulate 32-bit mode. Therefore applications that do not benefit from 64-bit features can run with full performance on the 32-bit version of WebSphere running on the above mentioned 64-bit platforms."|publisher = IBM Corporation|date = September 6, 2007|access-date = April 9, 2010|archive-date = January 25, 2022|archive-url = https://web.archive.org/web/20220125121650/ftp://ftp.software.ibm.com/software/webserver/appserv/was/64bitPerf.pdf|url-status = live}}</ref> while newer or modified applications can take advantage of new features of the processor design to achieve performance improvements. Also, processors supporting x86-64 still power on in [[real mode]] to maintain [[backward compatibility]] with the original [[Intel 8086|8086 processor]], as has been the case with x86 processors since the introduction of [[protected mode]] with the [[Intel 80286|80286]].

The original specification, created by [[AMD]] and released in 2000, has been implemented by AMD, [[Intel Corporation|Intel]], and [[VIA Technologies|VIA]]. The [[AMD K8]] [[microarchitecture]], in the [[Opteron]] and [[Athlon 64]] processors, was the first to implement it. This was the first significant addition to the [[x86]] architecture designed by a company other than Intel. Intel was forced to follow suit and introduced a modified [[NetBurst]] family which was software-compatible with AMD's specification. [[VIA Technologies]] introduced x86-64 in their VIA Isaiah architecture, with the [[VIA Nano]].

The x86-64 architecture was quickly adopted for desktop and laptop personal computers and servers which were commonly configured for 16&nbsp;GiB ([[gibibyte]]s) of memory or more. It has effectively replaced the discontinued Intel [[Itanium]] architecture (formerly [[IA-64]]), which was originally intended to replace the x86 architecture. x86-64 and Itanium are not compatible on the native instruction set level, and operating systems and applications compiled for one architecture cannot be run on the other natively.

== AMD64 ==
[[File:AMD64 Logo.svg|thumb|upright=0.5|AMD64 logo]]

=== History ===
AMD64 (also variously referred to by [[AMD]] in their literature and documentation as "AMD 64-bit Technology" and "AMD x86-64 Architecture") was created as an alternative to the radically different [[IA-64]] architecture designed by [[Intel]] and [[Hewlett-Packard]], which was [[backward compatibility|backward-incompatible]] with [[IA-32]], the 32-bit version of the [[x86]] architecture. AMD originally announced AMD64 in 1999<ref>{{cite press release
| title     = AMD Discloses New Technologies At Microporcessor Forum
| publisher = AMD
| date      = October 5, 1999
| url       = https://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx
| archive-url = https://web.archive.org/web/20120308030806/http://www.amd.com/us/press-releases/Pages/Press_Release_751.aspx
| archive-date = March 8, 2012
| access-date= November 9, 2010
}}</ref> with a full specification available in August 2000.<ref>{{cite press release
 | title     = AMD Releases x86-64 Architectural Specification; Enables Market Driven Migration to 64-Bit Computing
 | publisher = AMD
 | date      = August 10, 2000
 | url       = https://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx
 | archive-url = https://web.archive.org/web/20120308025559/http://www.amd.com/us/press-releases/Pages/Press_Release_715.aspx
 | archive-date = March 8, 2012
 | access-date= November 9, 2010
}}</ref> As AMD was never invited to be a contributing party for the IA-64 architecture and any kind of licensing seemed unlikely, the AMD64 architecture was positioned by AMD from the beginning as an evolutionary way to add [[64-bit computing]] capabilities to the existing x86 architecture while supporting legacy 32-bit x86 [[machine code|code]], as opposed to Intel's approach of creating an entirely new, completely x86-incompatible 64-bit architecture with IA-64.

The first AMD64-based processor, the [[Opteron]], was released in April 2003.

=== Implementations ===
AMD's processors implementing the AMD64 architecture include [[Opteron]], [[Athlon 64]], [[Athlon 64 X2]], [[Athlon 64 FX]], [[Athlon II]] (followed by "X2", "X3", or "X4" to indicate the number of cores, and XLT models), [[Turion 64]], [[Turion 64 X2]], [[Sempron]] ("Palermo" E6 stepping and all "Manila" models), [[Phenom (processor)|Phenom]] (followed by "X3" or "X4" to indicate the number of cores), [[Phenom II]] (followed by "X2", "X3", "X4" or "X6" to indicate the number of cores), [[AMD FX|FX]], [[AMD Accelerated Processing Unit|Fusion/APU]] and [[Ryzen]]/[[Epyc]].

=== Architectural features ===
The primary defining characteristic of AMD64 is the availability of 64-bit general-purpose [[processor register]]s (for example, {{mono|rax}}), 64-bit [[Integer (computer science)|integer]] arithmetic and logical operations, and 64-bit [[Protected Virtual Address Mode|virtual addresses]].<ref>{{cite book |url=https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24592.pdf |title=AMD64 Architecture Programmer's Manual |page=1}}</ref> The designers took the opportunity to make other improvements as well.

Notable changes in the 64-bit extensions include:

; 64-bit integer capability
: All [[general-purpose register]]s (GPRs) are expanded from 32&nbsp;[[bit]]s to 64&nbsp;bits, and all arithmetic and logical operations, memory-to-register and register-to-memory operations, etc., can operate directly on 64-bit integers. [[Stack (data structure)|Pushes and pops]] on the [[Stack register|stack]] default to 8-byte strides, and [[pointer (computer programming)|pointers]] are 8 bytes wide.
; Additional registers
: In addition to increasing the size of the general-purpose registers, the number of named general-purpose registers is increased from eight (i.e. {{mono|eax}}, {{mono|ebx}}, {{mono|ecx}}, {{mono|edx}}, {{mono|esi}}, {{mono|edi}}, {{mono|esp}}, {{mono|ebp}}) in x86 to 16 (i.e. {{mono|rax}}, {{mono|rbx}}, {{mono|rcx}}, {{mono|rdx}}, {{mono|rsi}}, {{mono|rdi}}, {{mono|rsp}}, {{mono|rbp}}, {{mono|r8}}, {{mono|r9}}, {{mono|r10}}, {{mono|r11}}, {{mono|r12}}, {{mono|r13}}, {{mono|r14}}, {{mono|r15}}). It is therefore possible to keep more local variables in registers rather than on the stack, and to let registers hold frequently accessed constants; arguments for small and fast subroutines may also be passed in registers to a greater extent.
: AMD64 still has fewer registers than many [[RISC]] [[instruction set]]s (e.g. [[Power ISA]] has 32 GPRs; [[ARM architecture#64/32-bit architecture|64-bit ARM]], [[RISC-V]] I, [[SPARC]], [[DEC Alpha|Alpha]], [[MIPS architecture|MIPS]], and [[PA-RISC]] have 31) or [[VLIW]]-like machines such as the [[IA-64]] (which has 128&nbsp;registers). However, an AMD64 implementation may have far more internal registers than the number of architectural registers exposed by the instruction set (see [[register renaming]]). (For example, AMD Zen cores have 168 64-bit integer and 160 128-bit vector floating-point physical internal registers.)
; Additional XMM (SSE) registers
: Similarly, the number of 128-bit XMM<!-- don't confuse this name with MMX; MMX has no hardware registers and is mapped to the FPU stack. Here we talk about SSE (XMM) registers --> registers (used for [[Streaming SIMD Extensions|Streaming SIMD]] instructions) is also increased from 8 to 16.
: The traditional x87 FPU register stack is not included in the register file size extension in 64-bit mode, compared with the XMM registers used by SSE2, which did get extended. The [[x87]] register stack is not a simple register file although it does allow direct access to individual registers by low cost exchange operations.
; Larger virtual address space
: The AMD64 architecture defines a 64-bit virtual address format, of which the low-order 48 bits are used in current implementations.<ref name="amd-24593"/>{{rp|page=120|date=November 2012}} This allows up to 256&nbsp;[[Tebibyte|TiB]] (2<sup>48</sup> [[byte]]s) of virtual address space. The architecture definition allows this limit to be raised in future implementations to the full 64 bits,<ref name="amd-24593"/>{{rp|page=2|date=November 2012}}{{rp|page=3|date=November 2012}}{{rp|page=13|date=November 2012}}{{rp|page=117|date=November 2012}}{{rp|page=120|date=November 2012}} extending the virtual address space to 16&nbsp;[[Exbibyte|EiB]] (2<sup>64</sup> bytes).<ref>Mauerer, W. (2010). Professional Linux kernel architecture. John Wiley & Sons.</ref> This is compared to just 4&nbsp;[[Gibibyte|GiB]] (2<sup>32</sup> bytes) for the x86.<ref name="intel-253668">{{cite web
  |url       = http://www.intel.com/Assets/PDF/manual/253668.pdf
  |title       = Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 3A: System Programming Guide, Part&nbsp;1
  |access-date       = July 10, 2019
  |pages       = 4–7
  |archive-date       = May 16, 2011
  |archive-url       = https://web.archive.org/web/20110516145322/http://www.intel.com/Assets/PDF/manual/253668.pdf
  |url-status       = live
  }}</ref>
: This means that very large files can be operated on by [[Memory-mapped file|mapping]] the entire file into the process's address space (which is often much faster than working with file read/write calls), rather than having to map regions of the file into and out of the address space.
; Larger physical address space
: The original implementation of the AMD64 architecture implemented 40-bit [[physical address]]es and so could address up to 1&nbsp;TiB (2<sup>40</sup> bytes) of RAM.<ref name="amd-24593" />{{rp|page=24|date=November 2012}} Current implementations of the AMD64 architecture (starting from [[AMD K10|AMD 10h microarchitecture]]) <!--- it's "10h", as in 10 hex, not 10th as in tenth. Please see the reference named amd10h, immediately following. Please do not change this back to "10th" ---> extend this to 48-bit physical addresses<ref name="amd10h">{{cite web |url=http://developer.amd.com/wordpress/media/2012/10/31116.pdf |title=BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors |access-date=February 27, 2016 |page=24 |quote=Physical address space increased to 48 bits. |archive-date=April 18, 2016 |archive-url=https://web.archive.org/web/20160418185513/http://developer.amd.com/wordpress/media/2012/10/31116.pdf |url-status=live }}</ref> and therefore can address up to 256&nbsp;TiB (2<sup>48</sup> bytes) of RAM. The architecture permits extending this to 52 bits in the future<ref name="amd-24593" />{{rp|page=24|date=November 2012}}<ref>
{{cite web
  |url      = http://www.amd64.org/fileadmin/user_upload/pub/64bit_Linux-Myths_and_Facts.pdf
  |title      = Myth and facts about 64-bit Linux
  |access-date      = May 30, 2010
  |date      = March 2, 2008
  |page      = 7
  |quote      = Physical address space increased to 48 bits
  |url-status      = dead
  |archive-url      = https://web.archive.org/web/20101010233951/http://www.amd64.org/fileadmin/user_upload/pub/64bit_Linux-Myths_and_Facts.pdf
  |archive-date      = October 10, 2010
  |df      = mdy-all
  }}</ref> (limited by the page table entry format);<ref name="amd-24593" />{{rp|page=131|date=November 2012}} this would allow addressing of up to 4&nbsp;PiB of RAM. For comparison, 32-bit x86 processors are limited to 64&nbsp;GiB of RAM in [[Physical Address Extension]] (PAE) mode,<ref name="shanley-ppro">{{cite book |title      = Pentium Pro and Pentium II System Architecture
 |edition    = Second
 |last       = Shanley
 |first      = Tom
 |isbn       = 0-201-30973-4
 |series     = PC System Architecture Series
 |year       = 1998
 |publisher  = Addison-Wesley
 |page       = [https://archive.org/details/pentiumpropentiu00shan/page/445 445]
 |url-access = registration
 |url        = https://archive.org/details/pentiumpropentiu00shan/page/445
}}</ref> or 4&nbsp;GiB of RAM without PAE mode.<ref name="amd-24593" />{{rp|page=4|date=November 2012}}
; Larger physical address space in legacy mode
: When operating in [[legacy mode]] the AMD64 architecture supports [[Physical Address Extension]] (PAE) mode, as do most current x86 processors, but AMD64 extends PAE from 36 bits to an architectural limit of 52&nbsp;bits of physical address. Any implementation, therefore, allows the same physical address limit as under [[long mode]].<ref name="amd-24593" />{{rp|page=24|date=November 2012}}
; Instruction pointer relative data access
: Instructions can now reference data relative to the instruction pointer (RIP register). This makes [[position-independent code]], as is often used in [[Library (computing)#Shared libraries|shared libraries]] and code loaded at run time, more efficient.
; SSE instructions
: The original AMD64 architecture adopted Intel's [[Streaming SIMD Extensions|SSE]] and [[SSE2]] as core instructions. These instruction sets provide a vector supplement to the scalar [[x87]] FPU, for the single-precision and double-precision data types. SSE2 also offers integer vector operations, for data types ranging from 8bit to 64bit precision. This makes the vector capabilities of the architecture on par with those of the most advanced x86 processors of its time. These instructions can also be used in 32-bit mode. The proliferation of 64-bit processors has made these vector capabilities ubiquitous in home computers, allowing the improvement of the standards of 32-bit applications. The 32-bit edition of Windows 8, for example, requires the presence of SSE2 instructions.<ref>{{cite web|last=Microsoft Corporation|title=What is PAE, NX, and SSE2 and why does my PC need to support them to run Windows 8 ?|url=http://windows.microsoft.com/en-GB/windows-8/what-is-pae-nx-sse2|access-date=March 19, 2013|archive-date=April 11, 2013|archive-url=https://web.archive.org/web/20130411004411/http://windows.microsoft.com/en-GB/windows-8/what-is-pae-nx-sse2|url-status=live}}</ref> [[SSE3]] instructions and later [[Streaming SIMD Extensions]] instruction sets are not standard features of the architecture.
; No-Execute bit
: The No-Execute bit or [[NX bit]] (bit 63 of the page table entry) allows the operating system to specify which pages of virtual address space can contain executable code and which cannot. An attempt to execute code from a page tagged "no execute" will result in a memory access violation, similar to an attempt to write to a read-only page. This should make it more difficult for malicious code to take control of the system via "[[Buffer overflow|buffer overrun]]" or "unchecked buffer" attacks. A similar feature has been available on x86 processors since the [[80286]] as an attribute of [[segment descriptor]]s; however, this works only on an entire segment at a time.
: [[x86 memory segmentation|Segmented addressing]] has long been considered an obsolete mode of operation, and all current PC operating systems in effect bypass it, setting all segments to a base address of zero and (in their 32-bit implementation) a size of 4&nbsp;GiB. AMD was the first x86-family vendor to implement no-execute in linear addressing mode. The feature is also available in legacy mode on AMD64 processors, and recent Intel x86 processors, when PAE is used.
; Removal of older features
: A few "system programming" features of the x86 architecture were either unused or underused in modern operating systems and are either not available on AMD64 in long (64-bit and compatibility) mode, or exist only in limited form. These include segmented addressing (although the FS and GS segments are retained in vestigial form for use as extra-base pointers to operating system structures),<ref name="amd-24593"/>{{rp|page=70|date=November 2012}} the [[Task State Segment|task state switch]] mechanism, and [[virtual 8086 mode]]. These features remain fully implemented in "legacy mode", allowing these processors to run 32-bit and 16-bit operating systems without modifications. Some instructions that proved to be rarely useful are not supported in 64-bit mode, including saving/restoring of segment registers on the stack, saving/restoring of all registers (PUSHA/POPA), decimal arithmetic, BOUND and INTO instructions, and "far" jumps and calls with immediate operands.

=== Virtual address space details<span class="anchor" id="VIRTUAL-ADDRESS-SPACE"></span> ===
==== Canonical form addresses ====
{{Multiple image
 | header    = Canonical address space implementations (diagrams not to scale)
 | width     = 150
 | direction = horizontal
 | align     = right
 | image1    = AMD64-canonical--48-bit.svg
 | caption1  = Current 48-bit implementation
 | image2    = AMD64-canonical--57-bit.svg
 | caption2  = 57-bit implementation
 | image3    = AMD64-canonical--64-bit.svg
 | caption3  = 64-bit implementation
}}

Although virtual addresses are 64&nbsp;bits wide in 64-bit mode, current implementations (and all chips that are known to be in the planning stages) do not allow the entire virtual address space of 2<sup>64</sup> bytes (16&nbsp;[[Exbibyte|EiB]]) to be used. This would be approximately four billion times the size of the virtual address space on 32-bit machines. Most operating systems and applications will not need such a large address space for the foreseeable future, so implementing such wide virtual addresses would simply increase the complexity and cost of address translation with no real benefit. AMD, therefore, decided that, in the first implementations of the architecture, only the least significant 48&nbsp;bits of a virtual address would actually be used in address translation ([[page table]] lookup).<ref name="amd-24593"/>{{rp|page=120|date=November 2012}}

In addition, the AMD specification requires that the most significant 16 bits of any virtual address, bits 48 through 63, must be copies of bit 47 (in a manner akin to [[sign extension]]). If this requirement is not met, the processor will raise an exception.<ref name="amd-24593"/>{{rp|page=131|date=November 2012}} Addresses complying with this rule are referred to as "canonical form."<ref name="amd-24593"/>{{rp|page=130|date=November 2012}} Canonical form addresses run from 0 through 00007FFF'FFFFFFFF, and from FFFF8000'00000000 through FFFFFFFF'FFFFFFFF, for a total of 256&nbsp;[[Tebibyte|TiB]] of usable virtual address space. This is still 65,536 times larger than the virtual 4&nbsp;GiB address space of 32-bit machines.

This feature eases later scalability to true 64-bit addressing. Many operating systems (including, but not limited to, the [[Windows NT]] family) take the higher-addressed half of the address space (named [[kernel space]]) for themselves and leave the lower-addressed half ([[user space]]) for application code, user mode stacks, heaps, and other data regions.<ref name="win-lim-msdn"/> The "canonical address" design ensures that every AMD64 compliant implementation has, in effect, two memory halves: the lower half starts at 00000000'00000000 and "grows upwards" as more virtual address bits become available, while the higher half is "docked" to the top of the address space and grows downwards. Also, enforcing the "canonical form" of addresses by checking the unused address bits prevents their use by the operating system in [[tagged pointer]]s as flags, privilege markers, etc., as such use could become problematic when the architecture is extended to implement more virtual address bits.

The first versions of Windows for x64 did not even use the full 256&nbsp;TiB; they were restricted to just 8&nbsp;TiB of user space and 8&nbsp;TiB of kernel space.<ref name="win-lim-msdn">{{cite web |url=http://msdn.microsoft.com/en-us/library/windows/desktop/aa366778(v=vs.85).aspx#memory_limits |title=Memory Limits for Windows Releases |website=[[MSDN]] |publisher=[[Microsoft]] |date=November 16, 2013 |access-date=January 20, 2014 |archive-date=January 6, 2014 |archive-url=https://web.archive.org/web/20140106195757/http://msdn.microsoft.com/en-us/library/windows/desktop/aa366778(v=vs.85).aspx#memory_limits |url-status=live }}</ref> Windows did not support the entire 48-bit address space until [[Windows&nbsp;8.1]], which was released in October 2013.<ref name="win-lim-msdn"/> <!--- it would be good to include other OS's limits here. --->

==== Page table structure ====
[[File:X86 Paging 64bit.svg|right|555px]]
The 64-bit addressing mode ("[[long mode]]") is a superset of [[Physical Address Extension]]s (PAE); because of this, [[paging|page]] sizes may be 4&nbsp;[[Kibibyte|KiB]] (2<sup>12</sup> bytes) or 2&nbsp;[[Mebibyte|MiB]] (2<sup>21</sup> bytes).<ref name="amd-24593"/>{{rp|page=120|date=November 2012}} Long mode also supports page sizes of 1&nbsp;[[Gibibyte|GiB]] (2<sup>30</sup> bytes).<ref name="amd-24593"/>{{rp|page=120|date=November 2012}} Rather than the three-level [[page table]] system used by systems in PAE mode, systems running in [[long mode]] use four levels of page table: PAE's ''Page-Directory Pointer Table'' is extended from four entries to 512, and an additional ''Page-Map Level&nbsp;4 (PML4) Table'' is added, containing 512 entries in 48-bit implementations.<ref name="amd-24593"/>{{rp|page=131|date=November 2012}} A full mapping hierarchy of 4&nbsp;KiB pages for the whole 48-bit space would take a bit more than 512&nbsp;[[Gibibyte|GiB]] of memory (about 0.195% of the 256&nbsp;TiB virtual space).

:{| class="wikitable" style="text-align:center"
|+ style="font-size: 105%; white-space: nowrap;" | 64 bit page table entry
|- style="border-top: 2px solid #777777;"
! Bits:
! 63
! colspan="11" | 62&nbsp;...&nbsp;52
! colspan="20" | 51&nbsp;...&nbsp;32
|- style="border-bottom: 2px solid #777777;"
! Content:
| [[NX bit|NX]]
| colspan="11" style="background-color: #ccc;" | ''reserved''
| colspan="20" | Bit&nbsp;51...32&nbsp;of base address
|-
!Bits:
! colspan="20" | 31&nbsp;...&nbsp;12
! colspan="3" | 11&nbsp;...&nbsp;9
! 8
! 7
! 6
! 5
! 4
! 3
! 2
! 1
! 0
|- style="border-bottom: 2px solid #777777;"
! Content:
| colspan="20" | Bit&nbsp;31...12&nbsp;of&nbsp;base address
| colspan="3" | ''ign.''
| G
| PAT
| D
| A
| PCD
| PWT
| U/S
| R/W
| P
|}

Intel has implemented a scheme with a [[Intel 5-level paging|5-level page table]], which allows Intel 64 processors to support 57-bit addresses, and in turn, a 128&nbsp;[[pebibyte|PiB]] virtual address space.<ref>{{cite web|url=https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf|title=5-Level Paging and 5-Level EPT|publisher=Intel|date=May 2017|access-date=June 17, 2017|archive-date=December 5, 2018|archive-url=https://web.archive.org/web/20181205041235/https://software.intel.com/sites/default/files/managed/2b/80/5-level_paging_white_paper.pdf|url-status=live}}</ref> Further extensions may allow full 64-bit virtual address space and physical memory with 12-bit page table descriptors and 16- or 21-bit memory offsets for 64&nbsp;KiB and 2&nbsp;MiB page allocation sizes; the page table entry would be expanded to 128 bits to support additional hardware flags for page size and virtual address space size.<ref>{{cite patent | country = US | number = 9858198 | status = patent | title =  64KB page system that supports 4KB page operation | pridate = 2015-06-26 | fdate = 2015-06-26 | pubdate = 2016-12-29 | gdate = 2018-01-02 | invent1 = Larry Seiler | assign1 = Intel Corp.}}</ref>

==== Operating system limits ====
The operating system can also limit the virtual address space. Details, where applicable, are given in the "[[#Operating system compatibility and characteristics|Operating system compatibility and characteristics]]" section.

=== Physical address space details ===
Current AMD64 processors support a physical address space of up to 2<sup>48</sup> bytes of RAM, or 256&nbsp;[[Tebibyte|TiB]].<ref name="amd10h"/> However, {{as of|2020|lc=1}}, there were no known x86-64 [[motherboard]]s that support 256&nbsp;TiB of RAM.<ref>{{cite web
|url       = http://www.supermicro.com/Aplus/motherboard/Opteron6100/
|title       = Opteron 6100 Series Motherboards
|publisher       = Supermicro Corporation
|access-date       = June 22, 2010
|archive-date       = June 3, 2010
|archive-url       = https://web.archive.org/web/20100603182215/http://www.supermicro.com/Aplus/motherboard/Opteron6100/
|url-status       = dead
}}</ref><ref>{{cite web
|url       = http://www.supermicro.com/products/motherboard/Xeon1333/#1366
|title       = Supermicro Xeon<!-- AutoEd: rm unicode ctrl char w/no win-1252 mapping, intent unknown -->Solutions
|publisher       = Supermicro Corporation
|access-date       = June 20, 2010
|archive-date       = May 27, 2010
|archive-url       = https://web.archive.org/web/20100527224603/http://www.supermicro.com/products/motherboard/Xeon1333/#1366
|url-status       = dead
}}</ref><ref>{{cite web
|url       = http://www.supermicro.com/Aplus/motherboard/Opteron8000/
|title       = Opteron 8000 Series Motherboards
|publisher       = Supermicro Corporation
|access-date       = June 20, 2010
|archive-date       = May 27, 2010
|archive-url       = https://web.archive.org/web/20100527212322/http://www.supermicro.com/Aplus/motherboard/Opteron8000/
|url-status       = dead
}}</ref><ref>{{cite web
|url       = http://www.supermicro.com/products/motherboard/Core/index.cfm#1366
|title       = Tyan Product Matrix
|publisher       = MiTEC International Corporation
|access-date       = June 21, 2010
|archive-date       = June 6, 2010
|archive-url       = https://web.archive.org/web/20100606190740/http://www.supermicro.com/products/motherboard/Core/index.cfm#1366
|url-status       = dead
}}</ref>{{failed verification|date=May 2016}} The operating system may place additional limits on the amount of RAM that is usable or supported. Details on this point are given in the "[[#Operating system compatibility and characteristics|Operating system compatibility and characteristics]]" section of this article.

=== {{Anchor|OPMODES}}Operating modes ===
The architecture has two primary modes of operation: long mode and legacy mode.

{| class="wikitable" style="text-align: center;"
|-
! colspan="2" | Operating
! rowspan="2" | [[Operating system]] required
! rowspan="2" | Type of code being run
! colspan="2" | Size (in bits)
! rowspan="2" | No. of [[register file|general-purpose registers]]
|-
! Mode
! Sub-mode
! Addresses
! Operands ('''''default in italics''''')
|-
| rowspan="3" | [[Long mode]]
| 64-bit mode
| 64-bit OS, 64-bit [[UEFI]] firmware, or the previous two interacting via a 64-bit firmware's UEFI interface
| [[long mode|64-bit]]
| 64
| 8, 16, '''''32''''', 64
| 16
|-
| rowspan="2" | Compatibility mode
| rowspan="2" | [[Bootloader]] or 64-bit OS
| [[protected mode#The 386|32-bit]]
| 32
| 8, 16, '''''32'''''
| 8
|-
| [[protected mode#The 286|16-bit protected mode]]
| 16
| 8, '''''16''''', 32
| 8
|-
| rowspan="5" | Legacy mode
| rowspan="2" | [[Protected mode]]
| [[Bootloader]], 32-bit OS, 32-bit UEFI firmware, or the latter two interacting via the firmware's UEFI interface
| [[protected mode#The 386|32-bit]]
| 32
| 8, 16, '''''32'''''
| 8
|-
| 16-bit protected mode OS
| [[protected mode#The 286|16-bit protected mode]]
| 16
| 8, '''''16''''', 32<ref group="m" name="opsize-prefix"/>
| 8
|-
| [[Virtual 8086 mode]]
| 16-bit protected mode or 32-bit OS
| subset of [[real mode]]
| 16
| 8, '''''16''''', 32<ref group="m" name="opsize-prefix"/>
| 8
|-
| [[Unreal mode]]
| [[Bootloader]] or real mode OS
| [[real mode]]
| 16, 20, 32
| 8, '''''16''''', 32<ref group="m" name="opsize-prefix"/>
| 8
|-
| [[Real mode]]
| [[Bootloader]], real mode OS, or any OS interfacing with a firmware's [[BIOS]] interface<ref name="AMIBlog">{{Cite web | title = From the AMI Archives: AMIBIOS 8 and the Transition to EFI | date = September 8, 2017 | url = https://www.ami.com/tech-blog/from-the-ami-archives-amibios-8-and-the-transition-to-efi/ | access-date = October 25, 2021 | publisher = [[American Megatrends]] | archive-date = October 25, 2021 | archive-url = https://web.archive.org/web/20211025233343/https://www.ami.com/tech-blog/from-the-ami-archives-amibios-8-and-the-transition-to-efi/ | url-status = dead}}</ref>
| [[real mode]]
| 16, 20, [[A20 line|21]]
| 8, '''''16''''', 32<ref group="m" name="opsize-prefix"/>
| 8
|}
{{reflist|group=m|refs=<ref name="opsize-prefix">Note that 16-bit code written for the 80286 and below does not use 32-bit operand instructions. Code written for the 80386 and above can use the operand-size override prefix (0x66). Normally this prefix is used by protected and long mode code for the purpose of using 16-bit operands, as that code would be running in a code segment with a default operand size of 32 bits. In real mode, the default operand size is 16 bits, so the 0x66 prefix is interpreted differently, changing operand size to 32 bits.</ref>}}
[[File:AMD64StateDiagram.svg|thumb|400px|State diagram of the x86-64 operating modes]]

==== Long mode ====
{{Main|Long mode}}

Long mode is the architecture's intended primary mode of operation; it is a combination of the processor's native 64-bit mode and a combined 32-bit and 16-bit compatibility mode. It is used by 64-bit operating systems. Under a 64-bit operating system, 64-bit programs run under 64-bit mode, and 32-bit and 16-bit protected mode applications (that do not need to use either real mode or virtual 8086 mode in order to execute at any time) run under compatibility mode. Real-mode programs and programs that use virtual 8086 mode at any time cannot be run in long mode unless those modes are emulated in software.<ref name="amd-24593"/>{{rp|11}} However, such programs may be started from an operating system running in long mode on processors supporting [[VT-x]] or [[AMD-V]] by creating a virtual processor running in the desired mode.

Since the basic [[instruction set]] is the same, there is almost no performance penalty for executing protected mode x86 code. This is unlike Intel's [[IA-64]], where differences in the underlying instruction set mean that running 32-bit code must be done either in emulation of x86 (making the process slower) or with a dedicated x86 coprocessor. However, on the x86-64 platform, many x86 applications could benefit from a 64-bit [[recompile]], due to the additional registers in 64-bit code and guaranteed SSE2-based FPU support, which a [[compiler]] can use for optimization. However, applications that regularly handle integers wider than 32 bits, such as cryptographic algorithms, will need a rewrite of the code handling the huge integers in order to take advantage of the 64-bit registers.

==== Legacy mode ====
Legacy mode is the mode that the processor is in when it is not in long mode.<ref name="amd-24593" />{{rp|page=14|date=March 2021}} In this mode, the processor acts like an older x86 processor, and only 16-bit and 32-bit code can be executed. Legacy mode allows for a maximum of 32&nbsp;bit virtual addressing which limits the virtual address space to 4&nbsp;GiB.<ref name="amd-24593"/>{{rp|page=14|date=November 2012}}{{rp|page=24|date=November 2012}}{{rp|page=118|date=November 2012}} 64-bit programs cannot be run from legacy mode.

==== Protected mode ====
[[Protected mode]] is made into a submode of legacy mode.<ref name="amd-24593" />{{rp|page=14|date=March 2021}} It is the submode that 32-bit operating systems and 16-bit protected mode operating systems operate in when running on an x86-64 CPU.<ref name="amd-24593" />{{rp|page=14|date=March 2021}}

==== Real mode ====
[[Real mode]] is the initial mode of operation when the processor is initialized, and is a submode of legacy mode. It is backwards compatible with the original [[Intel 8086]] and [[Intel 8088]] processors. Real mode is primarily used today by operating system bootloaders, which are required by the architecture to configure [[#Physical_address_space_details|virtual memory details]] before transitioning to higher modes. This mode is also used by any operating system that needs to communicate with the system firmware with a traditional [[BIOS]]-style interface.<ref name="AMIBlog" />

== Intel 64 ==
'''Intel&nbsp;64''' is Intel's implementation of x86-64, used and implemented in various processors made by Intel.

=== History ===
Historically, AMD has developed and produced processors with instruction sets patterned after Intel's original designs, but with x86-64, roles were reversed: Intel found itself in the position of adopting the [[instruction set architecture|ISA]] that AMD created as an extension to Intel's own x86 processor line.

Intel's project was originally [[codename]]d ''Yamhill''<ref>{{cite news |title=Intel is Continuing the Yamhill Project? |url=https://www.neowin.net/news/intel-is-continuing-the-yamhill-project/ |access-date=5 June 2022 |work=Neowin |language=en |archive-date=June 5, 2022 |archive-url=https://web.archive.org/web/20220605151028/https://www.neowin.net/news/intel-is-continuing-the-yamhill-project/ |url-status=live }}</ref> (after the [[Yamhill River]] in Oregon's Willamette Valley). After several years of denying its existence, Intel announced at the February 2004 [[Intel Developer Forum|IDF]] that the project was indeed underway. Intel's chairman at the time, [[Craig Barrett (chief executive)|Craig Barrett]], admitted that this was one of their worst-kept secrets.<ref>{{cite web |url=https://www.theinquirer.net/inquirer/news/1042795/craig-barrett-confirms-bit-address-extensions-xeon-and-prescott |archive-url=https://archive.today/20130112014446/http://www.theinquirer.net/inquirer/news/1042795/craig-barrett-confirms-bit-address-extensions-xeon-and-prescott |url-status=dead |archive-date=January 12, 2013 |title=Craig Barrett confirms 64 bit address extensions for Xeon. And Prescott. |publisher=The Inquirer |date=February 17, 2004 |access-date=August 20, 2017 }}</ref><ref>{{Cite web |url=http://www.internetnews.com/ent-news/article.php/3518781 |title="A Roundup of 64-Bit Computing", from internetnews.com |access-date=September 18, 2006 |archive-date=September 25, 2012 |archive-url=https://web.archive.org/web/20120925003349/http://www.internetnews.com/ent-news/article.php/3518781 |url-status=dead }}</ref>

Intel's name for this instruction set has changed several times. The name used at the IDF was ''CT''<ref>{{cite web |last1=Lapedus |first1=Mark |title=Intel to demo 'CT' 64-bit processor line at IDF |url=https://www.edn.com/intel-to-demo-ct-64-bit-processor-line-at-idf/ |website=EDN |date=February 6, 2004 |publisher=AspenCore Media |access-date=25 May 2021 |archive-date=May 25, 2021 |archive-url=https://web.archive.org/web/20210525031727/https://www.edn.com/intel-to-demo-ct-64-bit-processor-line-at-idf/ |url-status=live }}</ref> (presumably{{Original research inline|date=August 2017}} for ''Clackamas Technology'', another codename from an [[Clackamas River|Oregon river]]); within weeks they began referring to it as ''IA-32e'' (for [[IA-32]] extensions) and in March 2004 unveiled the "official" name ''EM64T'' (Extended Memory 64 Technology). In late 2006 Intel began instead using the name ''Intel&nbsp;64'' for its implementation, paralleling AMD's use of the name AMD64.<ref>{{cite web
| url        = http://www.intel.com/technology/intel64/index.htm
| title        = Intel&nbsp;64 Architecture
| access-date        = June 29, 2007
| publisher        = [[Intel]]
| archive-date        = June 29, 2011
| archive-url        = https://web.archive.org/web/20110629214538/http://www.intel.com/technology/intel64/index.htm
| url-status        = live
}}</ref>

The first processor to implement Intel&nbsp;64 was the multi-socket processor [[Xeon]] code-named ''[[Xeon#Nocona and Irwindale|Nocona]]'' in June 2004. In contrast, the initial Prescott chips (February 2004) did not enable this feature. Intel subsequently began selling Intel&nbsp;64-enabled Pentium 4s using the E0 revision of the Prescott core, being sold on the OEM market as the Pentium 4, model F. The E0 revision also adds eXecute Disable (XD) (Intel's name for the [[NX bit]]) to Intel&nbsp;64, and has been included in then current Xeon code-named ''Irwindale''. Intel's official launch of Intel&nbsp;64 (under the name EM64T at that time) in mainstream desktop processors was the N0 stepping Prescott-2M in February 2005.<ref>{{cite web|url=http://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%20620%202.8%20GHz%20-%20JM80547PG0722MM%20(BX80547PG2800F).html|title=Pentium 4 HT 620(N0)|website=cpu-world.com|access-date=23 April 2018|url-status=live|archive-url=https://web.archive.org/web/20171208003346/http://www.cpu-world.com/CPUs/Pentium_4/Intel-Pentium%204%20620%202.8%20GHz%20-%20JM80547PG0722MM%20(BX80547PG2800F).html|archive-date=8 December 2017}}</ref>

The first Intel [[mobile processor]] implementing Intel&nbsp;64 is the [[Merom (microprocessor)|Merom]] version of the [[Core 2]] processor, which was released on July 27, 2006. None of Intel's earlier notebook CPUs ([[Core Duo]], [[Pentium M]], [[Celeron M]], [[Pentium 4|Mobile Pentium 4]]) implement Intel&nbsp;64.

=== Implementations ===
Intel's processors implementing the Intel64 architecture include the [[Pentium 4]] F-series/5x1 series, 506, and 516, [[Celeron D]] models 3x1, 3x6, 355, 347, 352, 360, and 365 and all later [[Celeron]]s, all models of [[Xeon]] since "[[Xeon#Nocona and Irwindale|Nocona]]", all models of [[Pentium Dual-Core]] processors since "[[Merom (microprocessor)#Merom-2M|Merom-2M]]", the [[Intel Atom|Atom]] 230, 330, D410, D425, D510, D525, N450, N455, N470, N475, N550, N570, N2600 and N2800, all versions of the [[Pentium D]], [[Pentium Extreme Edition]], [[Core&nbsp;2]], [[Core&nbsp;i9]], [[Core&nbsp;i7]], [[Core&nbsp;i5]], and [[Core&nbsp;i3]] processors, and the [[Xeon Phi]] 7200 series processors.

== VIA's x86-64 implementation ==
[[VIA Technologies]] introduced their first implementation of the x86-64 architecture in 2008 after five years of development by its CPU division, [[Centaur Technology]].<ref>{{cite web
 |title        = VIA to launch new processor architecture in 1Q08
 |date = July 25, 2007
 |publisher    = [[DigiTimes]]
 |url          = http://www.digitimes.com/news/a20070725PD206.html
 |access-date  = July 25, 2007
 |format       = subscription required
 |archive-date = December 3, 2008
 |archive-url  = https://web.archive.org/web/20081203201340/http://www.digitimes.com/news/a20070725PD206.html
 |url-status   = live
}}</ref>
Codenamed "Isaiah", the 64-bit architecture was unveiled on January 24, 2008,<ref>{{cite web
 |title        = Isaiah revealed: VIA's new low-power architecture
 |publisher    = Ars Technica
 |url          = https://arstechnica.com/articles/paedia/cpu/via-cpu-isaiah.ars
 |access-date  = January 24, 2008
 |first        = Jon
 |last         = Stokes
 |date         = January 23, 2008
 |archive-date = January 27, 2008
 |archive-url  = https://web.archive.org/web/20080127095807/http://arstechnica.com/articles/paedia/cpu/via-cpu-isaiah.ars
 |url-status   = live
}}</ref> and launched on May 29 under the [[VIA Nano]] brand name.<ref>{{cite press release
 |title        = VIA Launches VIA Nano Processor Family
 |publisher    = [[VIA Technologies|VIA]]
 |url          = http://www.viatech.com/en/2008/05/via-launches-via-nano-processor-family/
 |access-date  = May 25, 2017
 |date         = May 29, 2008
 |archive-date = February 3, 2019
 |archive-url  = https://web.archive.org/web/20190203072901/https://www.viatech.com/en/2008/05/via-launches-via-nano-processor-family/
 |url-status   = live
}}</ref>

The processor supports a number of VIA-specific x86 extensions designed to boost efficiency in low-power appliances.
It is expected that the Isaiah architecture will be twice as fast in integer performance and four times as fast in [[floating-point]] performance as the previous-generation [[VIA Esther]] at an equivalent [[clock speed]]. Power consumption is also expected to be on par with the previous-generation VIA CPUs, with [[thermal design power]] ranging from 5&nbsp;W to 25&nbsp;W.<ref>{{cite web
 |publisher   = [[VIA Technologies|VIA]]
 |url         = http://www.via.com.tw/en/downloads/presentations/processors/pb_via-isaiah_080124.pdf
 |title       = VIA Isaiah Architecture Introduction
 |access-date  = July 31, 2013
 |date        = January 23, 2008
 |url-status     = dead
 |archive-url  = https://web.archive.org/web/20080907181213/http://www.via.com.tw/en/downloads/presentations/processors/pb_via-isaiah_080124.pdf
 |archive-date = September 7, 2008
 |df          = mdy-all
}}</ref>
Being a completely new design, the Isaiah architecture was built with support for features like the x86-64 instruction set and [[x86 virtualization]] which were unavailable on its predecessors, the [[VIA C7]] line, while retaining their encryption extensions.

== Microarchitecture levels ==
In 2020, through a collaboration between AMD, Intel, [[Red Hat]], and [[SUSE S.A.|SUSE]], three microarchitecture levels (or feature levels) on top of the x86-64 baseline were defined: x86-64-v2, x86-64-v3, and x86-64-v4.<ref>{{cite mailing list |first=Florian |last=Weimer |title=New x86-64 micro-architecture levels |url=https://lists.llvm.org/pipermail/llvm-dev/2020-July/143289.html |mailing-list=llvm-dev|date=10 July 2020 |access-date=March 11, 2021 |archive-date=April 14, 2021 |archive-url=https://web.archive.org/web/20210414100705/https://lists.llvm.org/pipermail/llvm-dev/2020-July/143289.html |url-status=live }}</ref><ref>{{cite web |first=Florian |last=Weimer |title=Building Red Hat Enterprise Linux 9 for the x86-64-v2 microarchitecture level |url=https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level |work=Red Hat developer blog |date=5 January 2021 |access-date=March 22, 2022 |archive-date=February 20, 2022 |archive-url=https://web.archive.org/web/20220220155150/https://developers.redhat.com/blog/2021/01/05/building-red-hat-enterprise-linux-9-for-the-x86-64-v2-microarchitecture-level |url-status=live }}</ref> These levels define specific features that can be targeted by programmers to provide compile-time optimizations. The features exposed by each level are as follows:<ref>{{Cite web |title=System V Application Binary Interface Low Level System Information |url=https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex |website=x86-64 psABI repo |date=29 January 2021 |via=[[GitLab]] |access-date=March 11, 2021 |archive-date=February 2, 2021 |archive-url=https://web.archive.org/web/20210202215134/https://gitlab.com/x86-psABIs/x86-64-ABI/-/blob/master/x86-64-ABI/low-level-sys-info.tex |url-status=live }}</ref>

{| class="wikitable"
|+ style="font-size: 105%;" | CPU microarchitecture levels
|-
! Level&nbsp;name
! CPU features
! Example instruction
! Supported processors
|-
| rowspan="9" | {{nowrap|''x86-64-v1''}}
| [[CMOV]] || {{mono|cmov}}
| rowspan="9" | Baseline for all x86-64 CPUs. Features match the common capabilities between the 2003 AMD ''AMD64'' and the 2004 Intel ''EM64T'' initial implementations in the AMD ''K8'' and the Intel ''Prescott'' processor families.<br />
* [[Intel Corporation|Intel]]
** [[Penryn (microarchitecture)|Penryn]] processors (SSE4.1 supported, except [[Pentium Dual-Core]] and [[Celeron]])
* [[Advanced Micro Devices|AMD]]
** Low-power [[Bobcat (processor)|Bobcat]] processors (SSE4a, <code>POPCNT</code> and <code>LZCNT</code> supported)
** [[AMD 10h|K10]] processors (SSE4a, <code>POPCNT</code> and <code>LZCNT</code> supported)
* [[VIA Technologies|VIA]]
** [[VIA Nano|Nano]] 3000, X2, QuadCore processors (SSE4.1 supported)
|-
| CX8 || {{mono|cmpxchg8b}}
|-
| [[X87|FPU]] || {{mono|fld}}
|-
| FXSR || {{mono|fxsave}}
|-
| MMX || {{mono|emms}}
|-
| OSFXSR || {{mono|fxsave}}
|-
| SCE || {{mono|syscall}}
|-
| SSE || {{mono|cvtss2si}}
|-
| SSE2 || {{mono|cvtpi2pd}}
|-
| rowspan="7" | ''x86-64-v2''
| CMPXCHG16B || {{mono|cmpxchg16b}}
| rowspan="7" | Features match the 2008 Intel Nehalem architecture, excluding Intel-specific instructions.<br />
* [[Intel Corporation|Intel]]
** Low-power [[Silvermont (microarchitecture)|Silvermont]], [[Goldmont]], [[Goldmont Plus]] and [[Tremont (microarchitecture)|Tremont]] processors<br />(SSE4.1, SSE4.2 and <code>POPCNT</code> supported)
** [[Nehalem (microarchitecture)|Nehalem]] and [[Westmere (microarchitecture)|Westmere]] processors<br />(SSE4.1, SSE4.2 and <code>POPCNT</code> supported, except [[Pentium]] and [[Celeron]])
** [[Sandy Bridge (microarchitecture)|Sandy Bridge]] and [[Ivy Bridge (microarchitecture)|Ivy Bridge]] processors<br />(SSE4.1, SSE4.2 and <code>POPCNT</code> supported, including [[Pentium]] and [[Celeron]])
* [[Advanced Micro Devices|AMD]]
** Low-power [[Jaguar (microarchitecture)|Jaguar-based]] and [[Puma (microarchitecture)|Puma-based]] processors<br />(SSE4a, SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
** [[Bulldozer (microarchitecture)|Bulldozer]], [[Piledriver (microarchitecture)|Piledriver]] and [[Steamroller (microarchitecture)|Steamroller]] processors<br />(SSE4a, SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
* [[VIA Technologies|VIA]]
** [[VIA Nano|Nano]] QuadCore C4000-series processors (SSE4.1, SSE4.2 supported)
** [[VIA Eden|Eden]] X4 processors (SSE4.1, SSE4.2 supported)
* [[Zhaoxin]]
** ZX-C processors and newer (SSE4.1, SSE4.2 supported)
|-
| LAHF-SAHF || {{mono|lahf}}
|-
| [[SSE4#POPCNT and LZCNT|POPCNT]] || {{mono|popcnt}}
|-
| SSE3 || {{mono|addsubpd}}
|-
| SSE4_1 || {{mono|blendpd}}
|-
| [[SSE4.2|SSE4_2]] || {{mono|pcmpestri}}
|-
| SSSE3 || {{mono|pshufb}}
|-
| rowspan=9 | ''x86-64-v3''
| AVX || {{mono|vzeroall}}
| rowspan=9 | Features match the 2013 Intel Haswell architecture, excluding Intel-specific instructions.<br />
* [[Intel Corporation|Intel]]
** Low-power [[Gracemont (microarchitecture)|Gracemont]] processors (SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
** [[Haswell (microarchitecture)|Haswell]] and [[Broadwell (microarchitecture)|Broadwell]] processors (SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
* [[Advanced Micro Devices|AMD]]
** [[Excavator (microarchitecture)|Excavator]] processors (SSE4a, SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
** [[Zen (microarchitecture)|Zen]], [[Zen+]], [[Zen 2]], and [[Zen 3]] processors (SSE4a, SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
* [[Zhaoxin]]
** YongFeng and Shijidadao processors (SSE4.2, AVX2 and FMA3 supported)
|-
| AVX2 || {{mono|vpermd}}
|-
| BMI1 || {{mono|andn}}
|-
| BMI2 || {{mono|bzhi}}
|-
| F16C || {{mono|vcvtph2ps}}
|-
| FMA || {{mono|vfmadd132pd}}
|-
| LZCNT || {{mono|lzcnt}}
|-
| MOVBE || {{mono|movbe}}
|-
| OSXSAVE || {{mono|xgetbv}}
|-
| rowspan="5" | ''x86-64-v4''
| AVX512F || {{mono|kmovw}}
| rowspan="5" | Features match the 2017 Intel Skylake-X architecture, excluding Intel-specific instructions.<br />
* [[Intel Corporation|Intel]]
** [[Skylake (microarchitecture)|Skylake]] processors and newer (SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
* [[Advanced Micro Devices|AMD]]
** [[Zen 4|Zen4]] processors and newer (SSE4a, SSE4.1, SSE4.2, <code>POPCNT</code> and <code>LZCNT</code> supported)
|-
| AVX512BW || {{mono|vdbpsadbw}}
|-
| AVX512CD || {{mono|vplzcntd}}
|-
| AVX512DQ || {{mono|vpmullq}}
|-
| AVX512VL || {{n/a}}
|}

The x86-64 microarchitecture feature levels can also be found as AMD64-v1, AMD64-v2 .. or AMD64_v1 .. in settings where the "AMD64" nomenclature is used. These are used as synonyms with the x86-64-vX nomenclature and are thus functionally identical. Examples of this include the Go language documentation and the Fedora Linux distribution.

All levels include features found in the previous levels. Instruction set extensions not concerned with general-purpose computation, including [[AES-NI]] and [[RDRAND]], are excluded from the level requirements.

On most recent x86_64 Linux distributions, all x86_64 feature levels supported by a CPU can be verified using command: <code>/lib64/ld-linux-x86-64.so.2 --help</code> (available since [[glibc]] 2.33<ref>{{cite web|url=https://sourceware.org/git/?p=glibc.git;a=blob;f=NEWS;h=71f5d20324a92ddd5aad861f2194bac2f4357df2;hb=9826b03b747b841f5fc6de2054bf1ef3f5c4bdf3|title=GNU C Library NEWS -- history of user-visible changes|date=2021-02-01|access-date=2025-05-28}}</ref>). The result will be visible at the end of command's output:
<syntaxhighlight lang="output">
Subdirectories of glibc-hwcaps directories, in priority order:
  x86-64-v4
  x86-64-v3 (supported, searched)
  x86-64-v2 (supported, searched)
</syntaxhighlight>
Here x86-64-v4 feature level is not supported by CPU, but x86-64-v3 and x86-64-v2 are, which means this CPU does not support AVX512 required at v4 level.

== Differences between AMD64 and Intel 64 ==
Although nearly identical, there are some differences between the two instruction sets in the semantics of a few seldom used machine instructions (or situations), which are mainly used for [[system programming]].<ref name=trcscott>{{cite web |last= Wasson |first= Scott |title= 64-bit computing in theory and practice |url= http://techreport.com/articles.x/8131/1 |work= The Tech Report |date= March 23, 2005 |access-date= March 22, 2011 |archive-date= March 12, 2011 |archive-url= https://web.archive.org/web/20110312004304/http://techreport.com/articles.x/8131/1 |url-status= live }}</ref> Unless instructed to otherwise via <code>-march</code> settings, compilers generally produce [[executable]]s (i.e. [[machine code]]) that avoid any differences, at least for ordinary [[application software|application programs]]. This is therefore of interest mainly to developers of compilers, operating systems and similar, which must deal with individual and special system instructions.

=== Recent implementations ===
* Intel&nbsp;64 allows <code>SYSCALL</code>/<code>SYSRET</code> only in 64-bit mode (not in compatibility mode),<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A–Z|pages=4–397|publisher=Intel|date=September 2013|access-date=January 21, 2014|archive-date=October 20, 2013|archive-url=https://web.archive.org/web/20131020144800/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|url-status=live}}</ref> and allows <code>SYSENTER</code>/<code>SYSEXIT</code> in both modes.<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z|pages=4–400|publisher=Intel|date=September 2013|access-date=January 21, 2014|archive-date=October 20, 2013|archive-url=https://web.archive.org/web/20131020144800/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|url-status=live}}</ref> AMD64 lacks <code>SYSENTER</code>/<code>SYSEXIT</code> in both sub-modes of [[long mode]].<ref name="amd-24593"/>{{rp|33}}
* When returning to a non-canonical address using <code>SYSRET</code>, AMD64 processors execute the general protection fault handler in privilege level 3,<ref>{{cite web|url=https://support.amd.com/TechDocs/24594.pdf|title=AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions|page=419|publisher=AMD|date=May 2018|access-date=August 2, 2018|archive-date=August 20, 2018|archive-url=https://web.archive.org/web/20180820123419/https://support.amd.com/TechDocs/24594.pdf|url-status=live}}</ref> while on Intel&nbsp;64 processors it is executed in privilege level 0.<ref>{{cite web|url=http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|title=Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2 (2A, 2B & 2C): Instruction Set Reference, A-Z|pages=4–412|publisher=Intel|date=September 2014|access-date=December 28, 2014|archive-date=January 13, 2015|archive-url=https://web.archive.org/web/20150113223656/http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf|url-status=live}}</ref>
* The <code>SYSRET</code> instruction will load a set of fixed values into the hidden part of the <code>SS</code> [[x86 memory segmentation|segment register]] (base-address, limit, attributes) on Intel&nbsp;64 but leave the hidden part of <code>SS</code> unchanged on AMD64.<ref>{{cite mailing list |mailing-list=x86@kernel.org |url=https://lore.kernel.org/lkml/5d120f358612d73fc909f5bfa47e7bd082db0af0.1429841474.git.luto@kernel.org/ |title=(PATCH) x86_64, asm: Work around AMD SYSRET SS descriptor attribute issue |author=Andy Lutomirski  |date=23 April 2015}}</ref>
* On Intel&nbsp;64, the <code>SYSRET</code> instruction unconditionally sets the [[Privilege level|privilege level]] (RPL) of the <code>SS</code> segment register to 3 (as the instruction causes a return to privilege level 3).<ref>{{cite web |title=Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 |url=https://cdrdv2-public.intel.com/843829/325383-sdm-vol-2abcd-dec-24.pdf |publisher=Intel |date=July 2025 |page=1442, see the assignment of SS.Selector}}</ref> On AMD64, the RPL is set to the corresponding bits in the STAR MSR ([[model-specific register]]), that is, bits 49 and 48.<ref>{{cite web |title=AMD64 Architecture Programmer’s Manual, Volume 2: System Programming |url=https://docs.amd.com/v/u/en-US/24593_3.43 |publisher=AMD |date=July 2025 |page=237, "SYSRET CS and SS Selectors"}}</ref>
* AMD64 requires a different microcode update format and control MSRs, while Intel&nbsp;64 implements [[microcode]] update unchanged from their 32-bit only processors.
* Intel&nbsp;64 lacks some MSRs that are considered architectural in AMD64. These include <code>SYSCFG</code>, <code>TOP_MEM</code>, and <code>TOP_MEM2</code>.
* Intel&nbsp;64 lacks the ability to save and restore a reduced (and thus faster) version of the [[floating-point]] state (involving the <code>FXSAVE</code> and <code>FXRSTOR</code> instructions).{{clarify|date=July 2021}}
* On AMD64, the <code>FXSAVE</code>/<code>FXRSTOR</code> instructions will only save/restore x87 exception pointers (FCS/FIP, FDS/FDP, FOP) when an unmasked pending x87 exception is present.<ref>AMD, [https://docs.amd.com/v/u/en-US/24593_3.43 AMD64 Architecture Programmer’s Manual Volume 2], order no. 24593, rev 3.43, June 2025, section 11.4.4.3 on page 355</ref><ref>CVE, [https://www.cve.org/CVERecord?id=CVE-2006-1056 CVE-2006-1056], security issue related to <code>FXSAVE</code>'s handling of x87 exception pointers on AMD64.</ref> On Intel&nbsp;64, these pointers are always saved and restored regardless of x87 exception status.
* In 64-bit mode, near branches with the 66H (operand size override) prefix behave differently. Intel&nbsp;64 ignores this prefix: the instruction has a 32-bit sign extended offset, and instruction pointer is not truncated. AMD64 uses a 16-bit offset field in the instruction, and clears the top 48&nbsp;bits of instruction pointer.
* On Intel&nbsp;64 but not AMD64, the <code>[[REX prefix|REX]].W</code> prefix can be used with the far-pointer instructions (<code>LFS</code>, <code>LGS</code>, <code>LSS</code>, {{nobreak|<code>JMP FAR</code>}}, {{nobreak|<code>CALL FAR</code>}}) to increase the size of their [[far pointer]] argument to 80 bits (64-bit offset + 16-bit segment).
* When the <code>MOVSXD</code> instruction is executed with a memory source operand and an operand-size of 16 bits, the memory operand will be accessed with a 16-bit read on Intel&nbsp;64, but a 32-bit read on AMD64.
* When the <code>PUSH</code> instruction is used with a [[x86 memory segmentation|segment register]] and an operand-size of 32 bits in legacy/compatibility mode, AMD64 will zero-extend the register from 2 to 4 bytes and push that 4-byte value onto the stack. Intel&nbsp;64 will also decrement the stack pointer by 4 but will just write 2 bytes, leaving a 2-byte hole that's not written.<ref>{{cite web |publisher=AMD |archive-url=https://web.archive.org/web/20091211024133/http://developer.amd.com/assets/CrossVendorMigration.pdf |title=Cross-Vendor Migration |date=2009 |page=7 |url=http://developer.amd.com/assets/CrossVendorMigration.pdf |archive-date=December 11, 2009 |url-status=dead |access-date=June 2, 2025 }}</ref><ref name="intel_seg_pushpop"/>
* When the <code>POP</code> instruction is used with a segment register and an operand-size of 32 or 64 bits, AMD64 will perform a memory read from the stack that is as wide as the operand-size, while Intel&nbsp;64 will perform a 16-bit memory read (but still increment the stack-pointer according to the operand size.)<ref name="intel_seg_pushpop">{{cite book |publisher=Intel |url=https://cdrdv2-public.intel.com/850979/253669-087-sdm-vol-3b.pdf |title=Intel 64 and IA-32 Architectures Software Developer’s Manual, volume 3B |id=order no. 253669-087 |at=section 24.31.1 on page 452 |archive-url=https://web.archive.org/web/20250516110000/https://cdrdv2-public.intel.com/850979/253669-087-sdm-vol-3b.pdf |archive-date=16 May 2025 |url-status=live}}</ref>
* The <code>FCOMI</code>/<code>FCOMIP</code>/<code>FUCOMI</code>/<code>FUCOMIP</code> (x87 floating-point compare) instructions will clear the OF, SF and AF bits of [[EFLAGS]] on Intel&nbsp;64, but leave these flag bits unmodified on AMD64. 
* For the <code>VMASKMOVPS</code>/<code>VMASKMOVPD</code>/<code>VPMASKMOVD</code>/<code>VPMASKMOVQ</code> (AVX/AVX2 masked move to/from memory) instructions, Intel&nbsp;64 architecturally guarantees that the instructions will not cause memory faults (e.g. page-faults and segmentation-faults) for any zero-masked lanes, while AMD64 does not provide such a guarantee.
* If the <code>RDRAND</code> instruction fails to obtain a random number (as indicated by <code>[[EFLAGS]].CF=0</code>), the destination register is architecturally guaranteed to be set to 0 on Intel&nbsp;64 but not AMD64.
* For the <code>VPINSRD</code> and <code>VPEXTRD</code> (AVX vector lane insert/extract) instructions outside 64-bit mode, AMD64 requires the instructions to be encoded with <code>[[VEX prefix|VEX]].W=0</code>, while Intel&nbsp;64 also accepts encodings with <code>VEX.W=1</code>. (In 64-bit mode, both AMD64 and Intel&nbsp;64 require <code>VEX.W=0</code>.)
* When alignment checking is enabled (<code>[[EFLAGS]].AC=1</code>), AVX instructions with misaligned 128-bit or 256-bit memory operands, and the SSE4.2 <code>PCMP*STR*</code> instructions with misaligned 128-bit memory operands, will cause #AC (alignment check) exceptions on AMD64<ref>{{cite book |publisher=AMD |url=https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf |title=AMD64 Architecture Programmer’s Manual Volume 2: System Programming |id=pub.no. 24593, rev 3.42 |date=March 2024 |at=section 8.2.17 on page 257 |archive-url=https://web.archive.org/web/20250405225925/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24593.pdf |archive-date=5 April 2025 |url-status=live}}</ref> but not Intel&nbsp;64.<ref>{{cite book |publisher=Intel |url=https://cdrdv2-public.intel.com/851056/253665-087-sdm-vol-1.pdf |title=Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 1 |id=order no. 253665-087US |date=March 2025 |at=section 14.9 on page 379 |archive-url=https://web.archive.org/web/20250404141850/https://cdrdv2-public.intel.com/851056/253665-087-sdm-vol-1.pdf |archive-date=4 April 2025 |url-status=live}}</ref>
* The <code>0F 0D /r</code> opcode with the [[ModR/M]] byte's Mod field set to <code>11b</code> is a Reserved-[[NOP (code)|NOP]] on Intel&nbsp;64<ref>{{cite book |publisher=Intel |url=https://cdrdv2-public.intel.com/843857/253669-sdm-vol-3b-dec-24.pdf |title=Intel 64 and IA-32 Architectures Software Developer's Manual, volume 3B |id=order no. 253669-086US |date=December 2024 |at=chapter 24.15, page 426 |archive-url=https://web.archive.org/web/20250111122148/https://cdrdv2-public.intel.com/843857/253669-sdm-vol-3b-dec-24.pdf |archive-date=11 January 2025 |url-status=live}}</ref> but will cause #UD (invalid-opcode exception) on AMD64.<ref>{{cite book |publisher=AMD |url=https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf |title=AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions |id=order no. 24594, rev 3.36 |date=March 2024 |at=see description of <code>PREFETCHW</code> instruction on page 283 |archive-url=https://web.archive.org/web/20241229222758/https://www.amd.com/content/dam/amd/en/documents/processor-tech-docs/programmer-references/24594.pdf |archive-date=29 December 2024 |url-status=live}}</ref> 
* The ordering guarantees provided by some [[Memory barrier|memory ordering instructions]] such as <code>LFENCE</code> and <code>MFENCE</code> differ between Intel&nbsp;64 and AMD64:
** <code>LFENCE</code> is dispatch-serializing (enabling it to be used as a [[Speculative execution|speculation]] fence) on Intel&nbsp;64 but is not architecturally guaranteed to be dispatch-serializing on AMD64.<ref>{{cite web |author=Hadi Brais |url=https://hadibrais.wordpress.com/2018/05/14/the-significance-of-the-x86-lfence-instruction/ |title=The Significance of the x86 LFENCE Instruction |date=14 May 2018 |archive-url=https://web.archive.org/web/20230610045406/https://hadibrais.wordpress.com/2018/05/14/the-significance-of-the-x86-lfence-instruction/ |archive-date=10 June 2023 |url-status=live}}</ref>
** <code>MFENCE</code> is a fully serializing instruction (including instruction fetch serialization) on AMD64 but not Intel&nbsp;64.
** The <code>MOV</code> to CR8 and <code>INVPCID</code> instructions are serializing on AMD64 but not Intel&nbsp;64.
** The <code>LMSW</code> instruction is serializing on Intel&nbsp;64 but not AMD64.
** <code>WRMSR</code> to the [[x2APIC]] ICR (Interrupt Command Register; MSR <code>830h</code>) is commonly used to produce an IPI ([[Inter-processor interrupt]]) — on Intel&nbsp;64<ref>{{cite mailing list |mailing-list=linux-kernel@vger.kernel.org |url=https://lore.kernel.org/all/20210208145812.351639855@linuxfoundation.org/ |title=(PATCH 5.4 55/65) x86/apic: Add extra serialization for non-serializing MSRs |author=Greg Kroah-Hartman |date=8 February 2021}}</ref> but not AMD64<ref>{{cite web |website=Linux kernel Git repository |url=https://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git/commit/?h=x86/cpu&id=04c3024560d3a14acd18d0a51a1d0a89d29b7eb5 |title=git commit: x86/barrier: Do not serialize MSR accesses on AMD |date=13 November 2023}}</ref> CPUs, such an IPI can be reordered before an older memory store.
** On recent AMD64 processors ([[Zen 4]] and later), <code>WRMSR</code> to the <code>FS_BASE</code>, <code>GS_BASE</code> and <code>KernelGSBase</code> MSRs is non-serializing.<ref name="amd_56713_p116">{{cite web |publisher=AMD |url=https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip |title=PPR for AMD Family 19h Model 61h, Revision B1 processors |id=document no. 56713, rev 3.05, mar 8 2023 |page=116 |archive-url=https://web.archive.org/web/20230425231817/https://www.amd.com/system/files/TechDocs/56713-B1_3.05.zip |archive-date=April 25, 2023 |url-status=live}}</ref> On Intel&nbsp;64 processors as well as older AMD64 processors, <code>WRMSR</code> to these MSRs is serializing.

=== Older implementations ===
{{update section|reason=future tense relating to processors that have been out for years, dates with day and month but no year|date=January 2023}}
* The AMD64 processors prior to Revision F<ref>{{cite web |title=Live Migration with AMD-V™ Extended Migration Technology |url=http://developer.amd.com/wordpress/media/2012/10/43781-3.00-PUB_Live-Virtual-Machine-Migration-on-AMD-processors.pdf |website=developer.amd.com |access-date=June 30, 2022 |archive-date=December 6, 2022 |archive-url=https://web.archive.org/web/20221206025751/http://developer.amd.com/wordpress/media/2012/10/43781-3.00-PUB_Live-Virtual-Machine-Migration-on-AMD-processors.pdf |url-status=live }}</ref> (distinguished by the switch from [[DDR SDRAM|DDR]] to [[DDR2 SDRAM|DDR2]] memory and new sockets [[Socket AM2|AM2]], [[Socket F|F]] and [[Socket S1|S1]]) of 2006 lacked the <code>CMPXCHG16B</code> instruction, which is an extension of the <code>CMPXCHG8B</code> instruction present on most post-[[80486]] processors. Similar to <code>CMPXCHG8B</code>, <code>CMPXCHG16B</code> allows for [[atomic operation]]s on octa-words (128-bit values). This is useful for parallel algorithms that use [[compare and swap]] on data larger than the size of a pointer, common in [[lock-free and wait-free algorithms]]. Without <code>CMPXCHG16B</code> one must use workarounds, such as a [[critical section]] or alternative lock-free approaches.<ref>{{cite web|url=http://www.research.ibm.com/people/m/michael/disc-2004.pdf|title=Practical Lock-Free and Wait-Free LL/SC/VL Implementations Using 64-Bit CAS|author=Maged M. Michael|publisher=IBM|access-date=January 21, 2014|archive-date=May 2, 2013|archive-url=https://web.archive.org/web/20130502033436/http://www.research.ibm.com/people/m/michael/disc-2004.pdf|url-status=dead}}</ref> Its absence also prevents 64-bit [[Microsoft Windows|Windows]] prior to Windows 8.1 from having a [[user-mode]] address space larger than 8&nbsp;[[tebibyte|TiB]].<ref>{{cite web|url=https://blogs.msdn.microsoft.com/oldnewthing/20040817-00/?p=38153#comment-204583|title=Why is the virtual address space 4GB anyway?|website=The Old New Thing|author=darwou|date=August 20, 2004|publisher=Microsoft|access-date=March 25, 2017|archive-date=March 26, 2017|archive-url=https://web.archive.org/web/20170326140218/https://blogs.msdn.microsoft.com/oldnewthing/20040817-00/?p=38153#comment-204583|url-status=live}}</ref> All 64-bit versions of Windows since [[Windows 8.1]] require the instruction.<ref name="CPUinsts8.1">{{cite web
|url=http://windows.microsoft.com/en-us/windows-8/system-requirements
|title=System Requirements—Windows 8.1
|quote=To install a 64-bit OS on a 64-bit PC, your processor needs to support CMPXCHG16b, PrefetchW, and LAHF/SAHF.
|access-date=April 27, 2014
|archive-date=April 28, 2014
|archive-url=https://web.archive.org/web/20140428223434/http://windows.microsoft.com/en-us/windows-8/system-requirements
|url-status=live
}}</ref>
* Early AMD64 and Intel&nbsp;64 CPUs lacked <code>LAHF</code> and <code>SAHF</code> instructions in 64-bit mode. AMD introduced these instructions (also in 64-bit mode) with their [[90 nm process|90&nbsp;nm]] (revision&nbsp;D) processors, starting with Athlon&nbsp;64 in October 2004.<ref>{{cite web |last1=Petkov |first1=Borislav |title=Re: [PATCH v2] x86: clear incorrectly forced X86_FEATURE_LAHF_LM flag |url=https://lkml.org/lkml/2009/8/10/159 |website=[[Linux kernel mailing list]] |date=10 August 2009 |access-date=June 30, 2022 |archive-date=January 11, 2023 |archive-url=https://web.archive.org/web/20230111050420/https://lkml.org/lkml/2009/8/10/159 |url-status=live }}</ref><ref>{{Cite web |url=http://support.amd.com/us/Processor_TechDocs/25759.pdf 
|title=Revision Guide for AMD Athlon 64 and AMD Opteron Processors |publisher=AMD |access-date=July 18, 2009 |archive-date=August 24, 2009 |archive-url=https://web.archive.org/web/20090824002650/http://support.amd.com/us/Processor_TechDocs/25759.pdf |url-status=live }}</ref> Intel introduced the instructions in October 2005 with the 0F47h and later revisions of [[NetBurst]].{{Refn|0F47h debuted in the B0 [[Stepping level|stepping]] of [[Pentium D]] on October 21,<ref>{{cite web |title=Product Change Notification 105224 - 01 |url=http://developer.intel.com/design/pcn/Processors/D0105224.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20051117160702/http://developer.intel.com/design/pcn/Processors/D0105224.pdf |archive-date=2005-11-17}}</ref><ref>{{cite web |title=Intel® Pentium® D Processor 800 Sequence and Intel® Pentium® Processor Extreme Edition 840 Specification Update |url=https://www.intel.com/Assets/PDF/specupdate/306832.pdf |access-date=June 30, 2022 |archive-date=May 18, 2021 |archive-url=https://web.archive.org/web/20210518130540/https://www.intel.com/assets/pdf/specupdate/306832.pdf |url-status=live }}</ref> but 0F48h which also supports LAHF/SAHF launched on October 10 in the [[Xeon#"Paxville_DP"|dual-core Xeon]].<ref>{{cite web |title=Intel Xeon 2.8 GHz - NE80551KG0724MM / BX80551KG2800HA |url=https://www.cpu-world.com/CPUs/Xeon/Intel-Xeon%202.8%20GHz%20-%20NE80551KG0724MM%20(BX80551KG2800HA).html |website=CPU-World |access-date=June 30, 2022 |archive-date=June 28, 2020 |archive-url=https://web.archive.org/web/20200628213257/http://www.cpu-world.com/CPUs/Xeon/Intel-Xeon%202.8%20GHz%20-%20NE80551KG0724MM%20(BX80551KG2800HA).html |url-status=live }}</ref>{{Efn|[[The Register]] reported that the stepping&nbsp;G1 (0F49h) of Pentium&nbsp;4 will sample on October 17 and ship in volume on November 14.<ref>{{cite web |last1=Smith |first1=Tony |title=Intel tweaks EM64T for full AMD64 compatibility |url=https://www.theregister.com/2005/08/23/intel_fixes_em64t/ |website=[[The Register]] |date=23 August 2005 |access-date=June 30, 2022 |archive-date=June 30, 2022 |archive-url=https://web.archive.org/web/20220630200453/https://www.theregister.com/2005/08/23/intel_fixes_em64t/ |url-status=live }}</ref> However, Intel's document says that samples are available on September 9, whereas October 17 is the "date of first availability of post-conversion material", which Intel defines as "the projected date that a customer may expect to receive the post-conversion materials. ... customers should be prepared to receive the post-converted materials on this date".<ref>{{cite web |title=Product Change Notification 105271 – 00 |url=http://developer.intel.com/design/pcn/Processors/D0105271.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20051117162258/http://developer.intel.com/design/pcn/Processors/D0105271.pdf |archive-date=2005-11-17}}</ref>}}}} All 64-bit versions of Windows since Windows 8.1 require this feature.<ref name="CPUinsts8.1" />
* Early Intel CPUs with Intel&nbsp;64 also lack the [[NX bit]] of the AMD64 architecture. It was added in the stepping E0 (0F41h) Pentium 4 in October 2004.<ref>{{cite web |title=Product Change Notification 104101 – 00 |url=http://developer.intel.com/design/pcn/Processors/D0104101.pdf |publisher=Intel |archive-url=https://web.archive.org/web/20040716131656/http://developer.intel.com/design/pcn/Processors/D0104101.pdf |archive-date=2004-07-16}}</ref> 64-bit versions of Windows since Windows 8.1 require this feature.<ref name="CPUinsts8.1" />
* Early Intel&nbsp;64 implementations had a 36-bit (64&nbsp;GiB) physical addressing of memory while original AMD64 implementations had a 40-bit (1&nbsp;[[Tebibyte|TiB]]) physical addressing. Intel used the 40-bit physical addressing first on Xeon MP ([[Xeon#Cranford and Potomac|Potomac]]), launched on 29 March 2005.<ref>{{cite web |url=https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/64-bit-xeon-mp-8mb-l3-cache-datasheet.pdf |title=64-bit Intel® Xeon™ Processor MP with up to 8MB L3 Cache Datasheet |access-date=November 17, 2022 |archive-date=November 17, 2022 |archive-url=https://web.archive.org/web/20221117025116/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/64-bit-xeon-mp-8mb-l3-cache-datasheet.pdf |url-status=live }}</ref> The difference is not a difference of the user-visible ISAs. In 2007 [[AMD 10h]]-based Opteron was the first to provide a 48-bit (256&nbsp;TiB) physical address space.<ref>{{cite web |title=Justin Boggs's at Microsoft PDC 2008 |url=https://zbook.org/read/70903_justin-boggs-isv-engineering-developer-relations-manager.html |page=5 |access-date=November 17, 2022 |archive-date=November 17, 2022 |archive-url=https://web.archive.org/web/20221117025143/https://zbook.org/read/70903_justin-boggs-isv-engineering-developer-relations-manager.html |url-status=live }}</ref><ref>{{cite web |last1=Waldecker |first1=Brian |title=AMD Opteron Multicore Processors |url=https://www.nersc.gov/assets/Uploads/AMDMultiCoreCrayNersc020110.pdf |page=13 |access-date=November 17, 2022 |archive-date=December 13, 2022 |archive-url=https://web.archive.org/web/20221213095258/https://www.nersc.gov/assets/Uploads/AMDMultiCoreCrayNersc020110.pdf |url-status=live }}</ref> Intel 64's physical addressing was extended to 44 bits (16&nbsp;TiB) in Nehalem-EX in 2010<ref>{{cite web |url=https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf |title=Intel® Xeon® Processor 7500 Series Datasheet, Volume 2 |access-date=November 17, 2022 |archive-date=November 17, 2022 |archive-url=https://web.archive.org/web/20221117025118/https://www.intel.com/content/dam/www/public/us/en/documents/datasheets/xeon-processor-7500-series-vol-2-datasheet.pdf |url-status=live }}</ref> and to 46 bits (64&nbsp;TiB) in Sandy Bridge E in 2011.<ref>{{cite web |quote=Intel 64 architecture increases the linear address space for software to 64 bits and supports physical address space up to 46 bits. |volume=1 |page=2{{hyp}}21 |url=http://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-manual-325462.html |title=Intel 64 and IA-32 Architectures Software Developer's Manual |date=September 2014 |archive-url=https://web.archive.org/web/20190514124207/https://www.intel.com/content/www/us/en/architecture-and-technology/64-ia-32-architectures-software-developer-manual-325462.html |archive-date=May 14, 2019 |url-status=dead}}</ref><ref>{{cite web |last1=Logan |first1=Tom |title=Intel Core i7-3960X Review |url=https://overclock3d.net/reviews/cpu_mainboard/intel_core_i7-3960x_review/2 |access-date=1 July 2022 |date=14 November 2011 |archive-date=March 28, 2016 |archive-url=https://web.archive.org/web/20160328235235/http://overclock3d.net/reviews/cpu_mainboard/intel_core_i7-3960x_review/2 |url-status=live }}</ref> With the Ice Lake 3rd gen Xeon Scalable processors, Intel increased the virtual addressing to 57 bits (128&nbsp;[[Pebibyte|PiB]]) and physical to 52 bits (4&nbsp;PiB) in 2021, necessitating a [[Intel 5-level paging|5-level paging]].<ref>{{cite web |last1=Ye |first1=Huaisheng |title=Introduction to 5-Level Paging in 3rd Gen Intel Xeon Scalable Processors with Linux |url=https://lenovopress.lenovo.com/lp1468.pdf |publisher=Lenovo |access-date=1 July 2022 |archive-date=May 26, 2022 |archive-url=https://web.archive.org/web/20220526220222/https://lenovopress.lenovo.com/lp1468.pdf |url-status=live }}</ref> The following year AMD64 added the same in 4th generation [[EPYC]] (Genoa).<ref>{{cite web |last1=Kennedy |first1=Patrick |title=AMD EPYC Genoa Gaps Intel Xeon in Stunning Fashion |url=https://www.servethehome.com/amd-epyc-genoa-gaps-intel-xeon-in-stunning-fashion/2/ |website=ServeTheHome |page=2 |date=November 10, 2022 |access-date=November 17, 2022 |archive-date=November 17, 2022 |archive-url=https://web.archive.org/web/20221117025115/https://www.servethehome.com/amd-epyc-genoa-gaps-intel-xeon-in-stunning-fashion/2/ |url-status=live }}</ref> Non-server CPUs retain smaller address spaces for longer.
* On all AMD64 processors, the [[find first set|<code>BSF</code>]] and [[find first set|<code>BSR</code>]] instructions will, when given a source value of 0, leave their destination register unmodified. This is mostly the case on Intel&nbsp;64 processors as well, except that on some older Intel&nbsp;64 CPUs, executing these instructions with an operand size of 32 bits will clear the top 32 bits of their destination register even with a source value of 0 (with the low 32 bits kept unchanged.)<ref>{{cite book |publisher=Intel |url=https://cdrdv2-public.intel.com/843829/325383-sdm-vol-2abcd-dec-24.pdf |title=Intel 64 and IA-32 Architectures Software Developer's Manual, Volume 2 |id=order no. 325383-086US |date=December 2024 |at=see entries on <code>BSF</code> and <code>BSR</code> instructions on pages 227 and 229 (footnote 1) |archive-url=https://web.archive.org/web/20250102001351/https://cdrdv2-public.intel.com/843829/325383-sdm-vol-2abcd-dec-24.pdf |archive-date=2 January 2025 |url-status=live}}</ref>
* AMD64 processors since [[Opteron]] Rev. E and [[Athlon 64]] Rev. D reintroduced limited support for segmentation, via the Long Mode Segment Limit Enable (LMSLE) bit, to ease [[x86 virtualization#64-bit|virtualization]] of 64-bit guests.<ref>{{cite web |url= http://www.pagetable.com/?p=25 |title= How retiring segmentation in AMD64 long mode broke VMware |publisher= Pagetable.com |date= November 9, 2006 |access-date= May 2, 2010 |archive-date= July 18, 2011 |archive-url= https://web.archive.org/web/20110718104331/http://www.pagetable.com/?p=25 |url-status= live }}</ref><ref>{{cite web |url= http://download3.vmware.com/vmworld/2005/pac346.pdf |title= VMware and CPU Virtualization Technology |publisher= VMware |access-date= September 8, 2010 |archive-date= July 17, 2011 |archive-url= https://web.archive.org/web/20110717231306/http://download3.vmware.com/vmworld/2005/pac346.pdf |url-status= live }}</ref> LMSLE support was removed in the Zen 3 processor.<ref>{{Cite web |title=Linux-Kernel Archive: [PATCH 2/5] KVM: svm: Disallow EFER.LMSLE on hardware that doesn't support it |url=https://lkml.indiana.edu/hypermail/linux/kernel/2209.2/00025.html |access-date=2023-11-03 |website=lkml.indiana.edu}}</ref>
* On all Intel&nbsp;64 processors, <code>CLFLUSH</code> is ordered with respect to <code>SFENCE</code> — this is also the case on newer AMD64 processors (Zen 1 and later). On older AMD64 processors, imposing ordering on the <code>CLFLUSH</code> instruction instead required <code>MFENCE</code>.
* On older AMD64 processors, the <code>XSAVE</code>/<code>XRSTOR</code> instructions would abstain from saving/restoring x87 error pointers (FCS/FIP, FDS/FDP, FOP) unless an unmasked pending x87 exception was present. On Intel&nbsp;64 processors and newer AMD64 processors (Zen 1 and later), these error pointers are always saved and restored. (This Intel/AMD difference continues to exist for the <code>FXSAVE</code>/<code>FXRSTOR</code> instructions, though.)

== Adoption ==
[[File:Processor families in TOP500 supercomputers.svg|thumb|350x350px|An area chart showing the representation of different families of microprocessors in the TOP500 supercomputer ranking list, from 1993 to 2020<ref>{{cite web |url=http://www.top500.org/statistics |title=Statistics &#124; TOP500 Supercomputer Sites |publisher=Top500.org |access-date=March 22, 2014 |archive-date=March 19, 2014 |archive-url=https://web.archive.org/web/20140319023302/http://www.top500.org/statistics/ |url-status=live }}</ref>]]

In [[supercomputer]]s tracked by [[TOP500]], the appearance of 64-bit extensions for the x86 architecture enabled 64-bit x86 processors by AMD and Intel to replace most RISC processor architectures previously used in such systems (including [[PA-RISC]], [[SPARC]], [[DEC Alpha|Alpha]] and others), as well as 32-bit x86, even though Intel itself initially tried unsuccessfully to replace x86 with a new incompatible 64-bit architecture in the [[Itanium]] processor.

{{As of|2023}}, a [[Hewlett Packard Enterprise|HPE]] [[Epyc|EPYC]]-based supercomputer called [[Frontier (supercomputer)|Frontier]] is number one. The first ARM-based supercomputer appeared on the list in 2018<ref>{{Cite web|url=https://www.top500.org/statistics/sublist/|title=Sublist Generator {{!}} TOP500 Supercomputer Sites|website=www.top500.org|access-date=2018-12-06|archive-date=December 7, 2018|archive-url=https://web.archive.org/web/20181207200508/https://www.top500.org/statistics/sublist/|url-status=live}}</ref> and, in recent years, non-CPU architecture co-processors ([[General-purpose computing on graphics processing units (software)|GPGPU]]) have also played a big role in performance. Intel's [[Xeon Phi#Knights Corner|Xeon Phi "Knights Corner"]] coprocessors, which implement a subset of x86-64 with some vector extensions,<ref>{{cite web|url=https://software.intel.com/sites/default/files/forum/278102/327364001en.pdf|title=Intel® Xeon PhiTM Coprocessor Instruction Set Architecture Reference Manual|at=section B.2 Intel Xeon Phi coprocessor 64 bit Mode Limitations|publisher=Intel|date=September 7, 2012|access-date=May 21, 2014|archive-date=May 21, 2014|archive-url=https://web.archive.org/web/20140521050107/https://software.intel.com/sites/default/files/forum/278102/327364001en.pdf|url-status=live}}</ref> are also used, along with x86-64 processors, in the [[Tianhe-2]] supercomputer.<ref>{{cite web|url=http://newsroom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-computing-technologies|title=Intel Powers the World's Fastest Supercomputer, Reveals New and Future High Performance Computing Technologies|access-date=June 21, 2013|archive-date=June 22, 2013|archive-url=https://web.archive.org/web/20130622162239/http://newsroom.intel.com/community/intel_newsroom/blog/2013/06/17/intel-powers-the-worlds-fastest-supercomputer-reveals-new-and-future-high-performance-computing-technologies|url-status=live}}</ref>
{{Clear}}

== Operating system compatibility and characteristics ==
The following operating systems and releases support the x86-64 architecture in [[long mode]].

=== BSD ===
==== DragonFly BSD ====
Preliminary infrastructure work was started in February 2004 for a x86-64 port.<ref name=dfly-amd64-prelim>{{cite web |url= http://leaf.dragonflybsd.org/mailarchive/commits/2004-02/msg00011.html |title= cvs commit: src/sys/amd64/amd64 genassym.c src/sys/amd64/include asm.h atomic.h bootinfo.h coredump.h cpufunc.h elf.h endian.h exec.h float.h fpu.h frame.h globaldata.h ieeefp.h limits.h lock.h md_var.h param.h pcb.h pcb_ext.h pmap.h proc.h profile.h psl.h ... |access-date= May 3, 2009 |archive-date= December 4, 2008 |archive-url= https://web.archive.org/web/20081204123450/http://leaf.dragonflybsd.org/mailarchive/commits/2004-02/msg00011.html |url-status= live }}</ref> This development later stalled. Development started again during July 2007<ref name=dfly-amd64-noah>{{cite web |url= http://leaf.dragonflybsd.org/mailarchive/users/2007-07/msg00016.html |title= AMD64 port |access-date= May 3, 2009 |archive-date= May 18, 2010 |archive-url= https://web.archive.org/web/20100518104312/http://leaf.dragonflybsd.org/mailarchive/users/2007-07/msg00016.html |url-status= live }}</ref>
and continued during [[Google Summer of Code]] 2008 and SoC 2009.<ref name=dfly-amd64-soc2008>{{cite web |url= http://www.dragonflybsd.org/docs/developer/GoogleSoC2008/ |title= DragonFlyBSD: GoogleSoC2008 |access-date= May 3, 2009 |archive-date= April 27, 2009 |archive-url= https://web.archive.org/web/20090427115711/http://www.dragonflybsd.org/docs/developer/GoogleSoC2008/ |url-status= live }}</ref><ref name=dfly-amd64-soc2009>{{cite web |url= http://leaf.dragonflybsd.org/mailarchive/users/2009-04/msg00091.html |title= Summer of Code accepted students |access-date= May 3, 2009 |archive-date= September 4, 2010 |archive-url= https://web.archive.org/web/20100904021545/http://leaf.dragonflybsd.org/mailarchive/users/2009-04/msg00091.html |url-status= live }}</ref> The first official release to contain x86-64 support was version 2.4.<ref name=dflyamd64-release>{{cite web |url= http://www.dragonflybsd.org/release24/ |title= DragonFlyBSD: release24 |access-date= May 3, 2009 |archive-date= September 23, 2009 |archive-url= https://web.archive.org/web/20090923152727/http://www.dragonflybsd.org/release24/ |url-status= live }}</ref>

==== FreeBSD ====
[[FreeBSD]] first added x86-64 support under the name "amd64" as an experimental architecture in 5.1-RELEASE in June 2003. It was included as a standard distribution architecture as of 5.2-RELEASE in January 2004. Since then, FreeBSD has designated it as a Tier&nbsp;1 platform. The 6.0-RELEASE version cleaned up some quirks with running x86 executables under amd64, and most drivers work just as they do on the x86 architecture. Work is currently being done to integrate more fully the x86 [[application binary interface]] (ABI), in the same manner as the Linux 32-bit ABI compatibility currently works.

==== NetBSD ====
x86-64 architecture support was first committed to the [[NetBSD]] source tree on June 19, 2001. As of NetBSD&nbsp;2.0, released on December 9, 2004, ''NetBSD/amd64'' is a fully integrated and supported port.
32-bit code is still supported in 64-bit mode, with a netbsd-32 kernel compatibility layer for 32-bit syscalls. The NX bit is used to provide non-executable stack and heap with per-page granularity (segment granularity being used on 32-bit x86).

==== OpenBSD ====
[[OpenBSD]] has supported AMD64 since OpenBSD 3.5, released on May 1, 2004. Complete in-tree implementation of AMD64 support was achieved prior to the hardware's initial release because AMD had loaned several machines for the project's [[hackathon]] that year. OpenBSD developers have taken to the platform because of its support for the [[NX bit]], which allowed for an easy implementation of the [[W^X]] feature.

The code for the AMD64 port of OpenBSD also runs on Intel 64 processors which contains cloned use of the AMD64 extensions, but since Intel left out the page table NX bit in early Intel 64 processors, there is no W^X capability on those Intel CPUs; later Intel 64 processors added the NX bit under the name "XD bit". [[Symmetric multiprocessing]] (SMP) works on OpenBSD's AMD64 port, starting with release 3.6 on November 1, 2004.

=== DOS ===
{{More citations needed|date=December 2022}}
It is possible to enter [[long mode]] under [[DOS]] without a DOS extender,<ref>{{Cite web |url=http://www.turboirc.com/asm |title=Tutorial for entering protected and long mode from DOS |access-date=July 6, 2008 |archive-url=https://web.archive.org/web/20170222181811/http://www.turboirc.com/asm/ |archive-date=February 22, 2017 |url-status=dead |df=mdy-all }}</ref> but the user must return to real mode in order to call BIOS or DOS interrupts.

It may also be possible to enter [[long mode]] with a [[DOS extender]] similar to [[DOS/4GW]], but more complex since x86-64 lacks [[virtual 8086 mode]]. DOS itself is not aware of that, and no benefits should be expected unless running DOS in an emulation with an adequate virtualization driver backend, for example: the mass storage interface.

=== Linux ===
{{See also|Comparison of Linux distributions#Instruction set architecture support}}

[[Linux]] was the first operating system kernel to run the x86-64 architecture in [[long mode]], starting with the 2.4 version in 2001 (preceding the hardware's availability).<ref>{{cite web |title=Porting Linux to x86-64 |author=Andi Kleen |url=http://www.x86-64.org/pipermail/announce/2001-June/000020.html |date=June 26, 2001 |quote=Status: The kernel, compiler, tool chain work. The kernel boots and work on simulator and is used for porting of userland and running programs |url-status=dead |archive-url=https://web.archive.org/web/20100910014057/http://www.x86-64.org/pipermail/announce/2001-June/000020.html |archive-date=September 10, 2010 |df=mdy }}</ref><ref>{{cite web |url= http://www.halobates.de/ |title= Andi Kleen's Page |author= Andi Kleen |quote= This was the original paper describing the Linux x86-64 kernel port back when x86-64 was only available on simulators. |access-date= August 21, 2009 |archive-date= December 7, 2009 |archive-url= https://web.archive.org/web/20091207131536/http://www.halobates.de/ |url-status= live }}</ref> Linux also provides backward compatibility for running 32-bit executables. This permits programs to be recompiled into long mode while retaining the use of 32-bit programs. Current Linux distributions ship with x86-64-native kernels and [[userland (computing)|userlands]]. Some, such as [[Arch Linux]],<ref>{{cite web |url= https://wiki.archlinux.org/index.php/Arch64_FAQ |title= Arch64 FAQ |date= April 23, 2012 |quote= You can either use the multilib packages or a i686 chroot. |access-date= May 11, 2012 |archive-date= May 14, 2012 |archive-url= https://web.archive.org/web/20120514030334/https://wiki.archlinux.org/index.php/Arch64_FAQ |url-status= live }}</ref> [[SUSE Linux|SUSE]], [[Mandriva Linux|Mandriva]], and [[Debian]], allow users to install a set of 32-bit components and libraries when installing off a 64-bit distribution medium, thus allowing most existing 32-bit applications to run alongside the 64-bit OS.

[[x32 ABI]] (Application Binary Interface), introduced in Linux 3.4, allows programs compiled for the x32 ABI to run in the 64-bit mode of x86-64 while only using 32-bit pointers and data fields.<ref name="x32ABIHOnline">{{cite news
 |url = http://www.h-online.com/open/features/Kernel-Log-x32-ABI-gets-around-64-bit-drawbacks-1342061.html
 |archive-url = https://web.archive.org/web/20111028081253/http://www.h-online.com/open/features/Kernel-Log-x32-ABI-gets-around-64-bit-drawbacks-1342061.html
 |archive-date = October 28, 2011
 |title = Kernel Log: x32 ABI gets around 64-bit drawbacks
 |publisher = www.h-online.com
 |author = Thorsten Leemhuis
 |date = September 13, 2011
 |access-date = November 1, 2011
 |url-status = dead
 |df = mdy-all
 }}</ref><ref name="x32ABILinuxPlumbers">{{cite news
 |url       = http://linuxplumbersconf.org/2011/ocw/sessions/531
 |title       = x32 - a native 32-bit ABI for x86-64
 |publisher       = linuxplumbersconf.org
 |access-date       = November 1, 2011
 |archive-date       = May 5, 2012
 |archive-url       = https://web.archive.org/web/20120505022446/http://www.linuxplumbersconf.org/2011/ocw/sessions/531
 |url-status       = live
 }}</ref><ref name="x32ABIDevelopmentGroup">{{cite news
 |url       = http://sites.google.com/site/x32abi/
 |title       = x32-abi
 |publisher       = Google Sites
 |access-date       = November 1, 2011
 |archive-date       = October 30, 2011
 |archive-url       = https://web.archive.org/web/20111030054600/http://sites.google.com/site/x32abi/
 |url-status       = live
 }}</ref>
Though this limits the program to a virtual address space of 4&nbsp;GiB, it also decreases the memory footprint of the program and in some cases can allow it to run faster.<ref name="x32ABIHOnline"/><ref name="x32ABILinuxPlumbers"/><ref name="x32ABIDevelopmentGroup"/>

64-bit Linux allows up to 128&nbsp;[[Tebibyte|TiB]] of virtual address space for individual processes, and can address approximately 64&nbsp;TiB of physical memory, subject to processor and system limitations,<ref name="DebianAMD64">{{cite news
 |url       = http://www.debian.org/ports/amd64/
 |title       = AMD64 Port
 |publisher       = debian.org
 |access-date       = October 29, 2011
 |archive-date       = September 26, 2019
 |archive-url       = https://web.archive.org/web/20190926060654/https://www.debian.org/ports/amd64/
 |url-status       = live
 }}</ref> or up to 128&nbsp;PiB (virtual) and 4&nbsp;PiB (physical) with 5-level paging enabled.<ref name="Kernel5LevelPaging">
{{cite news
 |url       = https://docs.kernel.org/arch/x86/x86_64/5level-paging.html
 |title       = 5-level paging
 |publisher       = kernel.org
 |access-date       = February 7, 2024
 }}</ref>

=== macOS ===
Mac OS X 10.4.7 and higher versions of [[Mac OS X Tiger|Mac OS X 10.4]] run 64-bit command-line tools using the POSIX and math libraries on 64-bit Intel-based machines, just as all versions of Mac OS X 10.4 and 10.5 run them on 64-bit PowerPC machines. No other libraries or frameworks work with 64-bit applications in Mac OS X 10.4.<ref>{{cite web
 |url        = https://developer.apple.com/releasenotes/DeveloperTools/RN-CompilerTools/index.html
 |archive-url = https://web.archive.org/web/20090422045532/http://developer.apple.com/releasenotes/DeveloperTools/RN-CompilerTools/index.html
 |archive-date= April 22, 2009
 |title      = Apple – Mac OS X Xcode 2.4 Release Notes: Compiler Tools
 |publisher  = [[Apple Inc.]]
 |date       = April 11, 2007
 |access-date = November 19, 2012}}</ref>
The kernel, and all kernel extensions, are 32-bit only.

[[Mac OS X Leopard|Mac OS X 10.5]] supports 64-bit GUI applications using [[Cocoa (API)|Cocoa]], [[Quartz (graphics layer)|Quartz]], [[OpenGL]], and [[X11]] on 64-bit Intel-based machines, as well as on 64-bit [[PowerPC]] machines.<ref>{{cite web
 |url        = https://www.apple.com/macosx/technology/64bit.html
 |archive-url = https://web.archive.org/web/20090112055017/http://www.apple.com/macosx/technology/64bit.html
 |archive-date= January 12, 2009
 |title      = Apple – Mac OS X Leopard – Technology - 64-bit
 |publisher  = Apple Inc.
 |access-date = November 19, 2012}}</ref>
All non-GUI libraries and frameworks also support 64-bit applications on those platforms. The kernel, and all kernel extensions, are 32-bit only.

[[Mac OS X Snow Leopard|Mac OS X 10.6]] is the first version of [[macOS]] that supports a 64-bit [[kernel (operating system)|kernel]]. However, not all 64-bit computers can run the 64-bit kernel, and not all 64-bit computers that can run the 64-bit kernel will do so by default.<ref>{{cite web
 |title      = Mac OS X v10.6: Macs that use the 64-bit kernel
 |url      = http://support.apple.com/kb/HT3770
 |publisher      = Apple Inc.
 |access-date      = November 29, 2012
 |archive-date      = August 31, 2009
 |archive-url      = https://web.archive.org/web/20090831113241/http://support.apple.com/kb/HT3770
 |url-status      = live
 }}</ref>
The 64-bit kernel, like the 32-bit kernel, supports 32-bit applications; both kernels also support 64-bit applications. 32-bit applications have a virtual address space limit of 4&nbsp;GiB under either kernel.<ref name="arstechnicaMacOSX64bit">{{cite web
 |url          = https://arstechnica.com/apple/reviews/2009/08/mac-os-x-10-6.ars/5
 |title        = Mac OS X 10.6 Snow Leopard: the Ars Technica review
 |publisher    = Ars Technica LLC
 |author       = John Siracusa
 |access-date  = June 20, 2010
 |archive-date = October 9, 2009
 |archive-url  = https://web.archive.org/web/20091009161632/http://arstechnica.com/apple/reviews/2009/08/mac-os-x-10-6.ars/5
 |url-status   = live
}}</ref><ref name="Apple64Bit">{{cite web
 |url        = https://www.apple.com/macosx/technology/#sixtyfourbit
 |archive-url = https://web.archive.org/web/20110328170107/http://www.apple.com/macosx/technology/#sixtyfourbit
 |archive-date= March 28, 2011
 |title      = Mac OS X Technology
 |publisher  = Apple Inc.
 |access-date = November 19, 2012}}</ref>  The 64-bit kernel does not support 32-bit [[loadable kernel module|kernel extensions]], and the 32-bit kernel does not support 64-bit kernel extensions.

[[OS X Mountain Lion|OS X 10.8]] includes only the 64-bit kernel, but continues to support 32-bit applications; it does not support 32-bit kernel extensions, however.

[[macOS Catalina|macOS 10.15]] includes only the 64-bit kernel and no longer supports 32-bit applications. This removal of support has presented a problem for [[Wine (software)|Wine]] (and the commercial version [[CrossOver]]), as it needs to still be able to run 32-bit Windows applications. The solution, termed ''wine32on64'', was to add [[thunk]]s that bring the CPU in and out of 32-bit compatibility mode in the nominally 64-bit application.<ref>{{cite web |title=So We Don't Have a Solution for Catalina...Yet |url=https://www.codeweavers.com/blog/jschmid/2019/9/10/so-we-dont-have-a-solution-for-catalinayet |date=10 September 2019 |first1=J |last1=Schmid |first2=K |last2=Thomases |first3=J |last3=Ramey |first4=U |last4=Czekalla |first5=B |last5=Mathieu |first6=R |last6=Abhiram |website=CodeWeavers Blog |language=en |access-date=September 29, 2021 |archive-date=September 29, 2021 |archive-url=https://web.archive.org/web/20210929085817/https://www.codeweavers.com/blog/jschmid/2019/9/10/so-we-dont-have-a-solution-for-catalinayet |url-status=live }}</ref><ref>{{cite web |last1=Thomases |first1=Ken |title=win32 on macOS |url=https://www.winehq.org/pipermail/wine-devel/2019-December/156602.html |website=WineHQ  |date=December 11, 2019 |access-date=September 29, 2021 |archive-date=November 11, 2020 |archive-url=https://web.archive.org/web/20201111190220/https://www.winehq.org/pipermail/wine-devel/2019-December/156602.html |url-status=live }}</ref>

macOS uses the [[universal binary]] format to package 32- and 64-bit versions of application and library code into a single file; the most appropriate version is automatically selected at load time. In Mac OS X 10.6, the universal binary format is also used for the kernel and for those kernel extensions that support both 32-bit and 64-bit kernels.

=== Solaris ===
{{see also|illumos}}
[[Solaris (operating system)|Solaris]] 10 and later releases support the x86-64 architecture.

For Solaris 10, just as with the [[SPARC]] architecture, there is only one operating system image, which contains a 32-bit kernel and a 64-bit kernel; this is labeled as the "x64/x86" DVD-ROM image. The default behavior is to boot a 64-bit kernel, allowing both 64-bit and existing or new 32-bit executables to be run. A 32-bit kernel can also be manually selected, in which case only 32-bit executables will run. The <code>isainfo</code> command can be used to determine if a system is running a 64-bit kernel.

For Solaris 11, only the 64-bit kernel is provided. However, the 64-bit kernel supports both 32- and 64-bit executables, libraries, and system calls.

=== Windows ===
x64 editions of Microsoft Windows client and server—[[Windows XP Professional x64 Edition]] and [[Windows Server 2003]] x64 Edition—were released in March 2005.<ref>{{Cite press release|url=https://news.microsoft.com/2005/04/25/microsoft-raises-the-speed-limit-with-the-availability-of-64-bit-editions-of-windows-server-2003-and-windows-xp-professional/#sm.0000kw91cdgntf2kwp82ed9a9yn4e|title=Microsoft Raises the Speed Limit with the Availability of 64-Bit Editions of Windows Server 2003 and Windows XP Professional |website=Microsoft News Center |date=April 25, 2005 |access-date=January 29, 2024}}</ref> Internally they are actually the same build (5.2.3790.1830 SP1),<ref>{{Cite web|url=https://support.microsoft.com/en-gb/kb/888733|title=A description of the x64-based versions of Windows Server 2003 and of Windows XP Professional x64 Edition|website=Microsoft Support|access-date=August 14, 2016|archive-date=April 20, 2016|archive-url=https://web.archive.org/web/20160420135711/https://support.microsoft.com/en-gb/kb/888733|url-status=dead}}</ref><ref>{{Cite web|url=https://www.microsoft.com/en-us/download/details.aspx?id=3725|title=Windows Server 2003 SP1 Administration Tools Pack|website=Microsoft Download Center|access-date=August 14, 2016|archive-url=https://web.archive.org/web/20160827033240/http://www.microsoft.com/en-us/download/details.aspx?id=3725|archive-date=August 27, 2016|url-status=dead|df=mdy-all}}</ref> as they share the same source base and operating system binaries, so even system updates are released in unified packages, much in the manner as Windows 2000 Professional and Server editions for x86. [[Windows Vista]], which also has many different editions, was released in January 2007. [[Windows&nbsp;7]] was released in July 2009. [[Windows Server 2008 R2]] was sold in only x64 and Itanium editions; later versions of Windows Server only offer an x64 edition.

Versions of Windows for x64 prior to Windows 8.1 and Windows Server 2012 R2 offer the following:
* 8&nbsp;TiB of virtual address space per process, accessible from both user mode and kernel mode, referred to as the user mode address space. An x64 program can use all of this, subject to backing store limits on the system, and provided it is linked with the "large address aware" option, which is present by default.<ref name="VSdocLAA">{{cite web
 |url          = https://learn.microsoft.com/en-us/cpp/build/reference/largeaddressaware-handle-large-addresses?view=msvc-170
 |title        = /LARGEADDRESSAWARE (Handle Large Addresses)
 |quote        = The /LARGEADDRESSAWARE option tells the linker that the application can handle addresses larger than 2&nbsp;gigabytes.
 |work         = Visual Studio 2022 Documentation – MSVC Linker Reference – MSVC Linker Options
 |publisher    = Microsoft
 |access-date  = December 21, 2022
 |archive-date = December 21, 2022
 |archive-url  = https://web.archive.org/web/20221221152408/https://learn.microsoft.com/en-us/cpp/build/reference/largeaddressaware-handle-large-addresses?view=msvc-170
 |url-status   = live
}}</ref> This is a 4096-fold increase over the default 2&nbsp;GiB user-mode virtual address space offered by 32-bit Windows.<ref name="Pietrek64BitWindowsProgramming">{{cite web
 |url          = https://learn.microsoft.com/en-us/archive/msdn-magazine/2006/may/x64-starting-out-in-64-bit-windows-systems-with-visual-c
 |title        = Everything You Need To Know To Start Programming 64-Bit Windows Systems
 |publisher    = Microsoft
 |author       = [[Matt Pietrek]]
 |date         = May 2006
 |access-date  = April 18, 2023
}}</ref><ref name="MicrosoftMoveTox64">{{cite web
 |url          = https://learn.microsoft.com/en-us/previous-versions/technet-magazine/cc161043(v=msdn.10)
 |title        = Making the Move to x64
 |publisher    = Microsoft
 |author       = Chris St. Amand
 |date         = January 2006
 |access-date  = April 18, 2023
}}</ref>
* 8&nbsp;TiB of kernel mode virtual address space for the operating system.<ref name="Pietrek64BitWindowsProgramming"/> As with the user mode address space, this is a 4096-fold increase over 32-bit Windows versions. The increased space primarily benefits the file system cache and kernel mode "heaps" (non-paged pool and paged pool). Windows only uses a total of 16&nbsp;TiB out of the 256&nbsp;TiB implemented by the processors because early AMD64 processors lacked a <code>CMPXCHG16B</code> instruction.<ref>{{cite web
 |title      = Behind Windows x86-64's 44-bit Virtual Memory Addressing Limit
 |url      = http://www.alex-ionescu.com/?p=50
 |access-date      = July 2, 2009
 |archive-date      = December 23, 2008
 |archive-url      = https://web.archive.org/web/20081223145800/http://www.alex-ionescu.com/?p=50
 |url-status      = live
 }}</ref>

Under Windows 8.1 and Windows Server 2012 R2, both user mode and kernel mode virtual address spaces have been extended to 128&nbsp;TiB.<ref name="win-lim-msdn"/> These versions of Windows will not install on processors that lack the <code>CMPXCHG16B</code> instruction.

The following additional characteristics apply to all x64 versions of Windows:

* Ability to run existing 32-bit applications (<code>.exe</code> programs) and dynamic link libraries (<code>.dll</code>s) using [[WoW64]] if WoW64 is supported on that version. Furthermore, a 32-bit program, if it was linked with the "large address aware" option,<ref name="VSdocLAA"/> can use up to 4&nbsp;GiB of virtual address space in 64-bit Windows, instead of the default 2&nbsp;GiB (optional 3&nbsp;GiB with <code>/3GB</code> boot option and "large address aware" link option) offered by 32-bit Windows.<ref name="64-bitProgrammingGameDevelopers">{{cite web
 |url       = https://learn.microsoft.com/en-us/windows/win32/dxtecharts/sixty-four-bit-programming-for-game-developers#porting-applications-to-64-bit-platforms
 |title       = 64-bit programming for Game Developers
 |access-date       = April 18, 2023
 }}</ref> Unlike the use of the <code>/3GB</code> boot option on x86, this does not reduce the kernel mode virtual address space available to the operating system. 32-bit applications can, therefore, benefit from running on x64 Windows even if they are not recompiled for x86-64.
* Both 32- and 64-bit applications, if not linked with "large address aware", are limited to 2&nbsp;GiB of virtual address space.
* Ability to use up to 128&nbsp;GiB (Windows XP/Vista), 192&nbsp;GiB (Windows&nbsp;7), 512&nbsp;GiB (Windows&nbsp;8), 1&nbsp;TiB (Windows Server 2003), 2&nbsp;TiB (Windows Server 2008/Windows 10), 4&nbsp;TiB (Windows Server 2012), or 24&nbsp;TiB (Windows Server 2016/2019) of physical random access memory (RAM).<ref>{{cite web
 |url        = https://learn.microsoft.com/en-us/windows/win32/memory/memory-limits-for-windows-releases
 |title        = Memory Limits for Windows and Windows Server Releases
 |publisher        = Microsoft
 |access-date        = April 18, 2023
 }}</ref>
* [[LLP64]] data model: in C/C++, "int" and "long" types are 32&nbsp;bits wide, "long long" is 64&nbsp;bits, while pointers and types derived from pointers are 64&nbsp;bits wide.
* Kernel mode device drivers must be 64-bit versions; there is no way to run 32-bit kernel mode executables within the 64-bit operating system. User mode device drivers can be either 32-bit or 64-bit.
* 16-bit Windows (Win16) and DOS applications will not run on x86-64 versions of Windows due to the removal of the [[virtual DOS machine]] subsystem (NTVDM) which relied upon the ability to use virtual 8086 mode. Virtual 8086 mode cannot be entered while running in long mode.
* Full implementation of the [[NX bit|NX]] (No Execute) page protection feature. This is also implemented on recent 32-bit versions of Windows when they are started in PAE mode.
* Instead of FS segment descriptor on x86 versions of the [[Windows NT]] family, GS segment descriptor is used to point to two operating system defined structures: Thread Information Block (NT_TIB) in user mode and Processor Control Region (KPCR) in kernel mode. Thus, for example, in user mode <code>GS:0</code> is the address of the first member of the Thread Information Block. Maintaining this convention made the x86-64 port easier, but required AMD to retain the function of the FS and GS segments in long mode – even though segmented addressing ''per se'' is not really used by any modern operating system.<ref name="Pietrek64BitWindowsProgramming"/>
* Early reports claimed that the operating system scheduler would not save and restore the [[x87]] FPU machine state across thread context switches. Observed behavior shows that this is not the case: the x87 state is saved and restored, except for kernel mode-only threads (a limitation that exists in the 32-bit version as well). The most recent documentation available from Microsoft states that the x87/[[MMX (instruction set)|MMX]]/[[3DNow!]] instructions may be used in long mode, but that they are deprecated and may cause compatibility problems in the future.<ref name="64-bitProgrammingGameDevelopers"/><!--- is there a way to use quotes with named refs?
 |quote=The x87, MMX, and 3DNow! instruction sets are deprecated in 64-bit modes.---> (3DNow! is no longer available on AMD processors, with the exception of the <code>PREFETCH</code> and <code>PREFETCHW</code> instructions,<ref>{{cite web |url=https://www.zdnet.com/article/amd-says-goodbye-to-3dnow-instruction-set/ |work=ZDNet |title=AMD says goodbye to 3DNow! instruction set |first=Adrian |last=Kingsley-Hughes |date=August 23, 2010 |access-date=January 8, 2023 |archive-date=January 8, 2023 |archive-url=https://web.archive.org/web/20230108040037/https://www.zdnet.com/article/amd-says-goodbye-to-3dnow-instruction-set/ |url-status=live }}</ref> which are also supported on Intel processors as of [[Broadwell (microarchitecture)|Broadwell]].<!-- citations at that article-->)
* Some components like [[Jet Database Engine]] and [[Data Access Objects]] will not be ported to 64-bit architectures such as x86-64 and IA-64.<ref>{{cite web |url=https://learn.microsoft.com/en-us/windows/win32/winprog64/general-porting-guidelines |title=General Porting Guidelines |department=Programming Guide for 64-bit Windows |website=[[Microsoft Docs]] |access-date=2023-04-18}}</ref><ref>{{cite web |url=https://learn.microsoft.com/en-us/sql/connect/connect-history?view=sql-server-ver16 |title=Driver history for Microsoft SQL Server |website=[[Microsoft Docs]] |access-date=2023-04-18}}</ref><ref>{{cite web |url=https://learn.microsoft.com/en-US/office/troubleshoot/access/jet-odbc-driver-available-32-bit-version |title=Microsoft OLE DB Provider for Jet and Jet ODBC driver are available in 32-bit versions only |department=Office Access |website=[[Microsoft Docs]] |id=KB957570 |access-date=2023-04-18}}</ref>
* [[Microsoft Visual Studio]] can compile [[native code|native applications]] to target either the x86-64 architecture, which can run only on 64-bit Microsoft Windows, or the [[IA-32]] architecture, which can run as a 32-bit application on 32-bit Microsoft Windows or 64-bit Microsoft Windows in [[WoW64]] emulation mode. [[Managed code|Managed applications]] can be compiled either in IA-32, x86-64 or AnyCPU modes. Software created in the first two modes behave like their IA-32 or x86-64 native code counterparts respectively; When using the AnyCPU mode, however, applications in 32-bit versions of Microsoft Windows run as 32-bit applications, while they run as a 64-bit application in 64-bit editions of Microsoft Windows.

== Video game consoles ==
The [[PlayStation 4]] and [[Xbox One]] use AMD x86-64 processors based on the [[Jaguar (microarchitecture)|Jaguar]] [[microarchitecture]].<ref name=XboxOneMay2013Anandtechcomparison>{{cite news |title= The Xbox&nbsp;One: Hardware Analysis & Comparison to PlayStation&nbsp;4 |author= Anand Lal Shimpi |publisher= Anandtech |url= http://www.anandtech.com/show/6972/xbox-one-hardware-compared-to-playstation-4/2 |date= May 21, 2013 |access-date= May 22, 2013 |archive-date= June 7, 2013 |archive-url= https://web.archive.org/web/20130607031844/http://www.anandtech.com/show/6972/xbox-one-hardware-compared-to-playstation-4/2 |url-status= dead }}</ref><ref name=XboxOneMay2013SpecGameinformer>{{cite web |url= https://www.gameinformer.com/b/news/archive/2013/05/21/the-tech-spec-test-xbox-one-vs-playstation-4.aspx |title= The Tech Spec Test: Xbox&nbsp;One Vs. PlayStation&nbsp;4 |publisher= Game Informer |date= May 21, 2013 |access-date= May 22, 2013 |archive-date= June 7, 2013 |archive-url= https://web.archive.org/web/20130607180640/https://www.gameinformer.com/b/news/archive/2013/05/21/the-tech-spec-test-xbox-one-vs-playstation-4.aspx |url-status= live }}</ref> Firmware and games are written in x86-64 code; no legacy x86 code is involved. The [[PlayStation 5]] and [[Xbox Series X/S]] use AMD x86-64 processors based on the [[Zen 2]] microarchitecture.<ref>{{Cite web|date=2020-08-31|title=What to expect from Sony 'PlayStation 5' launch in November|url=https://indianexpress.com/article/technology/gaming/sony-playstation-5-might-launch-on-november-13-6577207/|access-date=2020-09-14|website=The Indian Express|language=en|archive-date=September 19, 2020|archive-url=https://web.archive.org/web/20200919053244/https://indianexpress.com/article/technology/gaming/sony-playstation-5-might-launch-on-november-13-6577207/|url-status=live}}</ref><ref>{{Cite web|last=Cutress|first=Dr Ian|title=Hot Chips 2020 Live Blog: Microsoft Xbox Series X System Architecture (6:00pm PT)|url=https://www.anandtech.com/show/15994/hot-chips-2020-live-blog-microsoft-xbox-series-x-system-architecture-600pm-pt|access-date=2020-09-14|website=www.anandtech.com|archive-date=September 17, 2020|archive-url=https://web.archive.org/web/20200917190502/https://www.anandtech.com/show/15994/hot-chips-2020-live-blog-microsoft-xbox-series-x-system-architecture-600pm-pt|url-status=dead}}</ref> The [[Steam Deck]] uses a custom AMD x86-64 [[AMD Accelerated Processing Unit|accelerated processing unit]] (APU) based on the Zen 2 microarchitecture.<ref name="verge tech pres details">{{cite web |last=Hollister |first=Sean |date=November 12, 2021 |title=Steam Deck: Five big things we learned from Valve's developer summit |url=https://www.theverge.com/22779252/steam-deck-things-we-learned-from-valve-developer-summit |accessdate=November 12, 2021 |work=[[The Verge]] |archive-date=February 7, 2022 |archive-url=https://web.archive.org/web/20220207230831/https://www.theverge.com/22779252/steam-deck-things-we-learned-from-valve-developer-summit |url-status=live }}</ref>

== Industry naming conventions ==
Since AMD64 and Intel 64 are substantially similar, many software and hardware products use one vendor-neutral term to indicate their compatibility with both implementations. AMD's original designation for this processor architecture, "x86-64", is still used for this purpose,<ref name="apple-x86-64"/> as is the variant "x86_64".<ref name="apple-x86_64-arch-manpage"/><ref name="apple-x86_64-email"/> Other companies, such as [[Microsoft]]<ref name="ms-x64"/> and [[Sun Microsystems]]/[[Oracle Corporation]],<ref name="solaris-x64"/> use the contraction "x64" in marketing material.

The term [[IA-64]] refers to the [[Itanium]] processor, and should not be confused with x86-64, as it is a completely different instruction set.

Many operating systems and products, especially those that introduced x86-64 support prior to Intel's entry into the market, use the term "AMD64" or "amd64" to refer to both AMD64 and Intel 64.
* '''amd64'''
** Most [[BSD]] systems such as [[FreeBSD]], [[MidnightBSD]], [[NetBSD]] and [[OpenBSD]] refer to both AMD64 and Intel 64 under the architecture name "amd64".
** Some [[Linux distribution]]s such as [[Debian]], [[Ubuntu (operating system)|Ubuntu]], [[Gentoo Linux]] refer to both AMD64 and Intel 64 under the architecture name "amd64".
** [[Microsoft Windows]]'s x64 versions use the AMD64 moniker internally to designate various components which use or are compatible with this architecture. For example, the [[environment variable]] PROCESSOR_ARCHITECTURE is assigned the value "AMD64" as opposed to "x86" in 32-bit versions, and the system directory on a Windows x64 Edition installation CD-ROM is named "AMD64", in contrast to "i386" in 32-bit versions.<ref>{{Cite web |url=http://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture_fields.aspx |title=ProcessorArchitecture Fields |access-date=September 4, 2013 |archive-date=April 28, 2015 |archive-url=https://web.archive.org/web/20150428190214/https://msdn.microsoft.com/en-us/library/microsoft.build.utilities.processorarchitecture_fields.aspx |url-status=live }}</ref>
** Sun's [[Solaris (operating system)|Solaris]]'s ''isalist'' command identifies both AMD64- and Intel 64-based systems as "amd64".
** [[Java Development Kit]] (JDK): the name "amd64" is used in directory names containing x86-64 files.
* '''x86_64'''
** The [[Linux kernel]]<ref>{{cite web | url = http://lxr.linux.no/#linux+v3.7.8/arch/x86/configs/x86_64_defconfig | title = An example file from Linux 3.7.8 kernel source tree displaying the usage of the term x86_64 | access-date = February 17, 2013 | url-status = dead | archive-url = https://web.archive.org/web/20050923210216/http://lxr.linux.no/#linux+v3.7.8/arch/x86/configs/x86_64_defconfig | archive-date = September 23, 2005 | df = mdy-all }}</ref> and the [[GNU Compiler Collection]] refers to 64-bit architecture as "x86_64".
** Some Linux distributions, such as [[Fedora (operating system)|Fedora]], [[openSUSE]], [[Arch Linux]], [[Gentoo Linux]] refer to this 64-bit architecture as "x86_64".
** Apple [[macOS]] refers to 64-bit architecture as "x86-64" or "x86_64", as seen in the Terminal command <code>arch</code><ref name="apple-x86_64-arch-manpage"/> and in their developer documentation.<ref name="apple-x86-64"/><ref name="apple-x86_64-email"/>
** Breaking with most other BSD systems, [[DragonFly BSD]] refers to 64-bit architecture as "x86_64".
** [[Haiku (operating system)|Haiku]] refers to 64-bit architecture as "x86_64".

== Licensing ==
x86-64/AMD64 was solely developed by AMD. Until April 2021 when the relevant patents expired, AMD held patents on techniques used in AMD64;<ref>{{patent|US|6877084}}</ref><ref>{{patent|US|6889312}}</ref><ref>{{patent|US|6732258}}</ref> those patents had to be licensed from AMD in order to implement AMD64. Intel entered into a cross-licensing agreement with AMD, licensing to AMD their patents on existing x86 techniques, and licensing from AMD their patents on techniques used in x86-64.<ref>{{cite web
 |url=http://contracts.corporate.findlaw.com/agreements/amd/intel.license.2001.01.01.html
 |title=Patent Cross License Agreement Between AMD and Intel
 |access-date=August 23, 2009
 |date=January 1, 2001
 |url-status=dead
 |archive-url=https://web.archive.org/web/20070621084244/http://contracts.corporate.findlaw.com/agreements/amd/intel.license.2001.01.01.html
 |archive-date=June 21, 2007
}}</ref> In 2009, AMD and Intel settled several lawsuits and cross-licensing disagreements, extending their cross-licensing agreements.<ref>{{cite web |url = https://www.sec.gov/Archives/edgar/data/2488/000119312509236705/dex101.htm |title = AMD Intel Settlement Agreement |access-date = September 18, 2017 |archive-date = July 7, 2017 |archive-url = https://web.archive.org/web/20170707043343/https://www.sec.gov/Archives/edgar/data/2488/000119312509236705/dex101.htm |url-status = live }}</ref><ref>{{cite web |url= http://news.cnet.com/8301-1001_3-10396188-92.html |publisher= CNET |author= Stephen Shankland and Jonathan E. Skillings |title= Intel to pay AMD $1.25 billion in antitrust settlement |date= November 12, 2009 |access-date= April 24, 2012 |archive-date= November 8, 2012 |archive-url= https://web.archive.org/web/20121108032512/http://news.cnet.com/8301-1001_3-10396188-92.html |url-status= dead }}</ref><ref>{{cite web|last1=Smith|first1=Ryan|title=AMD and Intel Settle Their Differences: AMD Gets To Go Fabless|url=http://www.anandtech.com/show/2873|website=AnandTech|archive-url=https://web.archive.org/web/20100513042947/http://www.anandtech.com/show/2873|archive-date=May 13, 2010|date=November 12, 2009}}</ref>

== See also ==
* [[AGESA]] (AMD Generic Encapsulated Software Architecture)
* [[Transient execution CPU vulnerability]]

== Notes ==
{{reflist|group=note}}
{{reflist|group=lower-alpha}}

== References ==
{{reflist|30em}}

== External links ==
* [https://developer.amd.com/resources/developer-guides-manuals/ AMD Developer Guides, Manuals & ISA Documents]
* [http://www.stanford.edu/class/ee380/Abstracts/O00927.html x86-64: Extending the x86 architecture to 64-bits] – technical talk by the architect of AMD64 ([https://web.archive.org/web/20100813052749/http://stanford-online.stanford.edu/courses/ee380/000927-ee380-100.asx video archive]), and [http://www.stanford.edu/class/ee380/Abstracts/040107.html second talk by the same speaker] ([https://web.archive.org/web/20100813100133/http://stanford-online.stanford.edu/courses/ee380/040107-ee380-100.asx video archive])
* [https://web.archive.org/web/20060623073619/http://www.xbitlabs.com/news/other/display/20041227094638.html AMD's "Enhanced Virus Protection"]
* [https://www.theregister.co.uk/2005/08/23/intel_fixes_em64t/ Intel tweaks EM64T for full AMD64 compatibility]
* [http://www.extremetech.com/extreme/56018-analyst-intel-reverseengineered-amd64 Analyst: Intel Reverse-Engineered AMD64]
* [http://marc.info/?l=linux-kernel&m=107766481408468&w=2 Early report of differences between Intel IA32e and AMD64]
* [http://gcc.gnu.org/pub/gcc/summit/2003/Porting%20to%2064%20bit.pdf Porting to 64-bit GNU/Linux Systems], by Andreas Jaeger from [[GCC Summit]] 2003. An excellent paper explaining almost all practical aspects for a transition from 32-bit to 64-bit.
* [http://www.intel.com/technology/intel64/index.htm Intel 64 Architecture]
* [https://web.archive.org/web/20110403005033/http://software.intel.com/en-us/articles/all-about-64-bits/ Intel Software Network: "64 bits"]
* [https://web.archive.org/web/20170222181811/http://www.turboirc.com/asm/ TurboIRC.COM tutorials, including examples of how to of enter protected and long mode the raw way from DOS]
* [https://web.archive.org/web/20100123010204/http://software.intel.com/en-us/articles/seven-steps-of-migrating-a-program-to-a-64-bit-system/ Seven Steps of Migrating a Program to a 64-bit System]
* [http://msdn.microsoft.com/en-us/library/aa366778%28VS.85%29.aspx Memory Limits for Windows Releases]

{{AMD technology}}

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