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{{short description|American technology company}}
{{Infobox company
| name = Xilinx, Inc.
| logo = File:Xilinx logo.svg
| image = XilinxInc-lobby.jpg
| image_caption = Headquarters in [[San Jose, California]]
| type = [[Public company|Public]]
| traded_as = {{NASDAQ was|XLNX}}
| fate = Acquired by [[AMD]] in 2022 and Xilinx's generic branding phased out in 2023
| defunct = {{end date and age|2023|06|06}}
| foundation = {{start date and age|1984}}<ref name="Xilinx-Inc-Jun-1996-10-K">{{cite web |url=http://edgar.secdatabase.com/2283/101287096000076/filing-main.htm |title=Xilinx Inc, Form DEF 14A, Filing Date Jun 24, 1996 |publisher=secdatabase.com |access-date=May 6, 2018 |archive-date=May 7, 2018 |archive-url=https://web.archive.org/web/20180507153753/http://edgar.secdatabase.com/2283/101287096000076/filing-main.htm |url-status=live }}</ref>
| location = [[San Jose, California|San Jose]], [[California]], U.S.
| founders = {{ubl|[[James V. Barnett II]]|[[Ross Freeman]]|[[Bernie Vonderschmitt]]}}
| area_served = Worldwide
| key_people = {{ubl|class=nowrap|Dennis Segers ([[chairman]])|[[Victor Peng]] ([[President (corporate title)|president]], [[Chief Executive Officer|CEO]])|Brice Hill ([[Chief Financial Officer|CFO]])<ref>{{cite web |title=CFOs On the Move |date=10 April 2020 |url=https://www.cfo.com/people/2020/04/cfos-on-the-move-week-ending-april-10/ |access-date=16 April 2020 |archive-date=18 April 2020 |archive-url=https://web.archive.org/web/20200418042831/https://www.cfo.com/people/2020/04/cfos-on-the-move-week-ending-april-10/ |url-status=live }}</ref>|Ivo Bolsens ([[Chief Technology Officer|CTO]])}}
| industry = [[Integrated circuit]]s
| products = [[FPGA]]s, [[CPLD]]s
| revenue = {{nowrap|{{decrease}} {{US$|3.15 billion|link=yes}} (2021)}}<ref name="2021 10-K">{{cite web |title=Form 10-K Xilinx, Inc. For the Fiscal Year Ended April 3,2021 |url=https://www.sec.gov/ix?doc=/Archives/edgar/data/743988/000074398821000016/xlnx-20210403.htm |publisher=[[U.S. Securities and Exchange Commission]] |date=14 May 2021 }}</ref>
| operating_income = {{nowrap|{{decrease}} {{US$|753 million}} (2021)}}<ref name="2021 10-K" />
| net_income = {{nowrap|{{decrease}} {{US$|646 million}} (2021)}}<ref name="2021 10-K" />
| assets = {{nowrap|{{increase}} {{US$|5.52 billion}} (2021)}}<ref name="2021 10-K" />
| equity = {{nowrap|{{increase}} {{US$|2.89 billion}} (2021)}}<ref name="2021 10-K" />
| parent = [[AMD]] (2022–2023)
| num_employees = 4,890 (April 2021)<ref name="2021 10-K" />
| website = {{official URL}}
}}

'''Xilinx, Inc.''' ({{IPAc-en|ˈ|z|aɪ|l|ɪ|ŋ|k|s}} {{Respell|ZY|links}}) was an American technology and [[semiconductor]] company that primarily supplied [[programmable logic device]]s. The company is renowned for inventing the first commercially viable [[field-programmable gate array]] (FPGA). It also pioneered the first [[fabless manufacturing]] model.<ref name=":0b">{{Cite web|title=XCELL issue 32|url=http://www.xilinx.com/publications/archives/xcell/Xcell32.pdf|publisher=Xilinx}}</ref><ref name="six">Jonathan Cassell, iSuppli. "[http://www.isuppli.com/MarketWatchDetail.aspx?ID=314 A Forgettable Year for Memory Chip Makers: iSuppli releases preliminary 2008 semiconductor rankings] {{Webarchive|url=https://web.archive.org/web/20081217125827/http://www.isuppli.com/MarketWatchDetail.aspx?ID=314 |date=2008-12-17 }}." December 1, 2008. Retrieved January 15, 2009.</ref><ref name="eleven">John Edwards, EDN. "[https://archive.today/20120728124831/http://www.edn.com/article/CA6339519.html No room for Second Place]." June 1, 2006. Retrieved January 15, 2009.</ref>

Xilinx was co-founded by [[Ross Freeman]], [[Bernard Vonderschmitt]], and [[James V. Barnett II|James V Barnett II]] in 1984. The company went public on the [[Nasdaq]] in 1990.<ref>{{cite web |url=https://www.forbes.com/companies/xilinx |title=Forbes Profile: Xilinx |access-date=30 June 2022 |website=[[Forbes]]}}</ref><ref>{{cite web |url=https://www.latimes.com/archives/la-xpm-1991-04-30-fi-1269-story.html |title=THE TIMES 100 : The Best Performing Companies in California : View From the Street : Initial Stock Offerings Proved a Real Gamble |date=30 April 1991 |work=[[Los Angeles Times]] |first=Tom |last=Petruno}}</ref> In October 2020, [[AMD]] announced its acquisition of Xilinx, which was completed on February 14, 2022, through an all-stock transaction valued at approximately $60 billion.<ref>{{Cite web|title=AMD to Acquire Xilinx, Creating the Industry's High Performance Computing Leader|url=https://ir.amd.com/news-events/press-releases/detail/977/amd-to-acquire-xilinx-creating-the-industrys-high?sf239269550=1|access-date=2020-10-27|website=Advanced Micro Devices, Inc.| date=27 October 2020 |language=en}}</ref><ref>{{Cite news|last=Lee|first=Jane Lanhee|date=2022-02-14|title=AMD closes record chip industry deal with estimated $50 billion purchase of Xilinx|language=en|work=Reuters|url=https://www.reuters.com/technology/amd-closes-biggest-chip-acquisition-with-498-bln-purchase-xilinx-2022-02-14/|access-date=2022-02-14}}</ref> Xilinx remained a wholly owned [[subsidiary]] of AMD until the [[brand]] was phased out in June 2023, with Xilinx's product lines now branded under AMD.<ref>{{Cite web |title=424B3 |url=https://www.sec.gov/Archives/edgar/data/2488/000119312521071625/d83168d424b3.htm |access-date=2023-05-18 |website=www.sec.gov}}</ref>

==Company overview==

Xilinx was founded in [[Silicon Valley]] in 1984 and was headquartered in [[San Jose, California|San Jose]], United States. The company also had offices in [[Longmont]] (United States), [[Dublin]], [[Singapore]], [[Hyderabad]] (India), [[Beijing]], [[Shanghai]]; [[Brisbane]], [[Tokyo]] and [[Yerevan]].<ref name="four">Funding Universe. "[http://www.fundinguniverse.com/company-histories/Xilinx-Inc-Company-History.html Xilinx, Inc.] {{Webarchive|url=https://web.archive.org/web/20131104072422/http://www.fundinguniverse.com/company-histories/xilinx-inc-history/ |date=2013-11-04 }}" Retrieved January 15, 2009.</ref><ref>Cai Yan, [[EE Times]]. "[http://www.eetimes.com/electronics-news/4070772/Xilinx-testing-out-China-training-program Xilinx testing out China training program] {{Webarchive|url=https://web.archive.org/web/20130523202247/http://www.eetimes.com/electronics-news/4070772/Xilinx-testing-out-China-training-program |date=2013-05-23 }}." Mar 27, 2007. Retrieved Dec 19, 2012.</ref>

According to Bill Carter, former [[Chief technology officer|CTO]] and current{{when|date=February 2023}} fellow at Xilinx, the choice of the name Xilinx refers to the [[chemical symbol]] for [[silicon]] Si.<ref name=":6" />{{how|date=December 2021}}{{failed verification|date=February 2023}} The "linx" represents programmable links that connect programmable logic blocks together. The 'X's at each end represent the programmable logic blocks.<ref name="three"/>{{citation needed|date=February 2023|reason=the only citation here is a permanent dead link}}

Xilinx sold a broad range of [[field programmable gate array]]s (FPGAs), and [[complex programmable logic device]]s (CPLDs), design tools, [[intellectual property]], and reference designs.<ref name="two">{{cite web|title=Xilinx|url=http://www.xilinx.com/|access-date=August 16, 2015|archive-date=February 5, 2009|archive-url=https://web.archive.org/web/20090205124515/http://www.xilinx.com/company/history.htm|url-status=live}}</ref> Xilinx customers represent just over half of the entire programmable logic market, at 51%.<ref name="two"/><ref name="six"/><ref name="twentythree">{{Cite web |url=http://media.corporate-ir.net/media_files/irol/21/212763/Q309/xlnxfactsheetQ3FY09.pdf |title=Xilinx Fact Sheet |access-date=2009-01-29 |archive-date=2012-01-05 |archive-url=https://web.archive.org/web/20120105174526/http://media.corporate-ir.net/media_files/irol/21/212763/Q309/xlnxfactsheetQ3FY09.pdf |url-status=live }}</ref> [[Altera]] is Xilinx's strongest competitor with 34% of the market. Other key players in this market are [[Actel]] (now subsidiary of [[Microchip Technology|Microsemi]]) and [[Lattice Semiconductor]].<ref name="eleven"/>

==History==

===Early history===
[[Ross Freeman]], [[Bernard Vonderschmitt]], and [[James V Barnett II]]—all former employees of [[Zilog]], an [[integrated circuit]] and solid-state device manufacturer—co-founded Xilinx in 1984 with headquarters in [[San Jose, California|San Jose]], USA.<ref name="four" /><ref name="three">[http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle_print&ID=1255523 Xilinx MediaRoom - Press Releases]{{Dead link|date=August 2018|bot=InternetArchiveBot|fix-attempted=yes}}. Press.xilinx.com. Retrieved on 2013-11-20.</ref>

While working for Zilog, Freeman wanted to create chips that acted like a blank tape, allowing users to program the technology themselves.<ref name="three" /> "The concept required lots of [[transistors]] and, at that time, transistors were considered extremely precious—people thought that Ross's idea was pretty far out", said Xilinx Fellow Bill Carter, hired in 1984 to design ICs as Xilinx's eighth employee.<ref name="three" />

It was at the time more profitable to manufacture generic circuits in massive volumes<ref name="four"/> than specialized circuits for specific markets.<ref name="four"/> FPGAs promised to make specialized circuits profitable.

Freeman could not convince Zilog to invest in FPGAs to chase a market then estimated at $100 million,<ref name="four"/> so he and Barnett left to team up with Vonderschmitt, a former colleague. Together, they raised $4.5 million in [[Venture capital|venture]] [[funding]] to design the first commercially viable FPGA.<ref name="four"/> They incorporated the company in 1984 and began selling its first product by 1985.<ref name="four"/>

By late 1987, the company had raised more than $18 million in venture capital (equivalent to ${{Inflation|US|18|1987|r=2}} million in {{Inflation-year|US}}) and was making nearly $14 million a year.<ref name="four"/><ref name="twelve">[http://www.westegg.com/inflation/infl.cgi The Inflation Calculator] {{Webarchive|url=https://web.archive.org/web/20180326173743/https://westegg.com/inflation/infl.cgi |date=2018-03-26 }}. Retrieved January 15, 2009.</ref>

===Expansion===
From 1988 to 1990, the company's [[revenue]] grew each year, from $30 million to $100 million.<ref name="four" /> During this time, Monolithic Memories Inc. (MMI), the company which had been providing funding to Xilinx, was purchased by [[AMD]].<ref name="four" /> As a result, Xilinx dissolved the deal with MMI and went public on the Nasdaq in 1989.<ref name="four" /> The company also moved to a {{convert|144000|sqft|m2|adj=on}} plant in San Jose, California, to handle increasingly large orders from [[Hewlett-Packard|HP]], [[Apple Inc.]], [[IBM]] and [[Sun Microsystems]].<ref name="four" />

Other FPGA makers emerged in the mid-1990s.<ref name="four" /> By 1995, the company reached $550 million in revenue.<ref name="four" /> Over the years, Xilinx expanded operations to [[India]], [[Asia]] and [[Europe]].<ref name="five">Company Release. "[http://www.xilinx.com/prs_rls/2006/xil_corp/06116_china.htm Xilinx Underscores Commitment to China] {{webarchive|url=https://archive.today/20130209195736/http://www.xilinx.com/prs_rls/2006/xil_corp/06116_china.htm |date=2013-02-09 }}." November 1, 2006. Retrieved January 15, 2009.</ref><ref name="eight">[[EE Times]] Asia. "[http://www.eetasia.com/ART_8800381997_499485_NT_efffb30f.HTM Xilinx investing $40 million in Singapore operations] {{Webarchive|url=https://web.archive.org/web/20150610213035/http://www.eetasia.com/ART_8800381997_499485_NT_efffb30f.HTM |date=2015-06-10 }}." November 16, 2005. Retrieved January 15, 2009.</ref><ref name="nine">Pradeep Chakraborty. "[http://www.ciol.com/Semicon/SemiSpeak/Interviews/India-a-high-growth-area-for-Xilinx/8808108812/0/ India a high growth area for Xilinx] {{Webarchive|url=https://web.archive.org/web/20090303091216/http://www.ciol.com/Semicon/SemiSpeak/Interviews/India-a-high-growth-area-for-Xilinx/8808108812/0/ |date=2009-03-03 }}." August 8, 2008. Retrieved January 15, 2009.</ref><ref name="ten">EDB Singapore. "[http://www.edb.gov.sg/edb/sg/en_uk/index/news/articles/xilinx__inc__strengthens.html Xilinx, Inc. strengthens presence in Singapore to stay ahead of competition] {{Webarchive|url=https://web.archive.org/web/20090302014716/http://www.edb.gov.sg/edb/sg/en_uk/index/news/articles/xilinx__inc__strengthens.html |date=2009-03-02 }}." December 1, 2007. Retrieved January 15, 2009.</ref>

Xilinx's sales rose to $2.53 billion by the end of its fiscal year 2018.<ref>Xilinx Earnings Report. "[http://investor.xilinx.com/releasedetail.cfm?ReleaseID=1065046] {{Webarchive|url=https://web.archive.org/web/20180426195608/http://investor.xilinx.com/releasedetail.cfm?ReleaseID=1065046|date=2018-04-26}}." April 25, 2018. Retrieved April 25, 2018.</ref> Moshe Gavrielov – an [[Electronic design automation|EDA]] and [[Application-specific integrated circuit|ASIC]] industry veteran who was appointed president and CEO in early 2008 – introduced targeted design platforms that combine FPGAs with [[software]], IP cores, boards and kits to address focused target applications.<ref name="embedded">Embedded Technology Journal, “[http://www.techfocusmedia.net/embeddedtechnologyjournal/ondemand/20091015_01_xilinx/ Introducing the Xilinx Targeted Design Platform: Fulfilling the Programmable Imperative] {{Webarchive|url=https://web.archive.org/web/20110724092503/http://www.techfocusmedia.net/embeddedtechnologyjournal/ondemand/20091015_01_xilinx/ |date=2011-07-24 }}.” Retrieved June 10, 2010.</ref> These platforms provide an alternative to costly application-specific integrated circuits (ASICs) and application-specific standard products (ASSPs).<ref name="twentyeight">Lou Sosa, Electronic Design. "[http://electronicdesign.com/Articles/ArticleID/19017/19017.html PLDs Present The Key To Xilinx's Success] {{Webarchive|url=https://web.archive.org/web/20090302010121/http://electronicdesign.com/Articles/ArticleID/19017/19017.html |date=2009-03-02 }}." June 12, 2008. Retrieved January 20, 2008.</ref><ref name="twentynine">Mike Santarini, EDN. "[http://www.edn.com/blog/1480000148/post/60019806.html Congratulations on the Xilinx CEO gig, Moshe!] {{webarchive|url=https://web.archive.org/web/20080516040230/http://www.edn.com/blog/1480000148/post/60019806.html |date=2008-05-16 }}." January 8, 2008. Retrieved January 20, 2008.</ref><ref name=":0">Ron Wilson, EDN. "[http://www.edn.com/blog/1690000169/post/1320019732.html Moshe Gavrielov Looks into the Future of Xilinx and the FPGA Industry] {{webarchive|url=https://archive.today/20120728230208/http://www.edn.com/blog/1690000169/post/1320019732.html |date=2012-07-28 }}." January 7, 2008. Retrieved January 20, 2008.</ref>

On January 4, 2018, Victor Peng, the company's COO, replaced Gavrielov as CEO.<ref name=XilinxPressRelease08Jan2018>Company Release. "[https://www.xilinx.com/news/press/2018/xilinx-appoints-victor-peng-as-president-and-chief-executive-officer.html Xilinx Appoints Victor Peng as President and Chief Executive Officer] {{Webarchive|url=https://web.archive.org/web/20180124070908/https://www.xilinx.com/news/press/2018/xilinx-appoints-victor-peng-as-president-and-chief-executive-officer.html |date=2018-01-24 }}." Jan 8, 2018</ref>

===Recent history===
In 2011, the company introduced the [[Virtex (FPGA)|Virtex-7]] 2000T, the first product based on 2.5D stacked silicon (based on [[Interposer|silicon interposer]] technology) to deliver larger FPGAs than could be built using standard monolithic silicon.<ref name=":6">PR Newswire "[https://www.prnewswire.com/news-releases/xilinx-ships-worlds-highest-capacity-fpga-and-shatters-industry-record-for-number-of-transistors-by-2x-132515558.html Xilinx ships world's highest capacity FPGA and shatters industry record for number of transistors by 2x] {{Webarchive|url=https://web.archive.org/web/20180612163845/https://www.prnewswire.com/news-releases/xilinx-ships-worlds-highest-capacity-fpga-and-shatters-industry-record-for-number-of-transistors-by-2x-132515558.html |date=2018-06-12 }}" October 2011. Retrieved May 1st, 2018</ref> Xilinx then adapted the technology to combine formerly separate components in a single chip, first combining an FPGA with [[transceiver]]s based on heterogeneous process technology to boost bandwidth capacity while using less power.<ref>Clive Maxfield, [[EETimes]]. "[http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4374071/Xilinx-ships-the-world-s-first-heterogeneous-3D-FPGA Xilinx ships the world’s first heterogeneous 3D FPGA] {{Webarchive|url=https://web.archive.org/web/20120604063253/http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4374071/Xilinx-ships-the-world-s-first-heterogeneous-3D-FPGA |date=2012-06-04 }}." May 30, 2012. Retrieved June 12, 2012.</ref>

According to former Xilinx [[Chief executive officer|CEO]] Moshe Gavrielov, the addition of a heterogeneous communications device, combined with the introduction of new software tools and the Zynq-7000 line of 28&nbsp;nm [[System on a chip|SoC]] devices that combine an [[ARM core]] with an FPGA, are part of shifting its position from a programmable logic device supplier to one delivering “all things programmable”.<ref name=ElectronicProductNews15May2012>Electronic Product News. "[http://www.epn-online.com/page/new188150/with-moshe-gavrielov-president-ceo-xilinx.html Interview with Moshe Gavrielov, president, CEO, Xilinx] {{Webarchive|url=https://web.archive.org/web/20180612141756/http://www.epn-online.com/page/new188150/with-moshe-gavrielov-president-ceo-xilinx.html |date=2018-06-12 }}." May 15, 2012. Retrieved June 12, 2012.</ref>

In addition to Zynq-7000, Xilinx product lines include the [[Virtex (FPGA)|Virtex]], Kintex and Artix series, each including configurations and models optimized for different applications.<ref name="thirtythree">DSP-FPGA.com. [http://www.dsp-fpga.com/products/search/index.php?q=xilinx+fpga&op=cn&max=40 Xilinx FPGA Products] {{Webarchive|url=https://web.archive.org/web/20201011022312/https://militaryembedded.com/ |date=2020-10-11 }}.” April 2010. Retrieved June 10, 2010.</ref> In April 2012, the company introduced the [[Xilinx Vivado|Vivado Design Suite]] - a next-generation [[System on a chip|SoC]]-strength design environment for advanced electronic system designs.<ref name="EETimes25Apr2012">Brian Bailey, EE Times. "[http://www.eetimes.com/electronics-products/ip-eda-products/4371701/Second-generation-for-FPGA-software Second generation for FPGA software] {{Webarchive|url=https://web.archive.org/web/20130116073612/http://www.eetimes.com/electronics-products/ip-eda-products/4371701/Second-generation-for-FPGA-software |date=2013-01-16 }}." Apr 25, 2012. Retrieved Dec 21, 2012.</ref> In May, 2014, the company shipped the first of the next generation FPGAs: the 20[[Nanometre|nm]] UltraScale.<ref name=XCellDaily>{{cite web|url=http://forums.xilinx.com/t5/Xcell-Daily-Blog/Xilinx-ships-first-20nm-Virtex-UltraScale-FPGA-Why-this-matters/ba-p/458488|title=Xilinx ships first 20nm Virtex UltraScale FPGA – W... - Xilinx User Community Forums|date=13 May 2014 |access-date=August 16, 2015|archive-date=July 21, 2015|archive-url=https://web.archive.org/web/20150721065628/http://forums.xilinx.com/t5/Xcell-Daily-Blog/Xilinx-ships-first-20nm-Virtex-UltraScale-FPGA-Why-this-matters/ba-p/458488|url-status=live}}</ref>

In September 2017, [[Amazon (company)|Amazon]] and Xilinx started a campaign for FPGA adoption. This campaign enables [[Amazon Web Services|AWS]] Marketplace's [[Amazon Machine Image]]s (AMIs) with associated Amazon FPGA Instances created by partners. The two companies released software development tools to simplify the creation of FPGA technology. The tools create and manage the machine images created and sold by partners.<ref name="FBS13Dec2016">Karl Freund, [[Forbes (magazine)]]. "[https://www.forbes.com/sites/moorinsights/2016/12/13/amazons-xilinx-fpga-cloud-why-this-may-be-a-significant-milestone/#39772bfe370d  Amazon's Xilinx FPGA Cloud: Why This May Be A Significant Milestone] {{Webarchive|url=https://web.archive.org/web/20180612144551/https://www.forbes.com/sites/moorinsights/2016/12/13/amazons-xilinx-fpga-cloud-why-this-may-be-a-significant-milestone/#39772bfe370d |date=2018-06-12 }}." December 13, 2016. Retrieved April 26, 2018.</ref><ref name="FBS27Sep2017">Karl Freund, [[Forbes (magazine)]]. "[https://www.forbes.com/sites/moorinsights/2017/09/27/amazon-and-xilinx-deliver-new-fpga-solutions/#e1f32802370a  Amazon And Xilinx Deliver New FPGA Solutions] {{Webarchive|url=https://web.archive.org/web/20180612144555/https://www.forbes.com/sites/moorinsights/2017/09/27/amazon-and-xilinx-deliver-new-fpga-solutions/#e1f32802370a |date=2018-06-12 }}." September 27, 2017. Retrieved April 26, 2018.</ref>

In July 2018, Xilinx acquired DeepPhi Technology, a [[China|Chinese]] [[machine learning]] [[Startup company|startup]] founded in 2016.<ref name=":4">{{Cite web|url=https://www.anandtech.com/show/13098/xilinx-acquires-deepphi-tech-ml-startup|title=Xilinx Acquires DEEPhi Tech ML Startup|date=19 July 2018|website=AnandTech|url-status=dead|archive-url=https://web.archive.org/web/20200212194101/https://www.anandtech.com/show/13098/xilinx-acquires-deepphi-tech-ml-startup|archive-date=12 February 2020}}</ref><ref>{{Cite news|url=https://www.scientific-computing.com/news/xilinx-acquires-deephi-tech|title=Xilinx acquires DeePhi Tech|date=19 July 2018|work=Scientific Computing World|url-status=live|archive-date=11 October 2020|archive-url=https://web.archive.org/web/20201011022311/https://www.scientific-computing.com/news/xilinx-acquires-deephi-tech}}</ref> In October 2018, the Xilinx Virtex UltraScale+ FPGAs and NGCodec's H.265 video encoder were used in a cloud-based video coding service using the [[High Efficiency Video Coding]] (HEVC).<ref>{{Cite web|url=https://www.design-reuse.com/news/44920/xilinx-huawei-fpga-cloud-based-real-time-video-streaming-china.html|title=Xilinx and Huawei Announce the First FPGA Cloud-based Real-time Video Streaming Solution in China|website=Design And Reuse|language=en|access-date=2019-11-06|archive-date=2019-11-06|archive-url=https://web.archive.org/web/20191106192131/https://www.design-reuse.com/news/44920/xilinx-huawei-fpga-cloud-based-real-time-video-streaming-china.html|url-status=live}}</ref> The combination enables video streaming with the same visual quality as that using GPUs, but at 35%-45% lower bitrate.<ref>{{Cite web|url=https://www.algodone.com/from-ngcodec-to-huawei-salt-is-the-bridge-to-a-new-era-of-hardware-monetization/|title=From NGCodec to Huawei, SALT is the bridge to a new era of hardware monetization|website=Algodone|language=en|access-date=2020-02-20|archive-date=2020-02-20|archive-url=https://web.archive.org/web/20200220195832/https://www.algodone.com/from-ngcodec-to-huawei-salt-is-the-bridge-to-a-new-era-of-hardware-monetization/|url-status=live}}</ref>

In November 2018, the company's Zynq UltraScale+ family of multiprocessor system-on-chips was certified to [[safety integrity level]] (SIL) 3 HFT1 of the [[IEC 61508]] specification.<ref name=":2">{{Cite web|url=https://finance.yahoo.com/news/xilinx-platform-run-ai-driven-123712409.html|title=Xilinx Platform to Run AI Driven ZF Automotive Control Unit|website=finance.yahoo.com|date=7 January 2019 |language=en-US|access-date=2019-08-06|archive-date=2019-08-06|archive-url=https://web.archive.org/web/20190806152014/https://finance.yahoo.com/news/xilinx-platform-run-ai-driven-123712409.html|url-status=live}}</ref><ref>{{Cite web|url=https://www.smart2zero.com/news/zynq-ultrascale-family-now-offers-61508-certified-functional-safety|title=Zynq UltraScale+ family now offers 61508-certified functional safety|date=2018-11-20|website=Smart2.0|language=en|access-date=2019-08-06|archive-date=2019-08-06|archive-url=https://web.archive.org/web/20190806152024/https://www.smart2zero.com/news/zynq-ultrascale-family-now-offers-61508-certified-functional-safety|url-status=live}}</ref> With this certification, developers are able to use the [[Multi-processor system-on-chip|MPSoC]] platform in [[Artificial intelligence|AI]]-based safety applications of up to SIL 3, in industrial 4.0 platforms of automotive, aerospace, and AI systems.<ref>{{Cite web|url=https://finance.yahoo.com/news/xilinxs-zynq-mpsoc-platform-secures-121112160.html|title=Xilinx's Zynq MPSoC Platform Secures Exida Certification|website=finance.yahoo.com|date=21 November 2018 |language=en-US|access-date=2019-08-06|archive-date=2019-08-06|archive-url=https://web.archive.org/web/20190806152013/https://finance.yahoo.com/news/xilinxs-zynq-mpsoc-platform-secures-121112160.html|url-status=live}}</ref><ref>{{Cite web|url=https://www.eenewsembedded.com/news/xilinx-zynq-ultrascale-products-assessed-sil-3|title=Xilinx Zynq Ultrascale+ products assessed to SIL 3|date=2018-11-21|website=eeNews Embedded|language=en|access-date=2019-08-06|archive-date=2019-07-25|archive-url=https://web.archive.org/web/20190725150300/https://www.eenewsembedded.com/news/xilinx-zynq-ultrascale-products-assessed-sil-3|url-status=live}}</ref> In January 2019, ZF Friedrichshafen AG (ZF) worked with Xilinx's Zynq to power its ProAI automotive control unit, which is used to enable automated driving applications.<ref>{{Cite web|url=https://finance.yahoo.com/news/xilinx-platform-run-ai-driven-123712409.html|title=Xilinx Platform to Run AI Driven ZF Automotive Control Unit|website=finance.yahoo.com|date=7 January 2019 |language=en-US|access-date=2019-08-23|archive-date=2019-08-06|archive-url=https://web.archive.org/web/20190806152014/https://finance.yahoo.com/news/xilinx-platform-run-ai-driven-123712409.html|url-status=live}}</ref><ref>{{Cite web|url=https://evertiq.com/design/45374|title=Evertiq - Xilinx partners with ZF on autonomous driving development|website=evertiq.com|date=9 January 2019 |language=en|access-date=2019-08-23|archive-date=2019-08-23|archive-url=https://web.archive.org/web/20190823152626/https://evertiq.com/design/45374|url-status=live}}</ref><ref>{{Cite web|url=https://www.roadtraffic-technology.com/news/xilinx-zf-automated-driving/|title=Xilinx and ZF partner to jointly power automated driving|date=2019-01-08|website=Verdict Traffic|language=en-GB|access-date=2019-08-23|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022312/https://www.roadtraffic-technology.com/news/xilinx-zf-automated-driving/|url-status=live}}</ref> Xilinx's platform overlooks the aggregation, pre-processing, and distribution of real-time data, and accelerates the AI processing of the unit.<ref name=":2" /><ref>{{Cite web|url=https://www.mwee.com/news/xilinx-and-zf-collaborate-automated-driving|title=Xilinx and ZF to collaborate on automated driving|date=2019-01-07|website=www.mwee.com|language=en|access-date=2019-08-23|archive-date=2019-08-23|archive-url=https://web.archive.org/web/20190823152636/https://www.mwee.com/news/xilinx-and-zf-collaborate-automated-driving|url-status=live}}</ref>

In November 2018, Xilinx migrated its defense-grade XQ UltraScale+ products to TSMC's 16&nbsp;nm [[FinFET]] process.<ref>{{Cite web|url=https://www.eenewsanalog.com/news/xilinx-introduces-16nm-defense-grade-ultrascale-portfolio|title=Xilinx introduces 16nm Defense-Grade UltraScale+ Portfolio|date=2018-11-16|website=eeNews Analog|language=en|access-date=2019-08-29|archive-date=2019-08-29|archive-url=https://web.archive.org/web/20190829134910/https://www.eenewsanalog.com/news/xilinx-introduces-16nm-defense-grade-ultrascale-portfolio|url-status=live}}</ref><ref>{{Cite web|url=https://www.chipestimate.com/Xilinx-Advances-State-of-the-Art-in-Integrated-and-Adaptable-1542787200/Xilinx/news/46736|title=Xilinx Advances State-of-the-Art in Integrated and Adaptable Solutions for Aerospace and Defense with Introduction of 16nm Defense-Grade UltraScale+ Portfolio|website=www.chipestimate.com|access-date=2019-08-29|archive-date=2019-08-29|archive-url=https://web.archive.org/web/20190829134902/https://www.chipestimate.com/Xilinx-Advances-State-of-the-Art-in-Integrated-and-Adaptable-1542787200/Xilinx/news/46736|url-status=live}}</ref><ref>{{Cite web|url=https://www.electronicsweekly.com/news/business/542989-2018-11/|title=16nm for def-stan Ultra-Scale SoCs|last=Manners|first=David|date=2018-11-16|website=Electronics Weekly|language=en-GB|access-date=2019-08-29|archive-date=2019-08-29|archive-url=https://web.archive.org/web/20190829134904/https://www.electronicsweekly.com/news/business/542989-2018-11/|url-status=live}}</ref> The products included the industry's first defense-grade heterogeneous [[multi-processor]] SoC devices and encompassed the XQ Zynq UltraScale+ [[MPSoC]]s and RFSoCs as well as XQ UltraScale+ Kintex and Virtex FPGAs.<ref>{{Cite web|url=https://aerospacedefence.electronicspecifier.com/components-1/adaptable-solutions-with-16nm-defence-grade-ultrascale-portfolio|title=Adaptable Solutions with 16nm defence-grade UltraScale+ portfolio|website=aerospacedefence.electronicspecifier.com|access-date=2019-08-29|archive-date=2019-08-29|archive-url=https://web.archive.org/web/20190829134901/https://aerospacedefence.electronicspecifier.com/components-1/adaptable-solutions-with-16nm-defence-grade-ultrascale-portfolio|url-status=live}}</ref><ref>{{Cite web|url=https://chipsnwafers.electronicsforu.com/2018/11/17/highly-integrated-chips-suit-next-gen-aerospace-defense/|title=Highly-integrated Chips Enable Next-Gen Aerospace and Defense Apps|author=<!--Staff writer(s); no by-line.-->|date=2018-11-17|website=ChipsNWafers|language=en-US|access-date=2019-08-29|archive-date=2019-08-29|archive-url=https://web.archive.org/web/20190829134902/https://chipsnwafers.electronicsforu.com/2018/11/17/highly-integrated-chips-suit-next-gen-aerospace-defense/|url-status=live}}</ref> That same month the company expanded its Alveo data center accelerator cards portfolio with the Alveo U280.<ref>{{Cite web|url=https://www.electronicdesign.com/industrial-automation/xilinx-s-compact-fpga-card-heads-edge|title=Xilinx's Compact FPGA Card Heads to the Edge|date=2019-08-07|website=Electronic Design|language=en|access-date=2019-09-05|archive-date=2019-09-05|archive-url=https://web.archive.org/web/20190905131419/https://www.electronicdesign.com/industrial-automation/xilinx-s-compact-fpga-card-heads-edge|url-status=live}}</ref> The initial Alveo line included the U200 and U250, which featured 16&nbsp;nm UltraScale+ Virtex FPGAs and [[DDR4 SDRAM]].<ref>{{Cite web|url=https://www.linleygroup.com/newsletters/newsletter_detail.php?num=5978&year=2019&tag=3|title=Linley Group Newsletter|website=The Linley Group|url-status=live|archive-url=https://web.archive.org/web/20201011022311/https://www.linleygroup.com/newsletters/newsletter_detail.php?num=5978&year=2019&tag=3|archive-date=2020-10-11}}</ref> Those two cards were launched in October 2018 at the Xilinx Developer Forum.<ref name=":3">{{Cite news|url=https://www.datacenterdynamics.com/news/xilinx-unveils-versal-acap-chip-and-alveo-accelerators-data-center/|title=Xilinx unveils Versal ACAP chip and Alveo accelerators for the data center|website=www.datacenterdynamics.com|language=en|access-date=2019-10-03|archive-date=2019-05-13|archive-url=https://web.archive.org/web/20190513083221/https://www.datacenterdynamics.com/news/xilinx-unveils-versal-acap-chip-and-alveo-accelerators-data-center/|url-status=live}}</ref> At the Forum, Victor Peng, CEO of semiconductor design at Xilinx, and AMD CTO [[Mark Papermaster]], used eight Alveo U250 cards and two [[Epyc|AMD Epyc]] 7551 server CPUs to set a new world record for inference throughput at 30,000 images per second.<ref name=":3" />

Also in November 2018, Xilinx announced that [[Dell EMC]] was the first server vendor to qualify its Alveo U200 accelerator card, used to accelerate key HPC and other workloads with select Dell EMC PowerEdge servers.<ref>{{Cite web|url=https://www.hpcwire.com/off-the-wire/xilinx-announces-new-alveo-u280-hbm2-accelerator-card/|title=Xilinx Announces New Alveo U280 HBM2 Accelerator Card|website=HPCwire|language=en-US|access-date=2019-10-10|archive-date=2019-09-05|archive-url=https://web.archive.org/web/20190905131440/https://www.hpcwire.com/off-the-wire/xilinx-announces-new-alveo-u280-hbm2-accelerator-card/|url-status=live}}</ref> The U280 included support for [[High Bandwidth Memory|high-bandwidth memory]] (HBM2) and high-performance server interconnect.<ref>{{Cite web|url=https://mashup.servers-maintenance.com/2018/11/15/xilinx-announces-new-alveo-u280-hbm2-accelerator-card/|title=Xilinx Announces New Alveo U280 HBM2 Accelerator Card|date=2018-11-15|website=Servers Maintenance Mashup|language=en-US|access-date=2019-09-05|archive-date=2019-09-05|archive-url=https://web.archive.org/web/20190905131420/https://mashup.servers-maintenance.com/2018/11/15/xilinx-announces-new-alveo-u280-hbm2-accelerator-card/|url-status=live}}</ref> In August 2019, Xilinx launched the Alveo U50, a low-profile adaptable accelerator with PCIe Gen4 support.<ref>{{Cite web|url=https://www.zdnet.com/article/xilinx-launches-alveo-u50-data-center-accelerator-card/|title=Xilinx launches Alveo U50 data center accelerator card|last=Dignan|first=Larry|website=ZDNet|language=en|access-date=2019-10-23|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022312/https://www.zdnet.com/article/xilinx-launches-alveo-u50-data-center-accelerator-card/|url-status=live}}</ref><ref>{{Cite web|url=https://www.tomshardware.com/news/xilinx-alveo-u50-accelerator-card-pcie-4-hbm,40111.html|title=Xilinx One-Ups Intel With PCIe 4.0 Alveo U50 Data Center Card|last=Components|first=Arne Verheyde 2019-08-07T14:56:02Z|website=Tom's Hardware|date=7 August 2019 |language=en|access-date=2019-10-23}}</ref> The U55C accelerator card was launched in November 2021, designed for [[HPCC]] and big data workloads by incorporating the [[RDMA over Converged Ethernet|RoCE v2]]-based clustering solution, allowing for FPGA-based HPCC clustering to be integrated into existing data center infrastructures.<ref name="U55C">{{cite web |last1=Abazovic |first1=Fuad |title=Xilinx announces Alveo U55C most powerful accelerator card |url=https://www.fudzilla.com/news/ai/53888-xilinx-announces-alveo-u55c-most-powerful-accelerator-card |website=www.fudzilla.com |access-date=21 December 2021 |language=en-gb}}</ref>

In January 2019 [[K&L Gates]], a law firm representing Xilinx sent a [[DMCA]] [[cease and desist]] letter to an [[electrical engineering|EE]] [[YouTube]]r claiming [[trademark infringement]] for featuring the Xilinx logo next to [[Altera]]'s in an educational video.<ref>{{cite web|url=https://www.eevblog.com/forum/chat/xilinx-sends-lawyers-after-online-educators/|title=Xilinx sends lawyers after online educators|date=8 January 2019|publisher=EEVblog Electronics Community Forum|access-date=2019-01-20|archive-date=2019-01-21|archive-url=https://web.archive.org/web/20190121010729/https://www.eevblog.com/forum/chat/xilinx-sends-lawyers-after-online-educators/|url-status=live}}</ref><ref>{{cite web|url=https://news.ycombinator.com/item?id=18937001|title=Xilinx sends lawyers after an engineer teaching FPGA programming|publisher=Hacker News|date=18 January 2019|access-date=2019-01-20|archive-date=2019-01-20|archive-url=https://web.archive.org/web/20190120194604/https://news.ycombinator.com/item?id=18937001|url-status=live}}</ref> Xilinx refused to reply until a video outlining the legal threat was published, after which they sent an apology e-mail.<ref>{{cite web|url=https://www.youtube.com/watch?v=swVuqG9-H0E|title=Xilinx sends lawyers after an engineer teaching FPGA programming|website=[[YouTube]] |date=7 January 2019 |access-date=2019-01-20|archive-date=2019-01-18|archive-url=https://web.archive.org/web/20190118051700/https://www.youtube.com/watch?v=swVuqG9-H0E|url-status=live}}</ref>

In January 2019, [[Baidu]] announced that its new [[Edge computing|edge]] acceleration computing product, EdgeBoard, was powered by Xilinx.<ref>{{Cite web|url=https://www.vision-systems.com/boards-software/article/16748248/edgeboard-artificial-intelligence-device-from-baidu-based-on-xilinx-technology|title=EdgeBoard artificial intelligence device from Baidu based on Xilinx technology|date=2019-01-17|website=Vision Systems Design|language=en|access-date=2019-07-10|archive-date=2019-07-10|archive-url=https://web.archive.org/web/20190710184551/https://www.vision-systems.com/boards-software/article/16748248/edgeboard-artificial-intelligence-device-from-baidu-based-on-xilinx-technology|url-status=live}}</ref><ref>{{Cite web|url=https://www.electronicsweekly.com/news/business/xilinx-power-baidu-brain-2019-01/|title=Xilinx to power Baidu brain|last=Manners|first=David|date=2019-01-17|website=Electronics Weekly|language=en-GB|access-date=2019-07-10|archive-date=2019-07-10|archive-url=https://web.archive.org/web/20190710184557/https://www.electronicsweekly.com/news/business/xilinx-power-baidu-brain-2019-01/|url-status=live}}</ref> Edgeboard is a part of the Baidu Brain AI Hardware Platform Initiative, which encompasses Baidu's open computing services, and hardware and software products for its edge [[Artificial intelligence|AI]] applications.<ref>{{Cite web|url=https://www.eenewspower.com/news/xilinx-enable-baidu-brain-edge-ai-applications|title=Xilinx to enable Baidu Brain edge AI applications|date=2019-01-18|website=eeNews Power|language=en|access-date=2019-07-25|archive-date=2019-07-25|archive-url=https://web.archive.org/web/20190725150239/https://www.eenewspower.com/news/xilinx-enable-baidu-brain-edge-ai-applications|url-status=live}}</ref> Edgeboard is based on the Xilinx Zynq UltraScale+ MPSoC, which uses real-time processors together with programmable logic.<ref>{{Cite web|url=https://www.vision-systems.com/boards-software/article/16748248/edgeboard-artificial-intelligence-device-from-baidu-based-on-xilinx-technology|title=EdgeBoard artificial intelligence device from Baidu based on Xilinx technology|website=Vision Systems Design|date=17 January 2019 |access-date=2019-07-10|archive-date=2019-07-10|archive-url=https://web.archive.org/web/20190710184551/https://www.vision-systems.com/boards-software/article/16748248/edgeboard-artificial-intelligence-device-from-baidu-based-on-xilinx-technology|url-status=live}}</ref><ref>{{Cite web|url=https://techstockobserver.com/xilinx-technology-nasdaqxlnx-announces-that-the-baidu-brain-edge-ai-platform-will-get-powered-by-xilinx/|title=Xilinx Technology (NASDAQ:XLNX) Announces That The Baidu Brain Edge AI Platform Will Get Powered By Xilinx|date=2019-01-23|website=Tech Stock Observer|language=en-US|access-date=2019-08-02|archive-date=2019-08-02|archive-url=https://web.archive.org/web/20190802145957/https://techstockobserver.com/xilinx-technology-nasdaqxlnx-announces-that-the-baidu-brain-edge-ai-platform-will-get-powered-by-xilinx/|url-status=live}}</ref> The Xilinx-based Edgeboard can be used to develop products like smart-video security surveillance solutions, advanced-driver-assistance systems, and next-generation robots.<ref>{{Cite web|url=https://blog.hackster.io/baidu-announces-xilinx-based-edgeboard-for-ai-applications-31f32d4456cb|title=Baidu Announces Xilinx-Based EdgeBoard for AI Applications|last=Atwell|first=Cabe|website=Hackster.io|access-date=2019-08-02|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022351/https://www.hackster.io/news/baidu-announces-xilinx-based-edgeboard-for-ai-applications-31f32d4456cb|url-status=live}}</ref><ref>{{Cite web|url=https://www.4rfv.com/N3R6PHXBVW7J/579/xilinx-technology-to-power-baidu-brain-edge-ai-applications.htm|title=Xilinx Technology to Power Baidu Brain Edge AI Applications : Xilinx : International Broadcast News|website=www.4rfv.com|access-date=2019-08-02|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022342/https://www.4rfv.com/N3R6PHXBVW7J/579/xilinx-technology-to-power-baidu-brain-edge-ai-applications.htm|url-status=live}}</ref>

In February 2019, the company announced two new generations of its Zynq UltraScale+ RF system on chip (RFSoC) portfolio.<ref>{{Cite web|url=https://www.hpcwire.com/off-the-wire/xilinx-reports-record-revenues-exceeding-3-billion-for-fiscal-2019/|title=Xilinx Reports Record Revenues Exceeding $3 Billion For Fiscal 2019|website=HPCwire|language=en-US|access-date=2019-06-05|archive-date=2019-04-25|archive-url=https://web.archive.org/web/20190425183630/https://www.hpcwire.com/off-the-wire/xilinx-reports-record-revenues-exceeding-3-billion-for-fiscal-2019/|url-status=live}}</ref> The device covers the entire sub-6&nbsp;GHz spectrum, which is necessary for [[5G]], and the updates included: an extended millimeter wave interface, up to 20% power reduction in the RF data converter subsystem compared to the base portfolio, and support of [[5G NR|5G New Radio]].<ref>{{Cite web|url=https://www.edacafe.com/nbc/articles/1/1666597/Xilinx-Reports-Record-Revenues-Exceeding-$3-Billion-Fiscal-2019|title=Xilinx Reports Record Revenues Exceeding $3 Billion For Fiscal 2019|website=EDACafe|access-date=2019-06-05|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022340/https://www.edacafe.com/nbc/articles/1/1666597/Xilinx-Reports-Record-Revenues-Exceeding-$3-Billion-Fiscal-2019|url-status=live}}</ref> The second generation release covered up to 5&nbsp;GHz, while the third went up to 6&nbsp;GHz.<ref>{{Cite web|url=https://www.anandtech.com/show/13988/xilinx-announce-new-rfsocs-for-5g-covering-sub6-ghz-and-mmwave|title=Xilinx Announce New RFSoCs for 5G, Covering Sub-6 GHz and mmWave|last=Cutress|first=Ian|website=www.anandtech.com|access-date=2019-06-10|archive-date=2019-08-09|archive-url=https://web.archive.org/web/20190809110224/https://www.anandtech.com/show/13988/xilinx-announce-new-rfsocs-for-5g-covering-sub6-ghz-and-mmwave|url-status=dead}}</ref> As of February, the portfolio was the only adaptable radio platform single chip that had been designed to address the industry's 5G network needs.<ref>{{Cite web|url=https://techstockobserver.com/xilinx-inc-s-nasdaqxlnx-new-innovative-zynq-ultrascale-rfsoc-portfolio-includes-full-sub-6-ghz-spectrum-that-supports-5g/|title=Xilinx, Inc.'s (NASDAQ:XLNX) New Innovative Zynq UltraScale+ RFSoC Portfolio Includes Full Sub-6 GHz Spectrum That Supports 5G|date=2019-02-28|website=Tech Stock Observer|language=en-US|access-date=2019-06-10|archive-date=2019-08-02|archive-url=https://web.archive.org/web/20190802151629/https://techstockobserver.com/xilinx-inc-s-nasdaqxlnx-new-innovative-zynq-ultrascale-rfsoc-portfolio-includes-full-sub-6-ghz-spectrum-that-supports-5g/|url-status=live}}</ref> The second announcement revealed that Xilinx and [[Samsung Electronics]] performed the world's first [[5G NR|5G New Radio]] (NR) commercial deployment in [[South Korea]].<ref name=":0a">{{Cite news|url=https://www.fiercewireless.com/wireless/xilinx-and-samsung-enable-a-5g-nr-commercial-deployment-south-korea|title=Xilinx and Samsung enable a 5G NR commercial deployment in South Korea|newspaper=Fierce Wireless|date=7 March 2019 |language=en|access-date=2019-06-14|archive-date=2019-03-07|archive-url=https://web.archive.org/web/20190307210525/https://www.fiercewireless.com/wireless/xilinx-and-samsung-enable-a-5g-nr-commercial-deployment-south-korea|url-status=live}}</ref><ref name=":1">{{Cite web|url=https://www.ecnmag.com/news/2019/02/xilinx-and-samsung-join-forces-and-enable-5g-new-radio-commercial-deployment|title=Xilinx and Samsung Join Forces and Enable 5G New Radio Commercial Deployment|last=King|first=Tierney|date=2019-02-25|website=Electronic Component News|language=en|access-date=2019-06-14|archive-date=2019-02-26|archive-url=https://web.archive.org/web/20190226080557/https://www.ecnmag.com/news/2019/02/xilinx-and-samsung-join-forces-and-enable-5g-new-radio-commercial-deployment|url-status=live}}</ref> The two companies developed and deployed 5G massive multiple-input, multiple-output (m-MIMO) and millimeter wave (mmWave) products using Xilinx's UltraScale+ platform.<ref name=":0a" /> The capabilities are essential for 5G commercialization.<ref name=":1" /> The companies also announced collaboration on Xilinx's Versal adaptable compute acceleration platform (ACAP) products that will deliver 5G services.<ref>{{Cite web|url=https://www.thefastmode.com/technology-solutions/14349-xilinx-samsung-to-develop-and-deploy-5g-massive-mimo-and-mmwave-solutions|title=Xilinx, Samsung to Develop and Deploy 5G Massive MIMO and mmWave Solutions|last=Sharma|first=Ray|website=www.thefastmode.com|language=en|access-date=2019-06-18|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022340/https://www.thefastmode.com/technology-solutions/14349-xilinx-samsung-to-develop-and-deploy-5g-massive-mimo-and-mmwave-solutions|url-status=live}}</ref> In February 2019, Xilinx introduced an HDMI 2.1 IP subsystem core, which enabled the company's devices to transmit, receive, and process up to [[8K resolution|8K]] (7680 x 4320 pixels) UHD video in media players, cameras, monitors, LED walls, projectors, and [[Kernel (operating system)|kernel]]-based [[virtual machine]]s.<ref>{{Cite web|url=https://www.eenewsanalog.com/news/xilinx-introduces-hdmi-21-ip-subsystem|title=Xilinx introduces HDMI 2.1 IP subsystem|date=2019-02-05|website=eeNews Analog|language=en|access-date=2019-06-26|archive-date=2019-06-26|archive-url=https://web.archive.org/web/20190626170829/https://www.eenewsanalog.com/news/xilinx-introduces-hdmi-21-ip-subsystem|url-status=live}}</ref><ref>{{Cite web|url=https://www.digitalsignagetoday.com/news/xilinx-unveils-hdmi-21-ip-subsystem-for-8k-video/|title=Xilinx unveils HDMI 2.1 IP subsystem for 8K video|date=2019-02-11|website=www.digitalsignagetoday.com|language=en|access-date=2019-06-26|archive-date=2019-06-26|archive-url=https://web.archive.org/web/20190626173830/https://www.digitalsignagetoday.com/news/xilinx-unveils-hdmi-21-ip-subsystem-for-8k-video/|url-status=live}}</ref>

In April 2019, Xilinx entered into a definitive agreement to acquire Solarflare Communications, Inc.<ref name="electronics360.globalspec.com">{{Cite web|url=https://electronics360.globalspec.com/article/13677/xilinx-to-buy-network-interface-card-vendor-solarflare|title=Xilinx to buy network interface card vendor Solarflare|website=Electronics 360|access-date=2019-05-29|archive-date=2019-05-29|archive-url=https://web.archive.org/web/20190529174631/https://electronics360.globalspec.com/article/13677/xilinx-to-buy-network-interface-card-vendor-solarflare|url-status=live}}</ref><ref name="Xilinx to Acquire Solarflare">{{Cite web|url=https://www.hpcwire.com/off-the-wire/xilinx-to-acquire-solarflare/|title=Xilinx to Acquire Solarflare|website=HPCwire|language=en-US|access-date=2019-05-29|archive-date=2019-04-25|archive-url=https://web.archive.org/web/20190425184051/https://www.hpcwire.com/off-the-wire/xilinx-to-acquire-solarflare/|url-status=live}}</ref> Xilinx became a strategic investor in Solarflare in 2017.<ref name="Xilinx to Acquire Solarflare"/><ref>{{Cite web|url=https://www.electronicsweekly.com/news/business/xilinx-buys-solarflare-2019-04/|title=Xilinx buys Solarflare|last=Manners|first=David|date=2019-04-25|website=Electronics Weekly|language=en-GB|access-date=2019-05-29|archive-date=2019-05-29|archive-url=https://web.archive.org/web/20190529174633/https://www.electronicsweekly.com/news/business/xilinx-buys-solarflare-2019-04/|url-status=live}}</ref> The companies have been collaborating since then on advanced networking technology, and in March 2019 demonstrated their first joint solution: a single-chip FPGA-based 100G [[Network interface controller|NIC]]. The acquisition enables Xilinx to combine its FPGA, MPSoC and ACAP solutions{{buzzword inline|date=July 2019}} with Solarflare's NIC technology.<ref>{{Cite web|url=https://www.hpcwire.com/off-the-wire/xilinx-to-acquire-solarflare/|title=Xilinx to Acquire Solarflare|website=HPCwire|language=en-US|access-date=2019-06-04|archive-date=2019-04-25|archive-url=https://web.archive.org/web/20190425184051/https://www.hpcwire.com/off-the-wire/xilinx-to-acquire-solarflare/|url-status=live}}</ref><ref name="electronics360.globalspec.com"/><ref>{{Cite web|url=https://www.eetimes.com/document.asp?doc_id=1334613#|title=Xilinx to Buy Networking Technology Firm Solarflare|last=McGrath|first=Dylan|website=EE Times|access-date=2019-06-04|archive-date=2019-08-02|archive-url=https://web.archive.org/web/20190802185804/https://www.eetimes.com/document.asp?doc_id=1334613|url-status=live}}</ref> In August 2019, Xilinx announced that the company would be adding the world's largest FPGA - the Virtex Ultrascale+ VU19P, to the 16&nbsp;nm Virtex Ultrascale+ family. The VU19P contains 35 billion transistors.<ref>{{Cite web|url=https://www.electronicsweekly.com/news/business/xilinx-claims-worlds-largest-fpga-2019-08/|title=Xilinx claims world's largest FPGA|last=Manners|first=David|date=2019-08-22|website=Electronics Weekly|language=en-GB|access-date=2019-09-20|archive-date=2019-09-20|archive-url=https://web.archive.org/web/20190920135959/https://www.electronicsweekly.com/news/business/xilinx-claims-worlds-largest-fpga-2019-08/|url-status=live}}</ref><ref>{{Cite web|url=https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|title=Xilinx Announces World Largest FPGA: Virtex Ultrascale+ VU19P with 9m Cells|last=Cutress|first=Dr Ian|website=www.anandtech.com|access-date=2019-09-20|archive-date=2019-09-13|archive-url=https://web.archive.org/web/20190913210759/https://www.anandtech.com/show/14798/xilinx-announces-world-largest-fpga-virtex-ultrascale-vu19p-with-9m-cells|url-status=dead}}</ref><ref>{{Cite news|url=https://www.allaboutcircuits.com/news/xilinx-claims-title-of-worlds-largest-fpga-with-new-vu19p/|title=Xilinx Claims Title of "World's Largest FPGA" with New VU19P|website=www.allaboutcircuits.com|language=en|access-date=2019-09-20|archive-date=2019-09-20|archive-url=https://web.archive.org/web/20190920135958/https://www.allaboutcircuits.com/news/xilinx-claims-title-of-worlds-largest-fpga-with-new-vu19p/|url-status=live}}</ref>

In June 2019, Xilinx announced that it was shipping its first Versal chips.<ref>{{Cite web|url=https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/|title=Xilinx ships first Versal ACAP chips that adapt to AI programs|last=Takashi|first=Dean|date=2019-06-18|website=Venture Beat|language=en|access-date=2020-02-26|archive-date=2020-05-21|archive-url=https://web.archive.org/web/20200521204130/https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/|url-status=live}}</ref> Using ACAP, the chips’ hardware and software can be programmed to run almost any kind of AI software.<ref>{{Cite web|url=https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/|title=Xilinx ships first Versal ACAP chips that adapt to AI programs|date=2019-06-18|website=VentureBeat|language=en-US|access-date=2020-03-09|archive-date=2020-05-21|archive-url=https://web.archive.org/web/20200521204130/https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/|url-status=live}}</ref><ref>{{Cite web|url=https://www.zdnet.com/article/xilinx-ships-its-versal-ai-core-versal-prime-key-parts-of-its-adaptive-compute-acceleration-platform/|title=Xilinx ships its Versal AI Core, Versal Prime, key parts of its adaptive compute acceleration platform|last=Dignan|first=Larry|website=ZDNet|language=en|access-date=2020-03-09|archive-date=2020-08-06|archive-url=https://web.archive.org/web/20200806160903/https://www.zdnet.com/article/xilinx-ships-its-versal-ai-core-versal-prime-key-parts-of-its-adaptive-compute-acceleration-platform/|url-status=live}}</ref> On October 1, 2019, Xilinx announced the launch of Vitis, a unified [[Free and open-source software|free and open source software]] platform that helps developers take advantage of hardware adaptability.<ref>{{Cite web|url=https://www.forbes.com/sites/davealtavilla/2019/10/01/xilinx-unveils-vitis-disruptive-open-source-design-software-tools-for-adaptable-processing-engines/|title=Xilinx Unveils Vitis, Breakthrough Open-Source Design Software For Adaptable Processing Engines|last=Altavilla|first=Dave|website=Forbes|language=en|access-date=2019-10-29|archive-date=2019-10-29|archive-url=https://web.archive.org/web/20191029175220/https://www.forbes.com/sites/davealtavilla/2019/10/01/xilinx-unveils-vitis-disruptive-open-source-design-software-tools-for-adaptable-processing-engines/|url-status=live}}</ref><ref>{{Cite web|url=https://www.semiaccurate.com/2019/10/07/xilinx-updates-their-tool-suite-with-vitis/|title=Xilinx updates their tool suite with Vitis|date=2019-10-07|website=SemiAccurate|language=en-US|access-date=2019-10-29}}</ref><ref>{{Cite web|url=https://www.convergedigest.com/2019/10/xilinx-intros-unified-software-platform.html|title=Xilinx intros Unified Software Platform for developers|access-date=2019-10-29|archive-date=2019-10-29|archive-url=https://web.archive.org/web/20191029175221/https://www.convergedigest.com/2019/10/xilinx-intros-unified-software-platform.html|url-status=live}}</ref>

In 2019, Xilinx exceeded $3 billion in annual revenues for the first time, announcing revenues of $3.06 billion, up 24% from the prior fiscal year.<ref>{{Cite web|url=https://www.hpcwire.com/off-the-wire/xilinx-reports-record-revenues-exceeding-3-billion-for-fiscal-2019/|title=Xilinx Reports Record Revenues Exceeding $3 Billion For Fiscal 2019|website=HPCwire|language=en-US|access-date=2019-05-15|archive-date=2019-04-25|archive-url=https://web.archive.org/web/20190425183630/https://www.hpcwire.com/off-the-wire/xilinx-reports-record-revenues-exceeding-3-billion-for-fiscal-2019/|url-status=live}}</ref><ref>{{Cite web|url=https://www.edacafe.com/nbc/articles/1/1666597/Xilinx-Reports-Record-Revenues-Exceeding-$3-Billion-Fiscal-2019|title=Xilinx Reports Record Revenues Exceeding $3 Billion For Fiscal 2019|website=EDACafe|access-date=2019-05-15|archive-date=2020-10-11|archive-url=https://web.archive.org/web/20201011022342/https://www.edacafe.com/nbc/articles/1/1666597/Xilinx-Reports-Record-Revenues-Exceeding-$3-Billion-Fiscal-2019|url-status=live}}</ref> Revenues were $828 million for the fourth quarter of the fiscal year 2019, up 4% from the prior quarter and up 30% year over year.<ref>{{Cite web|url=https://www.fudzilla.com/news/memory-and-storage/48606-xilinx-thrived-to-3-06b-in-fy2019|title=Xilinx made $3.06 billion in 2019|last=Abazovic|first=Fuad|website=www.fudzilla.com|language=en-gb|access-date=2019-05-17|archive-date=2019-05-17|archive-url=https://web.archive.org/web/20190517150528/https://www.fudzilla.com/news/memory-and-storage/48606-xilinx-thrived-to-3-06b-in-fy2019|url-status=live}}</ref> Xilinx's communications sector represented 41% of the revenue; the industrial, aerospace and defense sectors represented 27%; the data center and test, measurement & emulation (TME) sectors accounted for 18%; and the automotive, broadcast and consumer markets contributed 14%.<ref>{{Cite web|url=https://www.fudzilla.com/news/memory-and-storage/48606-xilinx-thrived-to-3-06b-in-fy2019|title=Xilinx made $3.06 billion in 2019|last=Abazovic|first=Fuad|website=www.fudzilla.com|language=en-gb|access-date=2019-05-24|archive-date=2019-05-17|archive-url=https://web.archive.org/web/20190517150528/https://www.fudzilla.com/news/memory-and-storage/48606-xilinx-thrived-to-3-06b-in-fy2019|url-status=live}}</ref>

In August 2020, [[Subaru]] announced the use of one of Xilinx's chips as processing power for camera images in its [[Advanced driver-assistance systems|driver-assistance system]].<ref>{{Cite news|last=Nellis|first=Stephen|date=2020-08-20|title=Subaru taps Xilinx for key chip in driver-assistance system|language=en|work=Reuters|url=https://www.reuters.com/article/us-xilinx-subaru-idUSKCN25G05V|access-date=2020-09-22|archive-date=2020-10-01|archive-url=https://web.archive.org/web/20201001230425/https://www.reuters.com/article/us-xilinx-subaru-idUSKCN25G05V|url-status=live}}</ref> In September 2020, Xilinx announced its new [[chipset]], the T1 Telco Accelerator card, that can be used for units running on an open RAN 5G network.<ref>{{Cite news|title=Open RAN connects Xilinx with network operators|url=https://www.lightreading.com/open-ran/open-ran-connects-xilinx-with-network-operators/d/d-id/763871|url-status=live|archive-url=https://web.archive.org/web/20200919082350/https://www.lightreading.com/open-ran/open-ran-connects-xilinx-with-network-operators/d/d-id/763871|archive-date=2020-09-19|access-date=2020-09-29|website=Light Reading|language=en}}</ref>
[[File:AMD_Xilinx_logo.svg|thumb|Logo of Xilinx following AMD's acquisition of the company from 2022 until 2023]]
On October 27, 2020, [[AMD]] reached an agreement to acquire Xilinx in a [[stock swap|stock-swap]] deal, valuing the company at $35 billion. The deal was expected to close by the end of 2021.<ref>{{cite news|url=https://www.nytimes.com/2020/10/27/technology/amd-xilinx-35-billion-stock-deal.html|title=AMD Agrees to Buy Xilinx for $35 Billion in Stock|work=[[The New York Times]]|last=Lombardo|first=Cara|date=October 27, 2020|access-date=October 27, 2020}}</ref> Their stockholders approved the acquisition on April 7, 2021.<ref>{{cite news|url=https://www.xilinx.com/news/press/2021/amd-and-xilinx-stockholders-overwhelmingly-approve-amd-s-acquisition-of-xilinx.html|title=AMD and Xilinx Stockholders Overwhelmingly Approve AMD's Acquisition of Xilinx|work=Xilinx|date=2021-04-07|access-date=2021-05-10}}</ref> The deal was completed on February 14, 2022.<ref>{{Cite web|date=February 14, 2022|title=AMD Completes Acquisition of Xilinx|url=https://www.amd.com/en/press-releases/2022-02-14-amd-completes-acquisition-xilinx|website=AMD}}</ref> Since the acquisition was completed, all Xilinx products are co-branded as ''AMD Xilinx''; started in June 2023, all Xilinx's products are now being consolidated under AMD's branding.

In December 2020, Xilinx announced they were acquiring the assets of Falcon Computing Systems to enhance the [[Free and open-source software|free and open source]] Vitis platform, a design software for adaptable processing engines to enable highly optimized domain specific accelerators.<ref>{{Cite web|date=2020-12-15|title=Advancing HLS Adoption – Xilinx, Silexica, Falcon|url=https://www.eejournal.com/article/advancing-hls-adoption-xilinx-silexica-falcon/|access-date=2020-12-18|website=EEJournal|language=en-US}}</ref>

In April 2021, Xilinx announced a collaboration with [[Mavenir]] to boost cell phone tower capacity for open [[5G]] networks.<ref>{{Cite web|date=2021-04-13|title=Xilinx, Mavenir partner to boost open 5G network capacity|url=https://www.reuters.com/technology/xilinx-mavenir-partner-boost-open-5g-network-capacity-2021-04-13/|access-date=2021-05-18|website=Reuters}}</ref> That same month, the company unveiled the Kria portfolio, a line of small form factor [[System on module|system-on-modules]] (SOMs) that come with a pre-built software stack to simplify development.<ref>{{Cite web|date=2021-04-20|title=Xilinx Introduces Kria SoMs|url=https://www.eejournal.com/article/xilinx-introduces-kria-soms/|access-date=2021-05-27|website=EEJournal|language=en-US}}</ref> In June, Xilinx announced it was acquiring German software developer Silexica, for an undisclosed amount.<ref>{{Cite web|last=Hayes|first=Caroline|date=2021-06-15|title=Xilinx acquires Silexica and its C/C++ tools|url=https://www.electronicsweekly.com/news/design/eda-and-ip/xilinx-acquires-silexica-c-c-tools-2021-06/|access-date=2021-07-08|website=Electronics Weekly|language=en}}</ref>

==Technology==
[[File:Xilinx Spartan-3E (XC3S500E).jpg|thumb|The Spartan-3 platform was the industry's first 90nm FPGA, delivering more functionality and bandwidth per dollar than was previously possible.]]
{{Multiple issues|section=yes|
{{Overly detailed|section|date=March 2020}}
{{Promotional section|date=June 2020}}
}}
Xilinx designs and develops programmable logic products, including integrated circuits (ICs), software design tools, predefined system functions delivered as intellectual property (IP) cores, design services, customer training, field engineering and technical support.<ref name="two"/> Xilinx sells both FPGAs and CPLDs for electronic equipment manufacturers in end markets such as [[communications]], industrial, [[consumer]], [[automotive]] and [[data processing]].<ref>Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_66/xc_pdf/p20-26_66_F_XiASIM1.pdf Building Automotive Driver Assistance System Algorithms with Xilinx FPGA platforms] {{webarchive|url=https://web.archive.org/web/20090327150948/http://www.xilinx.com/publications/xcellonline/xcell_66/xc_pdf/p20-26_66_F_XiASIM1.pdf |date=2009-03-27 }}." October, 2008. Retrieved January 28, 2009.</ref><ref>Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p22-26_65_XIAD.pdf Taking Designs to New Heights with Space-Grade Virtex-4QV FPGAs] {{webarchive|url=https://web.archive.org/web/20090327150956/http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p22-26_65_XIAD.pdf |date=2009-03-27 }}." July, 2008. Retrieved January 28, 2009.</ref><ref>Xcell Journal, "[http://cde.cerosmedia.com/1R4975d4df9f378012.cde A Flexible Platform for Satellite-Based High-Performance Computing] {{Webarchive|url=https://web.archive.org/web/20090202064610/http://cde.cerosmedia.com/1R4975d4df9f378012.cde |date=2009-02-02 }}". January 2009 p 22. Retrieved January 28, 2009.</ref><ref>Xcell Journal, "[http://cde.cerosmedia.com/1R4975d4df9f378012.cde Virtex-5 Powers Reconfigurable Rugged PC] {{Webarchive|url=https://web.archive.org/web/20090202064610/http://cde.cerosmedia.com/1R4975d4df9f378012.cde |date=2009-02-02 }}." January 2009 p28. Retrieved January 28, 2009.</ref><ref>Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p18-21_65_F_ASIM.pdf Exploring and Prototyping Designs for Biomedical Applications] {{webarchive|url=https://web.archive.org/web/20090327150949/http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p18-21_65_F_ASIM.pdf |date=2009-03-27 }}." July 2008. Retrieved January 28, 2009.</ref><ref>Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_66/xc_pdf/p28-32_66_F_XiAISM2.pdf Security Video Analytics on Xilinx Spartan-3A DSP] {{webarchive|url=https://web.archive.org/web/20090327150947/http://www.xilinx.com/publications/xcellonline/xcell_66/xc_pdf/p28-32_66_F_XiAISM2.pdf |date=2009-03-27 }}." October 2008. Retrieved January 28, 2009.</ref><ref>Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_66/xc_pdf/p34-39_66_F_XiWild.pdf A/V Monitoring System Rides Virtex-5] {{webarchive|url=https://web.archive.org/web/20090327150958/http://www.xilinx.com/publications/xcellonline/xcell_66/xc_pdf/p34-39_66_F_XiWild.pdf |date=2009-03-27 }}." October 2008. Retrieved January 28, 2009.</ref>

Xilinx's FPGAs have been used for the [[A Large Ion Collider Experiment|ALICE]] (A Large Ion Collider Experiment) at the [[CERN]] European laboratory on the [[France|French]]-[[Switzerland|Swiss]] border to map and disentangle the trajectories of thousands of [[subatomic particles]].<ref>Xcell Journal, "[http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p28_31_65_F_XiWild.pdf CERN Scientists Use Virtex-4 FPGAs for Big Bang Research] {{webarchive |url=https://web.archive.org/web/20090327150946/http://www.xilinx.com/publications/xcellonline/xcell_65/xc_pdf/p28_31_65_F_XiWild.pdf |date=March 27, 2009}}." July 2008. Retrieved January 28, 2009.</ref> Xilinx has also engaged in a partnership with the [[United States Air Force]] Research Laboratory's Space Vehicles Directorate to develop FPGAs to withstand the damaging effects of [[space radiation|radiation in space]], which are 1,000 times less sensitive to space radiation than the commercial equivalent, for deployment in new satellites.<ref name=Kleiman>By Michael Kleinman, US Airforce News. “[https://www.af.mil/News/story/storyID/123222935/ New computer chip cuts costs, adds efficiency to space systems.]” September 21, 2010. Retrieved September 23, 2010.</ref> Xilinx FPGAs can run a regular embedded OS (such as [[Linux]] or [[vxWorks]]) and can implement processor peripherals in programmable logic.<ref name="two" /> The Virtex-II Pro, Virtex-4, Virtex-5, and Virtex-6 FPGA families, which include up to two embedded [[PowerPC]] cores, are targeted to the needs of [[system-on-chip]] (SoC) designers.<ref>{{Cite web |url=http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf |title=Virtex-II Pro Datasheet |access-date=2009-01-29 |archive-date=2009-03-27 |archive-url=https://web.archive.org/web/20090327150952/http://www.xilinx.com/support/documentation/data_sheets/ds083.pdf |url-status=live }}</ref><ref name="eweekly">{{Cite web |url=http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf |title=Virtex-4 Family Overview |access-date=2009-01-29 |archive-date=2009-02-06 |archive-url=https://web.archive.org/web/20090206003430/http://www.xilinx.com/support/documentation/data_sheets/ds112.pdf |url-status=live }}</ref><ref>Richard Wilson, ElectronicsWeekly.com, "[http://www.electronicsweekly.com/Articles/2009/02/02/45377/xilinx-repositions-fpgas-with-soc-move.htm Xilinx repositions FPGAs with SoC move] {{Webarchive|url=https://web.archive.org/web/20201011022347/https://www.electronicsweekly.com/news/products/ |date=2020-10-11 }}." February 2, 2009. Retrieved on February 2, 2009.</ref>

Xilinx's IP cores include IP for simple functions ([[Binary-coded decimal|BCD]] encoders, counters, etc.), for domain specific cores ([[digital signal processing]], [[Fast Fourier transform|FFT]] and [[Free ideal ring|FIR]] cores) to complex systems (multi-gigabit networking cores, the MicroBlaze soft microprocessor and the compact Picoblaze [[microcontroller]]).<ref name="two"/> Xilinx also creates custom cores for a fee.{{Citation needed|date=June 2019}}

The main design toolkit Xilinx provides engineers is the [[Xilinx Vivado|Vivado Design Suite]], an [[Integrated development environment|integrated design environment]] (IDE) with a system-to-IC level tools built on a shared scalable data model and a common debug environment. Vivado includes electronic system level (ESL) design tools for synthesizing and verifying C-based algorithmic IP; standards based packaging of both algorithmic and RTL IP for reuse; standards based IP stitching and systems integration of all types of system building blocks; and the verification of blocks and systems.<ref>EDN. "[http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X] {{Webarchive|url=https://web.archive.org/web/20130116054344/http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X |date=2013-01-16 }}." Jun 15, 2012. Retrieved Jun 25, 2013.</ref> A free version WebPACK Edition of Vivado provides designers with a limited version of the design environment.<ref>Clive Maxfield, [[EE Times]]. "[http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4403821/WebPACK-edition-of-Xilinx-Vivado-Design-Suite-now-available WebPACK edition of Xilinx Vivado Design Suite now available] {{Webarchive|url=https://web.archive.org/web/20130211010306/http://eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4403821/WebPACK-edition-of-Xilinx-Vivado-Design-Suite-now-available |date=2013-02-11 }}." Dec 20, 2012. Retrieved Jun 25, 2013.</ref>

Xilinx's Embedded Developer's Kit (EDK) supports the embedded [[PowerPC]] 405 and 440 cores (in Virtex-II Pro and some Virtex-4 and -5 chips) and the [[Microblaze]] core. Xilinx's System Generator for DSP implements DSP designs on Xilinx FPGAs. A freeware version of its EDA software called ISE WebPACK is used with some of its non-high-performance chips. Xilinx is the only (as of 2007) FPGA vendor to distribute a native Linux freeware synthesis toolchain.<ref name="cheung">Ken Cheung, EDA Geek. “[http://edageek.com/2007/03/26/xilinx-edk/ Xilinx Rolls Out Embedded Development Kit 9.li] {{Webarchive|url=https://web.archive.org/web/20150320135455/http://edageek.com/2007/03/26/xilinx-edk/ |date=2015-03-20 }}.” March 26, 2007. Retrieved June 10, 2010.</ref>

Xilinx announced the architecture for a new [[ARM Cortex-A9]]-based platform for embedded systems designers, that combines the software programmability of an embedded processor with the hardware flexibility of an FPGA.<ref name="EETimesApril27">Rich Nass, [[EE Times]]. "[http://www.eetimes.com/electronics-products/processors/4115523/Xilinx-puts-ARM-core-into-its-FPGAs Xilinx puts ARM core into its FPGAs] {{Webarchive|url=https://web.archive.org/web/20101123194443/http://www.eetimes.com/electronics-products/processors/4115523/Xilinx-puts-ARM-core-into-its-FPGAs |date=2010-11-23 }}." April 27, 2010. Retrieved February 14, 2011.</ref><ref name="DesignReuseMay3">Steve Leibson, Design-Reuse. "[http://www.design-reuse.com/industryexpertblogs/23302/xilinx-arm-based-extensible-processing-platform.html Xilinx redefines the high-end microcontroller with its ARM-based Extensible Processing Platform - Part 1] {{Webarchive|url=https://web.archive.org/web/20110709014357/http://www.design-reuse.com/industryexpertblogs/23302/xilinx-arm-based-extensible-processing-platform.html |date=2011-07-09 }}." May 3, 2010. Retrieved February 15, 2011.</ref> The new architecture abstracts much of the hardware burden away from the [[embedded software]] developers' point of view, giving them an unprecedented level of control in the development process.<ref name="EETimesApril28">Toni McConnel, [[EE Times]]. "[http://www.eetimes.com/electronics-products/processors/4115537/ESC--Xilinx-Extensible-Processing-Platform-combines-best-of-serial-and-parallel-processing Xilinx Extensible Processing Platform combines best of serial and parallel processing] {{Webarchive|url=https://web.archive.org/web/20111024163351/http://www.eetimes.com/electronics-products/processors/4115537/ESC--Xilinx-Extensible-Processing-Platform-combines-best-of-serial-and-parallel-processing|date=2011-10-24}}." April 28, 2010. Retrieved February 14, 2011.</ref><ref name="FPGABlogApril27">Ken Cheung, FPGA Blog. "[http://fpgablog.com/posts/arm-cortex-mpcore/ Xilinx Extensible Processing Platform for Embedded Systems] {{Webarchive|url=https://web.archive.org/web/20150108233522/http://fpgablog.com/posts/arm-cortex-mpcore/|date=2015-01-08}}." April 27, 2010. Retrieved February 14, 2011.</ref><ref name="EETimesApril27"/><ref name="DesignReuseMay3"/> With this platform, software developers can leverage their existing system code based on ARM technology and utilize vast off-the-shelf open-source and commercially available software component libraries.<ref name="EETimesApril28"/><ref name="FPGABlogApril27"/><ref name="EETimesApril27"/><ref name="DesignReuseMay3"/> Because the system boots an [[Operating system|OS]] at reset, software development can get under way quickly within familiar development and debug environments using tools such as [[ARM architecture family|ARM]]'s RealView development suite and related third-party tools, Eclipse-based IDEs, GNU, the Xilinx Software Development Kit and others.<ref name="EETimesApril28"/><ref name="FPGABlogApril27"/><ref name="EETimesApril27"/><ref name="DesignReuseMay3"/> In early 2011, Xilinx began shipping the Zynq-7000 SoC platform immerses ARM multi-cores, programmable logic fabric, DSP data paths, memories and [[Input/output|I/O]] functions in a dense and configurable mesh of interconnect.<ref name="EETimesMarch1">Colin Holland, [[EE Times]]. "[http://www.eetimes.com/electronics-news/4213637/Xilinx-provides-first-product-details-for-EPP-ARM-based-devices Xilinx provides details on ARM-based devices] {{Webarchive|url=https://web.archive.org/web/20111225132754/http://www.eetimes.com/electronics-news/4213637/Xilinx-provides-first-product-details-for-EPP-ARM-based-devices |date=2011-12-25 }}." March 1, 2011. Retrieved March 1, 2011.</ref><ref name="EmbeddedWorldMarch1">Laura Hopperton, Newelectronics. "[http://www.newelectronics.co.uk/electronics-news/embedded-world-xilinx-introduces-industrys-first-extensible-processing-platform/31861/ Embedded world: Xilinx introduces 'industry's first' extensible processing platform] {{Webarchive|url=https://web.archive.org/web/20171207013158/http://www.newelectronics.co.uk/electronics-news/embedded-world-xilinx-introduces-industrys-first-extensible-processing-platform/31861/ |date=2017-12-07 }}." March 1, 2011. Retrieved March 1, 2011.</ref> The platform targets embedded designers working on market applications that require multi-functionality and real-time responsiveness, such as automotive driver assistance, intelligent video surveillance, industrial automation, aerospace and defense, and next-generation wireless.<ref name="EETimesApril28"/><ref name="FPGABlogApril27"/><ref name="EETimesApril27"/><ref name="DesignReuseMay3"/>

Following the introduction of its 28&nbsp;nm 7-series FPGAs, Xilinx revealed that several of the highest-density parts in those FPGA product lines will be constructed using multiple dies in one package, employing technology developed for 3D construction and stacked-die assemblies.<ref name=ednEurope>EDN Europe. "[http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html Xilinx adopts stacked-die 3D packaging] {{webarchive |url=https://web.archive.org/web/20110219182606/http://www.edn-europe.com/xilinxadoptsstackeddie3dpackaging+article+4461+Europe.html |date=February 19, 2011 }}." November 1, 2010. Retrieved May 12, 2011.</ref><ref name=lawrence>{{cite web |url=http://www.theinquirer.net/inquirer/news/1811460/fpga-manufacturer-claims-beat-moores-law |author=Lawrence Latif |title=FPGA manufacturer claims to beat Moore's Law |date=October 27, 2010 |work=[[The Inquirer]] |url-status=unfit |archive-url=https://web.archive.org/web/20111121043259/http://www.theinquirer.net/inquirer/news/1811460/fpga-manufacturer-claims-beat-moores-law |archive-date=2011-11-21 }}</ref> The company's stacked silicon interconnect (SSI) technology stacks several (three or four) active FPGA dies side by side on a silicon [[interposer]]&nbsp;– a single piece of silicon that carries passive interconnect. The individual FPGA dies are conventional, and are flip-chip mounted by microbumps on to the interposer. The interposer provides direct interconnect between the FPGA dies, with no need for transceiver technologies such as high-speed [[SerDes]].<ref name=ednEurope/><ref name=lawrence/><ref>Clive Maxfield, EETimes. "[http://www.eetimes.com/electronics-blogs/other/4210170/Xilinx-multi-FPGA-provides-mega-boost-re-capacity--performance--and-power-efficiency- Xilinx multi-FPGA provides mega-boost re capacity, performance, and power efficiency!] {{Webarchive|url=https://web.archive.org/web/20101031130715/http://www.eetimes.com/electronics-blogs/other/4210170/Xilinx-multi-FPGA-provides-mega-boost-re-capacity--performance--and-power-efficiency- |date=2010-10-31 }}." October 27, 2010. Retrieved May 12, 2011.</ref> In October 2011, Xilinx shipped the first FPGA to use the new technology, the Virtex-7 2000T FPGA, which includes 6.8 billion transistors and 20 million ASIC gates.<ref name=don1025>Don Clark, The Wall Street Journal. "[https://blogs.wsj.com/digits/2011/10/25/xilinx-says-four-chips-act-like-one-giant/?KEYWORDS=Xilinx Xilinx Says Four Chips Act Like One Giant] {{Webarchive|url=https://web.archive.org/web/20180612143245/https://blogs.wsj.com/digits/2011/10/25/xilinx-says-four-chips-act-like-one-giant/?KEYWORDS=Xilinx |date=2018-06-12 }}." October 25, 2011. Retrieved November 18, 2011.</ref><ref name=clive1025>Clive Maxfield, EETimes. "[http://www.eetimes.com/electronics-news/4230048/Xilinx-announces-world-s-highest-capacity-FPGA Xilinx tips world’s highest capacity FPGA] {{Webarchive|url=https://web.archive.org/web/20111127172525/http://www.eetimes.com/electronics-news/4230048/Xilinx-announces-world-s-highest-capacity-FPGA |date=2011-11-27 }}." October 25, 2011. Retrieved November 18, 2011.</ref><ref name=david1025>David Manners, Electronics Weekly. "[http://www.electronicsweekly.com/Articles/25/10/2011/52110/xilinx-launches-20m-asic-gate-stacked-silicon-fpga.htm Xilinx launches 20m ASIC gate stacked silicon FPGA] {{Webarchive|url=https://web.archive.org/web/20130116054207/http://www.electronicsweekly.com/Articles/25/10/2011/52110/xilinx-launches-20m-asic-gate-stacked-silicon-fpga.htm |date=2013-01-16 }}." October 25, 2011. Retrieved November 18, 2011.</ref><ref name="scieng1026">Tim Pietruck, SciEngines GmbH. "[http://www.sciengines.com/company/news-a-events.html] {{Webarchive|url=https://web.archive.org/web/20111218192558/http://www.sciengines.com/company/news-a-events.html|date=2011-12-18}}." December 21, 2011 - RIVYERA-V7 2000T FPGA computer with the newest and largest Xilinx Virtex-7</ref> The following spring, Xilinx used 3D technology to ship the Virtex-7 HT, the industry's first heterogeneous FPGAs, which combine high bandwidth FPGAs with a maximum of sixteen 28&nbsp;Gbit/s and seventy-two 13.1&nbsp;Gbit/s transceivers to reduce power and size requirements for key Nx100G and 400G line card applications and functions.<ref>Tiernan Ray, Barrons. "[http://blogs.barrons.com/techtraderdaily/2012/05/30/xilinx-3-d-chip-a-route-to-more-complex-semiconductors./ Xilinx: 3-D Chip a Route to More Complex Semiconductors] {{Webarchive|url=https://web.archive.org/web/20150927033455/http://blogs.barrons.com/techtraderdaily/2012/05/30/xilinx-3-d-chip-a-route-to-more-complex-semiconductors./ |date=2015-09-27 }}." May 30, 2012. Retrieved Jan 9, 2013.</ref><ref>Loring Wirbel, EDN. "[http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/xilinx-virtex-7-ht-devices-use-3d-stacking-high-end-communication-edge Xilinx Virtex-7 HT devices use 3D stacking for a high-end communication edge] {{webarchive|url=https://web.archive.org/web/20130116054218/http://www.fpgagurus.edn.com/blog/fpga-gurus-blog/xilinx-virtex-7-ht-devices-use-3d-stacking-high-end-communication-edge |date=2013-01-16 }}." May 30, 2012. Retrieved Jan 9, 2013.</ref>

In January 2011, Xilinx acquired design tool firm AutoESL Design Technologies and added System C high-level design for its 6- and 7-series FPGA families.<ref name="EETimesJan31">Dylan McGrath, [[EE Times]]. "[http://www.eetimes.com/electronics-news/4212668/Xilinx-buys-high-level-synthesis-EDA-vendor Xilinx buys high-level synthesis EDA vendor] {{Webarchive|url=https://web.archive.org/web/20111017170928/http://www.eetimes.com/electronics-news/4212668/Xilinx-buys-high-level-synthesis-EDA-vendor |date=2011-10-17 }}." January 31, 2011. Retrieved February 15, 2011.</ref> The addition of AutoESL tools extended the design community for FPGAs to designers more accustomed to designing at a higher level of abstraction using [[C (programming language)|C]], [[C++]] and System C.<ref name="ElectronicsWeelyJan31">Richard Wilson, ElectronicsWeekly.com. "[http://www.electronicsweekly.com/Articles/2011/01/31/50386/xilinx-acquires-esl-firm-to-make-fpgas-easier-to-use.htm Xilinx acquires ESL firm to make FPGAs easier to use] {{Webarchive|url=https://web.archive.org/web/20110710181038/http://www.electronicsweekly.com/Articles/2011/01/31/50386/xilinx-acquires-esl-firm-to-make-fpgas-easier-to-use.htm |date=2011-07-10 }}." January 31, 2011. Retrieved February 15, 2011.</ref>

In April 2012, Xilinx introduced a revised version of its toolset for programmable systems, called [[Xilinx Vivado|Vivado Design Suite]]. This IP and system-centric design software supports newer high capacity devices, and speeds the design of programmable logic and I/O.<ref>Brian Bailey, [[EE Times]]. "[http://www.eetimes.com/electronics-products/ip-eda-products/4371701/Second-generation-for-FPGA-software Second generation for FPGA software] {{Webarchive|url=https://web.archive.org/web/20130116073612/http://www.eetimes.com/electronics-products/ip-eda-products/4371701/Second-generation-for-FPGA-software |date=2013-01-16 }}." Apr 25, 2012. Retrieved Jan 3, 2013.</ref> Vivado provides faster integration and implementation for programmable systems into devices with 3D stacked silicon interconnect technology, ARM processing systems, analog mixed signal (AMS), and many [[Semiconductor intellectual property core|semiconductor intellectual property]] (IP) cores.<ref name="EDN15Jun2012">EDN. "[http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X The Vivado Design Suite accelerates programmable systems integration and implementation by up to 4X] {{Webarchive|url=https://web.archive.org/web/20130116054344/http://www.edn.com/electronics-products/other/4375467/The-Vivado-Design-Suite-accelerates-programmable-systems-integration-by-up-to-4X |date=2013-01-16 }}." Jun 15, 2012. Retrieved Jan 3, 2013.</ref>

In July 2019, Xilinx acquired NGCodec, developers of FPGA [[Hardware acceleration|accelerated]] video encoders for [[Video hosting service|video streaming]], [[cloud gaming]] and cloud [[mixed reality]] services. NGCodec video encoders include support for [[H.264/MPEG-4 AVC|H.264/AVC]], [[HEVC|H.265/HEVC]], [[VP9]] and [[AV1]], with planned future support for [[Versatile Video Coding|H.266/VVC]] and AV2.<ref>{{Cite web|url=https://forums.xilinx.com/t5/Xilinx-Xclusive-Blog/Buffer-Be-Gone-Xilinx-Acquires-NGCodec-to-Deliver-High-Quality/ba-p/990357|title=Buffer Be Gone! Xilinx Acquires NGCodec to Deliver High-Quality, Efficient Cloud Video Encoding|date=2019-07-01|website=forums.xilinx.com|language=en|access-date=2019-07-02|archive-date=2019-07-02|archive-url=https://web.archive.org/web/20190702110951/https://forums.xilinx.com/t5/Xilinx-Xclusive-Blog/Buffer-Be-Gone-Xilinx-Acquires-NGCodec-to-Deliver-High-Quality/ba-p/990357|url-status=live}}</ref><ref>{{Cite web|url=https://ngcodec.com/|title=NGCodec|website=NGCodec|language=en-US|access-date=2019-07-02|archive-date=2019-07-01|archive-url=https://web.archive.org/web/20190701182423/https://ngcodec.com/|url-status=live}}</ref>

In May 2020, Xilinx installed its first Adaptive Compute Cluster (XACC) at ETH Zurich in Switzerland.<ref name=":5">{{Cite web|title=Xilinx to establish adaptive compute research clusters|url=https://www.newelectronics.co.uk/electronics-news/xilinx-to-establish-adaptive-compute-research-clusters/226811/|url-status=live|access-date=2020-06-09|website=NewsElectronics|date=5 June 2020 |archive-date=2020-06-09|archive-url=https://web.archive.org/web/20200609154751/https://www.newelectronics.co.uk/electronics-news/xilinx-to-establish-adaptive-compute-research-clusters/226811/}}</ref> The XACCs provide infrastructure and funding to support research in adaptive compute acceleration for high performance computing (HPC).<ref name=":5" /> The clusters include high-end servers, Xilinx Alveo accelerator cards, and high speed networking.<ref>{{Cite web|last=Brueckner|first=Rich|date=2020-05-05|title=Xilinx Establishes FPGA Adaptive Compute Clusters at Leading Universities|url=https://insidehpc.com/2020/05/xilinx-establishes-fpga-adaptive-compute-clusters-at-leading-universities/|access-date=2020-06-23|website=insideHPC|language=en-US|archive-date=2020-06-26|archive-url=https://web.archive.org/web/20200626140054/https://insidehpc.com/2020/05/xilinx-establishes-fpga-adaptive-compute-clusters-at-leading-universities/|url-status=live}}</ref> Three other XACCs will be installed at the [[University of California, Los Angeles]] (UCLA); the [[University of Illinois at Urbana Champaign]] (UIUC); and the [[National University of Singapore]] (NUS).<ref name=":5" /><ref>{{Cite web|date=2020-05-06|title=Xilinx forms university adaptive compute research clusters|url=https://www.eenewsembedded.com/news/xilinx-forms-university-adaptive-compute-research-clusters|url-status=live|archive-url=https://web.archive.org/web/20200618153831/https://www.eenewsembedded.com/news/xilinx-forms-university-adaptive-compute-research-clusters|archive-date=2020-06-18|access-date=2020-06-17|website=eeNews Embedded|language=en}}</ref>

==Family lines of products==
[[File:ZyXEL ZyAIR B-2000 - Xilinx XC9536XL-8842.jpg|thumb|CPLD Xilinx XC9536XL]]

Before 2010, Xilinx offered two main FPGA families: the high-performance [[Virtex (FPGA)|Virtex]] series and the high-volume Spartan series, with a cheaper EasyPath option for ramping to volume production.<ref name="thirtythree"/> The company also provided two [[Complex programmable logic device|CPLD]] lines: the CoolRunner and the 9500 series. Each model series had been released in multiple generations since its launch.<ref name="Brown">Stephen Brown and Johnathan Rose, University of Toronto. “[https://www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdf Architecture of FPGAs and CPLDs: A Tutorial] {{Webarchive|url=https://web.archive.org/web/20100709205713/http://www.eecg.toronto.edu/~jayar/pubs/brown/survey.pdf |date=2010-07-09 }}.” Retrieved June 10, 2010.</ref> With the introduction of its 28&nbsp;nm FPGAs in June 2010, Xilinx replaced the high-volume Spartan family with the medium-cost Kintex family and the low-cost Artix family.<ref name="EET">[[EE Times]]. “[https://www.eetimes.com/electronics-products/fpga-pld-products/4200530/Xilinx-to-offer-three-classes-of-FPGAs-at-28-nm Xilinx to offer three classes of FPGAs at 28-nm] {{Webarchive|url=https://web.archive.org/web/20101123194437/http://www.eetimes.com/electronics-products/fpga-pld-products/4200530/Xilinx-to-offer-three-classes-of-FPGAs-at-28-nm |date=2010-11-23 }}.” June 21, 2010. Retrieved September 23, 2010.</ref><ref name="Morris">Kevin Morris, FPGA Journal. “[http://www.techfocusmedia.net/fpgajournal/feature_articles/20100622-virtex/ Veni! Vidi! Virtex! (and Kintex and Artix Too)] {{webarchive|url=https://web.archive.org/web/20101123043600/http://www.techfocusmedia.net/fpgajournal/feature_articles/20100622-virtex/|date=November 23, 2010}}.” June 21, 2010. Retrieved September 23, 2010.</ref>

Xilinx's newer FPGA products use a [[high-κ dielectric|High-κ/Metal-Gate Stack]] (HKMG) process, which reduces static power consumption while increasing logic capacity.<ref name="harris">Daniel Harris, Electronic Design. “[https://electronicdesign.com/article/digital/if-only-the-original-spartans-could-have-thrived-o.aspx If Only the Original Spartans Could Have Thrived On So Little Power] {{webarchive|url=https://web.archive.org/web/20111205015520/http://electronicdesign.com/article/digital/if-only-the-original-spartans-could-have-thrived-o.aspx|date=2011-12-05}}.” February 27, 2008. Retrieved January 20, 2008.</ref> In 28&nbsp;nm devices, static power accounts for much and sometimes most of the total power dissipation. Virtex-6 and Spartan-6 FPGA families are said to consume 50 percent less power, and have up to twice the logic capacity compared to the previous generation of Xilinx FPGAs.<ref name="eweekly"/><ref name="eetimes">Peter Clarke, [[EE Times]], "[https://www.eetimes.com/news/latest/showArticle.jhtml?articleID=213000271 Xilinx launches Spartan-6, Virtex-6 FPGAs] {{Webarchive|url=https://web.archive.org/web/20130523202018/http://www.eetimes.com/news/latest/showArticle.jhtml?articleID=213000271 |date=2013-05-23 }}." February 2, 2009. Retrieved February 2, 2009</ref><ref name="EDN">Ron Wilson, EDN, "[https://www.edn.com/article/CA6633947.html Xilinx FPGA introductions hint at new realities] {{webarchive|url=https://archive.today/20130122084337/http://www.edn.com/article/CA6633947.html |date=2013-01-22 }}." February 2, 2009. Retrieved on February 2, 2009.</ref>

In June 2010, Xilinx introduced the Xilinx 7 series: the Virtex-7, Kintex-7, and Artix-7 families, promising improvements in system power, performance, capacity, and price. These new FPGA families are manufactured using [[TSMC]]'s 28&nbsp;nm HKMG process.<ref name="xilinx7">Brent Przybus, Xilinx, "[https://www.xilinx.com/support/documentation/white_papers/wp373_V7_K7_A7_Devices.pdf Xilinx Redefines Power, Performance, and Design Productivity with Three New 28 nm FPGA Families: Virtex-7, Kintex-7, and Artix-7 Devices] {{Webarchive|url=https://web.archive.org/web/20100704231736/http://www.xilinx.com/support/documentation/white_papers/wp373_V7_K7_A7_Devices.pdf |date=2010-07-04 }}." June 21, 2010. Retrieved on June 22, 2010.</ref> The 28&nbsp;nm series 7 devices feature a 50 percent power reduction compared to the company's 40&nbsp;nm devices and offer capacity of up to 2 million logic cells.<ref name= EET /> Less than one year after announcing the 7 series 28&nbsp;nm FPGAs, Xilinx shipped the world's first 28&nbsp;nm FPGA device, the Kintex-7.<ref>Convergedigest. "[https://www.convergedigest.com/Silicon/siliconarticle.asp?ID=32793&ctgy=%27%20target Xilinx Ships First 28nm FPGA]{{Dead link|date=August 2018 |bot=InternetArchiveBot |fix-attempted=yes }}." Mar 18, 2011. Retrieved May 11, 2012.</ref><ref>Clive Maxfield, EETimes. "[https://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4214345/Xilinx-ships-first-28nm-Kintex-7-FPGAs Xilinx ships first 28nm Kintex-7 FPGAs] {{Webarchive|url=https://web.archive.org/web/20120413031515/http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4214345/Xilinx-ships-first-28nm-Kintex-7-FPGAs |date=2012-04-13 }}." March 21, 2011. Retrieved May 11, 2012.</ref> In March 2011, Xilinx introduced the Zynq-7000 family, which integrates a complete [[ARM Cortex-A9]] MPCore processor-based system on a 28&nbsp;nm FPGA for system architects and embedded software developers.<ref name="EETimesMarch1"/><ref name="EmbeddedWorldMarch1"/> In May 2017, Xilinx expanded the 7 Series with the production of the Spartan-7 family.<ref name="spartan7announce">Company Release. "[https://www.xilinx.com/news/press/2015/xilinx-announces-the-spartan-7-fpga-family.html Xilinx Announces the Spartan-7 FPGA Family] {{Webarchive|url=https://web.archive.org/web/20180507085509/https://www.xilinx.com/news/press/2015/xilinx-announces-the-spartan-7-fpga-family.html |date=2018-05-07 }}." November 19, 2015.</ref><ref name="spartan7prod">Company Release. "[https://www.xilinx.com/news/press/2017/xilinx-spartan-7-fpgas-now-in-production.html Xilinx Spartan-7 FPGAs Now in Production] {{Webarchive|url=https://web.archive.org/web/20180507085446/https://www.xilinx.com/news/press/2017/xilinx-spartan-7-fpgas-now-in-production.html |date=2018-05-07 }}." May 09, 2017.</ref>

In Dec, 2013, Xilinx introduced the UltraScale series: Virtex UltraScale and Kintex UltraScale families. These new FPGA families are manufactured by [[TSMC]] in its 20&nbsp;nm planar process.<ref name=TSMC>{{cite web |url=https://www.xilinx.com/publications/prod_mktg/Xilinx-UltraScale-Backgrounder.pdf |title=Archived copy |access-date=2014-05-13 |url-status=dead |archive-url=https://web.archive.org/web/20140707070659/http://www.xilinx.com/publications/prod_mktg/Xilinx-UltraScale-Backgrounder.pdf |archive-date=2014-07-07 }}</ref> At the same time it announced an UltraScale SoC architecture, called Zynq UltraScale+ [[MPSoC]], in TSMC 16&nbsp;nm FinFET process.<ref name="TSMC_16">{{cite web|url=https://www.xilinx.com/products/technology/ultrascale-mpsoc/index.htm|title=UltraScale MPSoC Architecture|access-date=August 16, 2015|archive-date=October 12, 2014|archive-url=https://web.archive.org/web/20141012035155/http://www.xilinx.com/products/technology/ultrascale-mpsoc/index.htm|url-status=live}}</ref>

In March 2021, Xilinx announced a new cost-optimized portfolio with Artix and Zynq UltraScale+ devices, fabricated on TSMC's 16&nbsp;nm process.<ref>{{Cite web|date=2021-03-16|title=Xilinx Back in the Cost-Optimized Game|url=https://www.eejournal.com/article/xilinx-back-in-the-cost-optimized-game/|access-date=2021-04-02|website=EEJournal|language=en-US}}</ref>

===Virtex family===
{{main|Virtex (FPGA)}}
The [[Virtex (FPGA)|Virtex]] series of FPGAs have integrated features that include [[FIFO (computing and electronics)|FIFO]] and ECC logic, DSP blocks, [[PCI-Express]] controllers, [[Ethernet]] [[MAC address|MAC]] blocks, and high-speed transceivers. In addition to FPGA logic, the Virtex series includes embedded fixed function hardware for commonly used functions such as multipliers, memories, serial transceivers and microprocessor cores.<ref name="Virtex1">Ron Wilson, EDN. "[http://www.edn.com/article/459148-Xilinx_FPGA_introductions_hint_at_new_realities.php Xilinx FPGA introductions hint at new realities] {{webarchive|url=https://web.archive.org/web/20110525031230/http://www.edn.com/article/459148-Xilinx_FPGA_introductions_hint_at_new_realities.php |date=May 25, 2011 }}." February 2, 2009 Retrieved June 10, 2010.</ref> These capabilities are used in applications such as wired and wireless infrastructure equipment, advanced medical equipment, test and measurement, and defense systems.<ref name="Virtex2">Design & Reuse. "[http://www.design-reuse.com/news/19988/xilinx-virtex-6-fpga.html New Xilinx Virtex-6 FPGA Family Designed to Satisfy Insatiable Demand for Higher Bandwidth and Lower Power Systems] {{Webarchive|url=https://web.archive.org/web/20100103040550/http://www.design-reuse.com/news/19988/xilinx-virtex-6-fpga.html |date=2010-01-03 }}." February 2, 2009. Retrieved June 10, 2010.</ref>

The Virtex 7 family, is based on a 28&nbsp;nm design and is reported to deliver a two-fold system performance improvement at 50 percent lower power compared to previous generation Virtex-6 devices. In addition, Virtex-7 doubles the memory bandwidth compared to previous generation Virtex FPGAs with 1866&nbsp;Mbit/s memory interfacing performance and over two million logic cells.<ref name="EET" /><ref name="Morris" />

In 2011, Xilinx began shipping sample quantities of the Virtex-7 2000T "3D FPGA", which combines four smaller FPGAs into a single package by placing them on a special silicon interconnection pad (called an [[interposer]]) to deliver 6.8 billion transistors in a single large chip. The interposer provides 10,000 data pathways between the individual FPGAs — roughly 10 to 100 times more than would usually be available on a board – to create a single FPGA.<ref name="don1025" /><ref name="clive1025" /><ref name="david1025" /> In 2012, using the same 3D technology, Xilinx introduced initial shipments of their Virtex-7 H580T FPGA, a heterogeneous device, so called because it comprises two FPGA dies and one 8-channel 28&nbsp;Gbit/s transceiver die in the same package.<ref name="ElectronicProductNews15May2012"/>

The Virtex-6 family is built on a 40&nbsp;nm process for compute-intensive electronic systems, and the company claims it consumes 15 percent less power and has 15 percent improved performance over competing 40&nbsp;nm FPGAs.<ref>Company Release. "[http://press.xilinx.com/phoenix.zhtml?c=212763&p=irol-newsArticle&ID=1250609 New Xilinx Virtex-6 FPGA Family Designed to Satisfy Insatiable Demand for Higher Bandwidth and Lower Power Systems]{{Dead link|date=July 2025 |bot=InternetArchiveBot |fix-attempted=yes }}." February 2, 2009. Retrieved February 2, 2009.</ref>

The Virtex-5 LX and the LXT are intended for logic-intensive applications, and the Virtex-5 SXT is for DSP applications.<ref>DSP DesignLine. "[http://www.industrialcontroldesignline.com/products/208404026' Analysis: Xilinx debuts Virtex-5 FXT, expands SXT] {{Webarchive|url=https://web.archive.org/web/20201011022346/https://www.informatech.com/ |date=2020-10-11 }}." June 13, 2008. Retrieved January 20, 2008.</ref> With the Virtex-5, Xilinx changed the logic fabric from four-input LUTs to six-input LUTs. With the increasing complexity of combinational logic functions required by SoC designs, the percentage of combinational paths requiring multiple four-input LUTs had become a performance and routing bottleneck. The six-input LUT represented a tradeoff between better handling of increasingly complex combinational functions, at the expense of a reduction in the absolute number of LUTs per device. The Virtex-5 series is a 65&nbsp;nm design [[Semiconductor device fabrication|fabricated]] in 1.0V, triple-oxide process technology.<ref name="Virtex3">National Instruments. "[http://zone.ni.com/devzone/cda/tut/p/id/7440#toc1 Advantages of the Xilinx Virtex-5 FPGA] {{Webarchive|url=https://web.archive.org/web/20100726040646/http://zone.ni.com/devzone/cda/tut/p/id/7440#toc1 |date=2010-07-26 }}." June 17, 2009. Retrieved June 29, 2010.</ref>

Legacy Virtex devices (Virtex, Virtex-II, Virtex-II Pro, Virtex 4) are still available, but are not recommended for use in new designs.

===Kintex===
[[File:Xilinx_Kintex7_XCKU025_on_matrox_grabber.jpg|thumb|A Xilinx Kintex UltraScale FPGA (XCKU025-FFVA1156) on a [[Matrox]] [[frame grabber]]]]
The Kintex-7 family is the first Xilinx mid-range FPGA family that the company claims delivers Virtex-6 family performance at less than half the price while consuming 50 percent less power. The Kintex family includes high-performance 12.5&nbsp;Gbit/s or lower-cost optimized 6.5&nbsp;Gbit/s serial connectivity, memory, and logic performance required for applications such as high volume [[10G]] optical wired communication equipment, and provides a balance of signal processing performance, power consumption and cost to support the deployment of [[Long Term Evolution]] (LTE) wireless networks.<ref name="EET" /><ref name="Morris" />

In August 2018, SK Telecom deployed Xilinx Kintex UltraScale FPGAs as their artificial intelligence accelerators at their data centers in South Korea.<ref name="kintex">{{cite web |url=https://medium.com/@fudo.abazovic/sk-telecom-deploys-xilinx-fpgas-for-ai-d5abea8916b4 |title=SK Telecom deploys Xilinx FPGAs for AI |date=19 August 2018 |access-date=2020-03-02 |archive-date=2020-03-02 |archive-url=https://web.archive.org/web/20200302215729/https://medium.com/@fudo.abazovic/sk-telecom-deploys-xilinx-fpgas-for-ai-d5abea8916b4 |url-status=live }}</ref> The FPGAs run SKT's automatic speech-recognition application to accelerate Nugu, SKT's voice-activated assistant.<ref name="kintex" /><ref>{{cite news |url=https://www.datacenterdynamics.com/news/sk-telecom-deploys-xilinx-fpgas-in-its-data-center/ |title=SSK Telecom deploys Xilinx FPGAs in its data center |access-date=2020-03-02 |archive-date=2020-10-11 |archive-url=https://web.archive.org/web/20201011022347/https://www.datacenterdynamics.com/en/news/sk-telecom-deploys-xilinx-fpgas-in-its-data-center/ |url-status=live }}</ref>

In July, 2020 Xilinx made the latest addition to their Kintex family, 'KU19P FPGA' which delivers more logic fabric and embedded memory<ref>{{Cite web |url=https://www.ept.ca/products/fpga-boosts-logic-fabric-embedded-memory/ |title=FPGA boosts logic fabric, embedded memory - Electronic Products & TechnologyElectronic Products & Technology |date=July 2020 |access-date=2020-08-05 |archive-date=2020-08-04 |archive-url=https://web.archive.org/web/20200804212616/https://www.ept.ca/products/fpga-boosts-logic-fabric-embedded-memory/ |url-status=live }}</ref>

===Artix===
[[File:Xilinx XC7A35T.jpg|thumb|A Artix-7 FPGA (XC7A35T-CSG325)]]
The Artix-7 family delivers 50 percent lower power and 35 percent lower cost compared to the Spartan-6 family and is based on the unified Virtex-series architecture. The Artix family is designed to address the small form factor and low-power performance requirements of battery-powered portable [[ultrasound]] equipment, commercial digital camera lens control, and military [[avionics]] and communications equipment.<ref name="EET" /><ref name="Morris" /> With the introduction of the Spartan-7 family in 2017, which lack high-bandwidth transceivers, the Artix-7's was clarified as being the "transceiver optimized" member.<ref name="costOptimizedPortfolio2017">Company Website. "[https://www.xilinx.com/products/silicon-devices/cost-optimized-portfolio.html Cost-Optimized Portfolio] {{Webarchive|url=https://web.archive.org/web/20170705133028/https://www.xilinx.com/products/silicon-devices/cost-optimized-portfolio.html |date=2017-07-05 }}." Retrieved July 5, 2017.</ref>

===Zynq===
[[File:Adapteva_Parallella_DK02_-_Zynq_(15455173526).png|thumb|A Zynq-7000 (XC7Z010-CLG400) on a [[Adapteva]] Parallella [[single-board computer]]]]
The Zynq-7000 family of [[System on a chip|SoCs]] addresses high-end embedded-system applications, such as video surveillance, automotive-driver assistance, next-generation wireless, and factory automation.<ref name="EETimesMarch1"/><ref name="EmbeddedWorldMarch1"/><ref name="EDNMarch1">Mike Demler, EDN. "[http://www.edn.com/article/517141-Xilinx_integrates_dual_ARM_Cortex_A9_MPCore_with_28_nm_low_power_programmable_logic.php Xilinx integrates dual ARM Cortex-A9 MPCore with 28-nm, low-power programmable logic] {{webarchive|url=https://archive.today/20130122011606/http://www.edn.com/article/517141-Xilinx_integrates_dual_ARM_Cortex_A9_MPCore_with_28_nm_low_power_programmable_logic.php |date=2013-01-22 }}." March 1, 2011. Retrieved March 1, 2011.</ref> Zynq-7000 integrate a complete [[ARM Cortex-A9]] MPCore-processor-based 28&nbsp;nm system. The Zynq architecture differs from previous marriages of programmable logic and embedded processors by moving from an FPGA-centric platform to a processor-centric model.<ref name="EETimesMarch1"/><ref name="EmbeddedWorldMarch1"/><ref name="EDNMarch1"/> For software developers, Zynq-7000 appear the same as a standard, fully featured [[ARM architecture family|ARM]] processor-based [[System on a chip|system-on-chip (SoC)]], booting immediately at power-up and capable of running a variety of operating systems independently of the programmable logic.<ref name="EETimesMarch1"/><ref name="EmbeddedWorldMarch1"/><ref name="EDNMarch1"/> In 2013, Xilinx introduced the Zynq-7100, which integrates [[digital signal processing]] (DSP) to meet emerging programmable systems integration requirements of wireless, broadcast, medical and military applications.<ref>Clive Maxfield, EETimes. "[http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4410302/Xilinx-unveils-new-Zynq-7100-All-Programmable-SoCs Xilinx unveils new Zynq-7100 All Programmable SoCs] {{Webarchive|url=https://web.archive.org/web/20130326190106/http://www.eetimes.com/electronics-products/electronic-product-reviews/fpga-pld-products/4410302/Xilinx-unveils-new-Zynq-7100-All-Programmable-SoCs |date=2013-03-26 }}." Mar 20, 2013. Retrieved Jun 3, 2013.</ref>

The new Zynq-7000 product family posed a key challenge for system designers, because Xilinx ISE design software had not been developed to handle the capacity and complexity of designing with an FPGA with an ARM core.<ref name="EETimes25Apr2012"/><ref name="EDN15Jun2012"/> Xilinx's new [[Xilinx Vivado|Vivado Design Suite]] addressed this issue, because the software was developed for higher capacity FPGAs, and it included [[high level synthesis]] (HLS) functionality that allows engineers to compile the co-processors from a [[C (programming language)|C]]-based description.<ref name="EETimes25Apr2012"/><ref name=EDN15Jun2012/>

The [[AXIOM (camera)|AXIOM]],<ref>{{cite web |url=https://www.apertus.org/alpha_prototype |title=Axiom Alpha |access-date=2014-06-20 |archive-date=2014-07-02 |archive-url=https://web.archive.org/web/20140702114027/https://www.apertus.org/alpha_prototype |url-status=live }}</ref> the world's first [[digital cinema camera]] that is [[open source hardware]], contains a Zynq-7000.<ref>{{cite web |url=https://forums.xilinx.com/t5/Xcell-Daily-Blog/Zynq-based-Axiom-Alpha-open-4K-cine-camera-proto-debuts-in/ba-p/430066 |title=Zynq-based Axiom Alpha open 4K cine camera proto debuts in Vienna hackerspace |date=2014-03-20 |access-date=2014-06-20 |archive-date=2014-08-13 |archive-url=https://web.archive.org/web/20140813105309/http://forums.xilinx.com/t5/Xcell-Daily-Blog/Zynq-based-Axiom-Alpha-open-4K-cine-camera-proto-debuts-in/ba-p/430066 |url-status=live }}</ref>

===Spartan family===
[[File:Fritz!Box Fon WLAN 7270 - Xilinx 3S250E-3338.jpg|thumb|Xilinx 3S250, Spartan-3E FPGA family]]
The Spartan series targets low cost, high-volume applications with a low-power footprint e.g. [[displays]], [[set-top boxes]], [[wireless router]]s and other applications.<ref name="spartan">Daniel Harris, Electronic Design. "[http://electronicdesign.com/Articles/Index.cfm?AD=1&ArticleID=18342 If only the original spartans could have thrived on so little power] {{webarchive|url=https://web.archive.org/web/20090302010210/http://electronicdesign.com/Articles/Index.cfm?AD=1&ArticleID=18342 |date=2009-03-02 }}." February 27, 2008. Retrieved January 20, 2008.</ref>

The Spartan-6 family is built on a 45&nbsp;nm, 9-metal layer, dual-oxide process technology.<ref name="eetimes"/><ref name="spartanrelease">Company Release. "[http://news.prnewswire.com/ViewContent.aspx?ACCT=109&STORY=/www/story/02-02-2009/0004964201&EDATE The low-cost Spartan-6 FPGA family delivers an optimal balance of low risk, low cost, low power, and high performance] {{dead link|date=October 2017|bot=medic}}{{cbignore|bot=medic}}." February 2, 2009.</ref> The Spartan-6 was marketed in 2009 as a low-cost option for automotive, wireless communications, flat-panel display and video surveillance applications.<ref name="spartanrelease"/>

The Spartan-7 family, built on the same 28[[nanometer|nm]] process used in the other 7-Series FPGAs, was announced in 2015,<ref name="spartan7announce"/> and became available in 2017.<ref name="spartan7prod"/> Unlike the Artix-7 family and the "LXT" members of the Spartan-6 family, the Spartan-7 FPGAs lack high-bandwidth transceivers.<ref name="costOptimizedPortfolio2017"/>

===EasyPath===
Because EasyPath devices are identical to the FPGAs that customers are already using the parts can be produced faster and more reliably from the time they are ordered compared to similar competing programs.<ref name="thirtyone">{{cite web |last1=Morris |first1=Kevin |title=Not Bad Die: Xilinx EasyPath Explained |url=https://www.fpgajournal.com/articles_2008/pdf/20080527_easypath.pdf |website=FPGA Journal |access-date=20 January 2008 |archive-url=https://web.archive.org/web/20090327150947/http://www.fpgajournal.com/articles_2008/pdf/20080527_easypath.pdf |archive-date=27 March 2009 |url-status=dead}}</ref>

===Versal===
Versal is Xilinx's 7&nbsp;nm architecture that targets [[heterogeneous computing]] needs in datacenter acceleration applications, in [[artificial intelligence]] acceleration at the [[edge computing|edge]], [[Internet of things]] (IoT) applications and [[embedded computing]].

The Everest program focuses on the Versal Adaptive Compute Acceleration Platform (ACAP), a product category combining a traditional FPGA fabric with an [[ARM architecture|ARM]] [[system on chip]] and a set of [[coprocessor]]s, connected through a [[network on a chip]].<ref name="VB20190618">"[https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/ Xilinx ships first Versal ACAP chips that adapt to AI programs] {{Webarchive|url=https://web.archive.org/web/20200521204130/https://venturebeat.com/2019/06/18/xilinx-ships-first-versal-acap-chips-that-adapt-to-ai-programs/ |date=2020-05-21 }}." June 18, 2019. Retrieved Feb  26, 2020.</ref> Xilinx's goal was to reduce the barriers to adoption of FPGAs for accelerated compute-intensive datacenter workloads.<ref name="FBS26Mar2018">Karl Freund, [[Forbes (magazine)]]. "[https://www.forbes.com/sites/moorinsights/2018/03/26/xilinx-everest-enabling-fpga-acceleration-with-acap/#5b2a9b6b342e Xilinx Everest: Enabling FPGA Acceleration With ACAP] {{Webarchive|url=https://web.archive.org/web/20180612144257/https://www.forbes.com/sites/moorinsights/2018/03/26/xilinx-everest-enabling-fpga-acceleration-with-acap/#5b2a9b6b342e |date=2018-06-12 }}." March 26, 2018. Retrieved April 26, 2018.</ref> They are designed for a wide range of applications in the fields of [[big data]] and [[machine learning]], including video transcoding, database querying, data compression, search, [[inference#Inference engines|AI inferencing]], [[machine vision]], [[computer vision]], [[vehicular automation|autonomous vehicles]], [[genomics]], computational storage and network acceleration.<ref name="VB20190618"/>

On April 15, 2020, it was announced that Xilinx would supply its Versal chips to [[Samsung Electronics]] for 5G networking equipment.<ref>"[https://www.platformexecutive.com/news/mobile-telecoms-infrastructure/samsung-to-tap-xilinx-chips-for-5g-network-equipment/ Samsung to tap Xilinx chips for 5G network equipment] {{Webarchive|url=https://web.archive.org/web/20201011022347/https://www.platformexecutive.com/news/mobile-telecoms-infrastructure/samsung-to-tap-xilinx-chips-for-5g-network-equipment/ |date=2020-10-11 }}." Apr 16, 2020. Retrieved April 16, 2020.</ref> In July 2021, Xilinx debuted the Versal HBM, which combines the network interface of the platform with [[High Bandwidth Memory|HBM2e]] memory to alleviate data bottlenecking.<ref>{{cite web |last1=McGregor |first1=Jim |title=Xilinx Ups The Ante In High-Performance Processing With Versal HBM |url=https://www.forbes.com/sites/tiriasresearch/2021/07/15/xilinx-ups-the-ante-in-high-performance-processing-with-versal-hbm/?sh=4d3955f455e1 |website=Forbes |access-date=28 September 2021 |language=en}}</ref>

==See also==
{{Portal|Companies|San Francisco Bay Area}}
* [[AI accelerator]]
* [[Altera]]
* [[High speed serial link]]

==References==
{{Reflist}}

==External links==
{{commons category}}
* {{official website|1=https://www.xilinx.com/|2=Xilinx official website}}
{{Finance links historical
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[[Category:Defunct computer companies of the United States]]
[[Category:Defunct computer hardware companies]]
[[Category:Defunct manufacturing companies based in the San Francisco Bay Area]]
[[Category:Defunct semiconductor companies of the United States]]
[[Category:Electronics companies disestablished in 2023]]
[[Category:Electronics companies established in 1984]]
[[Category:Fabless semiconductor companies]]
[[Category:Manufacturing companies based in San Jose, California]]
[[Category:Server hardware]]
[[Category:Technology companies based in the San Francisco Bay Area]]