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"Pure" CPUs: RM Empty Section

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'''[[Athlon]]''' is a family of CPUs designed by [[AMD]], targeted mostly at the desktop market. The name "Athlon" has been largely unused as just "Athlon" since 2001 when AMD started naming its processors [[Athlon XP]], but in 2008 began referring to single core 64-bit processors from the [[Athlon X2|AMD Athlon X2]] and [[AMD Phenom]] product lines. Later the name began being used for some [[AMD Accelerated Processing Unit|APUs]].

==Features overview==
===APUs===
[[Template:AMD APU features|APU features table]]

==Desktop processors==
===Athlon (Model 1, K7 "Argon", 250 [[Nanometre|nm]])===
* L2 cache always runs with 50% of CPU speed
* All models support: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]]''
{| class="wikitable"
!Model number || Frequency || L2 cache || [[front-side bus|FSB]] [[#fn_1|1]] || Multiplier || Voltage || [[Thermal Design Power|TDP]] || Socket || Release date || Order part number || Release price ([[United States dollar|USD]])
|-
|Athlon 500 || 500 MHz || rowspan="5" | 512 KB || rowspan="5" | 200 MT/s || 5x || rowspan="5" | 1.60 V || 42 [[Watt|W]] || rowspan="5" | [[Slot A]] || rowspan="3" | June 23, 1999 || AMD-K7500MTR51B C || $324
|-
|Athlon 550 || 550 MHz || 5.5x || 46 W || AMD-K7550MTR51B C || $479
|-
|Athlon 600 || 600 MHz || 6x || 50 W || AMD-K7600MTR51B C || $699
|-
|Athlon 650 || 650 MHz || 6.5x || 54 W || August 9, 1999 || AMD-K7650MTR51B C || rowspan="2" | $849
|-
|Athlon 700 || 700 MHz || 7x || 50 W || October 4, 1999 || AMD-K7700MTR51B C
|}

===Athlon (Model 2, K75 "Pluto/Orion", 180 nm)===
* L2 cache runs with 50% (up to 700 MHz), 40% (up to 850 MHz) or 33% (up to 1000 MHz) of CPU speed.
* 900 - 1000 MHz have Orion designation.
* All models support: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]]''
{| class="wikitable"
!Model number || Frequency || L2 cache || [[front-side bus|FSB]] [[#fn_1|1]] || Multiplier || Voltage || [[Thermal Design Power|TDP]] || Socket || Release date || Order part number || Release price ([[United States dollar|USD]])
|-
|Athlon 550 || 550 MHz || rowspan="10" | 512 KB || rowspan="10" | 200 MT/s || 5.5x || rowspan="5" | 1.60 V || 31 [[Watt|W]] || rowspan="10" | [[Slot A]] || rowspan="5" | November 29, 1999 || AMD-K7550MTR51B A ||
|-
|Athlon 600 || 600 MHz || 6x || 34 W || AMD-K7600MTR51B A ||
|-
|Athlon 650 || 650 MHz || 6.5x || 36 W || AMD-K7650MTR51B A ||
|-
|Athlon 700 || 700 MHz || 7x || 39 W || AMD-K7700MTR51B A ||
|-
|Athlon 750 || 750 MHz || 7.5x || 40 W || AMD-K7750MTR52B A || $799
|-
|Athlon 800 || 800 MHz || 8x || rowspan="2" | 1.70 V || 48 W || January 6, 2000 || AMD-K7800MPR52B A ||
|-
|Athlon 850 || 850 MHz || 8.5x || 50 W || February 11, 2000 || AMD-K7850MPR52B A || $849
|-
|Athlon 900 || 900 MHz || 9x || rowspan="3" | 1.80 V || 60 W || rowspan="3" | March 6, 2000 || AMD-K7900MNR53B A || $899
|-
|Athlon 950 || 950 MHz || 9.5x || 62 W || AMD-K7950MNR53B A || $999
|-
|Athlon 1000 || 1000 MHz || 10x || 65 W || AMD-K7100MNR53B A || $1,299
|}

===Athlon (Model 4, "Thunderbird", 180 nm)===
* L2 cache always runs with full CPU speed
* All models support: ''[[MMX (instruction set)|MMX]], [[3DNow!|Enhanced 3DNow!]]''
{| class="wikitable"
!Model number || Frequency || L2 cache || [[front-side bus|FSB]] [[#fn_1|1]] || Multiplier || Voltage || [[Thermal Design Power|TDP]] || Socket || Release date || Order part number || Release price ([[United States dollar|USD]])
|-
|Athlon 600 || 600 MHz || rowspan="27" | 256 KB || rowspan="17" | 200 MT/s || 6x || rowspan="2" | 1.75 V || 38 W<ref>{{cite web |url=http://cpu-data.info/index.php?grp=A0600AMT3B&gr=-1&lng=1 |title = List of microprocessors}}</ref> || [[Socket A]] || rowspan="17" | June 5, 2000 || A0600AMT3B ||
|-
| rowspan="2" |Athlon 650 || rowspan="2" | 650 MHz || rowspan="2" | 6.5x || 38 [[Watt|W]] || Socket A || A0650AMT3B A0650APT3B ||
|-
|1.70 V
|36.1 W
|[[Slot A]]
|AMD-A0650MPR24B A
|OEM
|-
| rowspan="2" |Athlon 700 || rowspan="2" | 700 MHz || rowspan="2" | 7x || 1.75 V || 40 W || Socket A || A0700AMT3B A0700APT3B ||
|-
|1.70 V
|38.3 W
|Slot A
|AMD-A0700MPR24B A
|OEM
|-
| rowspan="2" |Athlon 750 || rowspan="2" | 750 MHz || rowspan="2" | 7.5x || 1.75 V || 43 W || Socket A || A0750AMT3B
A0750APT3B
| $319
|-
|1.70 V
|40.4 W
|Slot A
|AMD-A0750MPR24B A
|OEM
|-
| rowspan="2" |Athlon 800 || rowspan="2" | 800 MHz || rowspan="2" | 8x || 1.75 V || 45 W || Socket A || A0800AMT3B A0800APT3B || $359
|-
|1.70 V
|42.6 W
|Slot A
|AMD-A0800MPR24B A
|OEM
|-
| rowspan="2" |Athlon 850 || rowspan="2" | 850 MHz || rowspan="2" | 8.5x || 1.75 V || 47 W || Socket A || A0850AMT3B A0850APT3B || $507
|-
|1.70 V
|44.8 W
|Slot A
|AMD-A0850MPR24B A
|OEM
|-
| rowspan="2" |Athlon 900 || rowspan="2" | 900 MHz || rowspan="2" | 9x || rowspan="6" | 1.75 V || rowspan="2" | 50 W || Socket A || A0900AMT3B A0900APT3B
A0900DMT3B
| $589
|-
|Slot A
|AMD-A0900MMR24B A
|OEM
|-
| rowspan="2" |Athlon 950 || rowspan="2" | 950 MHz || rowspan="2" | 9.5x || rowspan="2" | 52 W || Socket A || A0950AMT3B
A0950APT3B

A0950DMT3B
| $759
|-
|Slot A
|AMD-A0950MMR24B A
|OEM
|-
| rowspan="2" |Athlon 1000B || rowspan="3" | 1000 MHz || rowspan="2" | 10x || rowspan="3" | 54 W || Socket A || A1000AMS3B A1000AMT3B
A1000DMT3B
| $990
|-
|Slot A
|AMD-A1000MMR24B A
|OEM
|-
|Athlon 1000C || 266 MT/s || 7.5x || rowspan="10" | 1.75 V || rowspan="10" | Socket A || October 31, 2000 || A1000AMS3C A1000AMT3C
A1000DMT3C
| $385
|-
|Athlon 1100 || 1100 MHz || 200 MT/s || 11x || 55.1/60 W || August 14, 2000 || A1100AMS3B
A1100AMT3B
| $853
|-
|Athlon 1133 || 1133 MHz || 266 MT/s || 8.5x || 63 W || October 31, 2000 || A1133AMS3C || $506
|-
|Athlon 1200B || rowspan="2" | 1200 MHz || 200 MT/s || 12x || rowspan="3" | 66 W || October 17, 2000 || A1200AMS3B || $612
|-
|Athlon 1200C || rowspan="2" | 266 MT/s || 9x || October 31, 2000 || A1200AMS3C || $673
|-
|Athlon 1266 || 1266 MHz || 9.5x || March 21, 2001<ref>{{Cite web|title=AMD A1266AMS3C Information {{!}} cpu-galerie.de|url=http://cpu-galerie.com/html/amdk7athlonsockel-a1266ams3c.html|access-date=2021-10-12|website=cpu-galerie.com}}</ref>|| A1266AMS3C ||
|-
|Athlon 1300 || 1300 MHz || 200 MT/s || 13x || 68 W || rowspan="2" | March 21, 2001 || A1300AMS3B
A1300APS3B
| $318
|-
|Athlon 1333 || 1333 MHz || 266 MT/s || 10x || 70 W || A1333AMS3C || $350
|-
|Athlon 1400B || rowspan="2" | 1400 MHz || 200 MT/s || 14x || rowspan="2" | 72 W || rowspan="2" | June 6, 2001 || A1400AMS3B || $253
|-
|Athlon 1400C || 266 MT/s || 10.5x || A1400AMS3C || $253
|}

===Athlon XP===
{{Main|List of AMD Athlon XP processors}}

===Athlon 64===
{{Main|List of AMD Athlon 64 processors}}

===Athlon X2===
{{Main|List of AMD Athlon X2 processors}}

===Athlon II===
{{Main|List of AMD Athlon II processors}}

===Athlon (Piledriver)===
===="Trinity" (2012)====
* Platform "Virgo"
* [[32 nm process|32 nm fabrication]] on GlobalFoundries SOI process
* Socket [[Socket FM2|FM2]]
* CPU: [[Piledriver (microarchitecture)|Piledriver]]
** L1 Cache: 16 KB Data per core and 64 KB Instructions per module
* Die Size: {{val|246|u=mm2}}, 1.303 Billion transistors<ref>{{cite web |url=http://www.pcper.com/news/Processors/Trinity-Improvements-Include-Updated-Piledriver-Cores-and-VLIW4-GPUs-0 |title=Trinity Improvements Include Updated Piledriver Cores and VLIW4 GPUs |date=4 May 2012 |access-date=2013-11-10}}</ref>
* Support for up to four DIMMs of up to DDR3-1866 memory
* 5 GT/s UMI
* Integrated [[PCIE#PCI Express 2.0|PCIe 2.0]] controller, and Turbo Core technology for faster CPU/GPU operation when the thermal specification permits
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4a]], [[SSE4.1]], [[SSE4.2]], [[AMD64]], [[AMD-V]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], [[F16C]],<ref name="auto">{{Cite web |url=https://www.extremetech.com/computing/129363-amd-detonates-trinity-behold-bulldozers-second-coming |title=AMD detonates Trinity: Behold Bulldozer's second coming - ExtremeTech |access-date=2017-10-07}}</ref> [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]]

{| class="wikitable sortable" style="text-align:center;"
|-
! rowspan="2" |Model number
! rowspan="2" |Released
! rowspan="2" |Fab
! rowspan="2" |Step.
! rowspan="2" | [Modules/[[Floating-point unit|FPUs]]]
[[Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! rowspan="2" | Clock
(GHz)
! rowspan="2" | Turbo
(GHz)
! colspan="2" | [[Cache memory|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="2" |DDR3
Mem.
! rowspan="2" |TDP
(W)
! rowspan="2" |Box Number
! rowspan="2" |Part number<ref>{{cite web |url=http://www.shopblt.com/cgi-bin/s.cgi?s_max=100&order_id=239797834&s_mfg=AMD |title=Product Search Results—Bottom Line Telecommunications |publisher=Bottom Line Telecommunications Corporation |access-date=2013-11-10}}</ref>
|-
! [[L1 cache|L1]]
! [[L2 cache|L2]]
(MB)
|-
! {{rh}} class="table-rh" | Athlon X2 340<ref name="AX2_340">{{cite web|url=http://ru.gecid.com/cpu/amd_athlon_x2_340/?s=all|title=Обзор и тестирование процессора AMD Athlon X2 340|access-date=2016-09-12|author=Альберт Шаповалов|website=Ru.gecid.com/|date=10 September 2014|language=ru}}</ref>
| 2012/10
| rowspan="4" |32 nm
| rowspan="4" |TN-A1
|[1]2
| 3.2
| 3.6
| rowspan="4" |64KB inst. per module 16KB data per core
|1
|1600
|65
|
| AD340XOKA23HJ
|-
! {{rh}} class="table-rh" | Athlon X4 730
| 2012
10/1
| rowspan="3" | [2]4
| 2.8
| 3.2
| rowspan="3" |2× 2MB
| rowspan="3" |1866
| rowspan="2" |65
|
|AD730XOKA44HJ
|-
! {{rh}} class="table-rh" |[http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/740/80 Athlon X4 740]
| rowspan=2 | 2012/10
| 3.2
| 3.7
| AD740XOKHJBOX
| AD740XOKA44HJ
|-
! {{rh}} | [http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/750K/81 Athlon X4 750K]
| 3.4
| 4.0
| 100
| AD750KWOHJBOX
| AD750KWOA44HJ
|}
{{notelist|refs=
}}

==="Richland" (2013)===
* [[32 nm process|32 nm fabrication]] on GlobalFoundries SOI process
* Socket [[Socket FM2|FM2]]
* Two or four CPU cores based on the [[Piledriver (microarchitecture)|Piledriver]] microarchitecture
** Die Size: {{val|246|u=mm2}}, 1.303 Billion transistors<ref>{{cite web |author1=Hassan Mujtaba |title=AMD A10-6800K and A10-6700 "Richland" APU Review |url=https://wccftech.com/review/amd-a10-6800k-a10-6700-richland-apu-review/ |website=Wccftech |access-date=20 March 2020}}</ref>
** L1 Cache: 16 KB Data per core and 64 KB Instructions per module
** MMX, SSE, [[SSE2]], [[SSE3]], SSSE3, [[SSE4a]], SSE4.1, SSE4.2, [[AMD64]], [[AMD-V]], [[AES instruction set|AES]], [[Advanced Vector Extensions|AVX]], AVX1.1, [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], Turbo Core 3.0, [[NX bit]], [[PowerNow!]]

{| class="wikitable sortable" style="text-align:center;"
|-
! rowspan="3" |Model
! rowspan="3" |Released
! rowspan="3" |Fab
! rowspan="3" |Step.
! rowspan="3" |[Modules/[[Floating-point unit|FPUs]]]
[[Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" |Freq. (GHz)
! colspan="2" rowspan="2" |[[Cache memory|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan="3" |DDR3
Mem.
! rowspan="3" |TDP
(W)
! rowspan="3" |Box Number
! rowspan="3" |Part number
|-
! rowspan="2" | Base
! rowspan="2" | Turbo
|-
! [[L1 cache|L1]]
! [[L2 cache|L2]]
(MB)
|-
! {{rh}} class="table-rh" | Athlon X2 350<ref name="amdcpulist">{{cite web |url=https://www.amd.com/en-us/products/processors/desktop/athlon-cpu |title=AMD Athlon Processors |access-date=2015-03-02}}</ref>
|
| rowspan="4" |32 nm
| rowspan="4" |RL-A1
| rowspan="2" |[1]2
| 3.5
| 3.9
| rowspan="4" |64KB inst. per module 16KB data per core
| rowspan="2" |1
| rowspan="4" | 1866
| rowspan="2" | 65
|
| AD350XOKA23HL
|-
! {{rh}} class="table-rh" | Athlon X2 370K
| Jun 2013
| 4.0
| 4.2
| AD370KOKHLBOX
| AD370KOKA23HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/750/143 Athlon X4 750]
| Oct 2013
| rowspan="2" | [2]4
| 3.4
| 4.0
| rowspan="2" | 2× 2MB
| 65
|
| AD750XOKA44HL
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/CPU/AMD-Athlon%E2%84%A2/AMD-Athlon%E2%84%A2-X4/760K/83 Athlon X4 760K]
| Jun 2013
| 3.8
| 4.1
| 100
| AD760KWOHLBOX
| AD760KWOA44HL
|}
{{notelist|refs=
}}

===Athlon (Jaguar)===
==== "Kabini" (2013, [[System on a chip|SoC]]) ====
* [[28 nm process|28 nm fabrication]] by [[GlobalFoundries]]
* [[Socket AM1]], aka Socket FS1b (AM1 platform)
* 2 to 4 CPU Cores ([[Jaguar (microarchitecture)]])
* L1 Cache: 32 KB Data per core and 32 KB Instructions per core
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4a]], [[SSE4.1]], [[SSE4.2]], [[AMD64]], [[Advanced Vector Extensions|AVX]], [[F16C]], [[CLMUL instruction set|CLMUL]], [[AES instruction set|AES]], MOVBE (Move Big-Endian instruction), XSAVE/XSAVEOPT, [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[AMD-V]] support
* SoC with integrated memory, PCIe, 2× USB 3.0, 6× USB 2.0, Gigabit Ethernet, and 2× SATA III (6 [[Gigabit|Gb]]/s) controllers
* GPU based on [[Graphics Core Next]] (GCN)

{| class="wikitable sortable" style="text-align:center;"
! rowspan=3 | Model
! rowspan=3 | Released
! rowspan=3 | Fab
! rowspan=3 | Step.
! colspan=5 | CPU
! colspan=4 | GPU
! rowspan=3 | DDR3
Memory support
! rowspan=3 | TDP
(W)
! rowspan=3 | Box Number
! rowspan=3 | Part number
|-
! rowspan=2 | [[Multi-core processor|Cores]] [[thread (computing)|(threads)]]
! rowspan=2 | Clock
(GHz)
! colspan=3 | [[Cache memory|Cache]]{{efn|name="kib"|AMD in its technical documentation uses KB, which it defines as Kilobyte and as equal to 1024 bytes, and MB, which it defines as Megabyte and as equal to 1024 KB.<ref name="AMD_54945" />}}
! rowspan=2 | Model
! rowspan=2 | Config
! rowspan=2 | Clock
(MHz)
! rowspan=2 | Processing power ([[GFLOPS]]){{efn|name="SFLOPS"}}
|-
! [[L1 cache|L1]]
! [[L2 cache|L2]]
(MB)
! [[L3 cache|L3]]
|-
! {{rh}} | [https://www.cpu-world.com/CPUs/Jaguar/AMD-Athlon%20X4%20530%20-%20AD530XJAH44HM.html Athlon X4 530]
| rowspan=2 | ?
| rowspan="5" | 28 nm
| rowspan="5" | A1
| rowspan=2 |4 (4)
| 2
| rowspan="5" | 32 KB inst. 32 KB data per core
| rowspan=2 | 2
| rowspan=7 {{n/a}}
| rowspan=2 colspan=4 {{n/a}}
| rowspan=2 | ?
| rowspan="5" | 25
|
| AD530XJAH44HM
|-
! {{rh}} | [https://www.cpu-world.com/CPUs/Jaguar/AMD-Athlon%20X4%20550%20-%20AD550XJAH44HM.html Athlon X4 550]
| 2.2
|
| AD550XJAH44HM
|-
! {{rh}} class="table-rh" | [http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5150-APU-with-Radeon%E2%84%A2-R3-Series/76 Athlon 5150]
| rowspan="2" |April 9, 2014
| rowspan="3" |4 (4)
| 1.60
| rowspan="3" |2
| rowspan="3" | R3 (HD 8400)
| rowspan="3" |128:8:4 2 CU
| rowspan="3" | 600
| rowspan="3" | 153.6
| rowspan="3" |1600 (Single channel only)
| AD5150JAHMBOX
| AD5150JAH44HM
|-
! {{rh}} | [http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5350-APU-with-Radeon%E2%84%A2-R3-Series/77 Athlon 5350]
| 2.05
| AD5350JAHMBOX
| AD5350JAH44HM
|-
! {{rh}} | [http://products.amd.com/en-us/search/APU/AMD-Athlon%E2%84%A2-APUs/AMD-Athlon%E2%84%A2-Quad-Core-APU/Athlon%E2%84%A2-5370-APU-with-Radeon%E2%84%A2-R3-Series/182 Athlon 5370]
| Feb, 2016
| 2.20
|
| AD5370JAH44HM
|}
{{notelist|refs=
{{efn|name="SFLOPS"|[[Single-precision floating-point format|Single-precision]] performance is calculated from the base (or boost) core clock speed based on a [[Fused multiply–add|FMA]] operation.}}
}}

===Athlon (Steamroller, Excavator)===
===="Kaveri" (2014) & "Godavari" (2015)====
* [[28 nm process|28 nm fabrication]] by [[GlobalFoundries]].
* [[Socket FM2+]],<ref>{{cite web |url= http://www.xbitlabs.com/news/cpu/display/20130530232155_AMD_s_Next_Gen_Kaveri_APUs_Will_Require_New_Mainboards.html |title= AMD's Next-Gen "Kaveri" APUs Will Require New Mainboards |author=Anton Shilov |access-date=2014-12-17 |date=2013-05-30}}</ref> support for [[PCI Express#3.0|PCIe 3.0]].
* Two or four CPU cores based on the [[Steamroller (microarchitecture)|Steamroller]] microarchitecture.
**Kaveri refresh models have codename Godavari.<ref>{{Cite web|url=http://www.cpu-world.com/Cores/Godavari.html|title=AMD Godavari core|website=www.cpu-world.com|access-date=2018-09-16}}</ref>
* Die Size: {{val|245|u=mm2}}, 2.41 Billion transistors.<ref>{{cite web |author1=Joel Hruska |title=AMD Kaveri A10-7850K and A8-7600 review: Was it worth the wait for the first true heterogeneous chip? |url=https://www.extremetech.com/computing/174632-amd-kaveri-a10-7850k-and-a8-7600-review-was-it-worth-the-wait-for-the-first-true-heterogeneous-chip |website=ExtremeTech |access-date=20 March 2020}}</ref>
* L1 Cache: 16 KB Data per core and 96 KB Instructions per module.
* [[MMX (instruction set)|MMX]], [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[SSE4a]], [[AMD64]], [[AMD-V]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[Turbo Core]]
* Dual-channel (2× 64 Bit) [[DDR3 SDRAM|DDR3]] memory controller.

{| class="wikitable" style="text-align:center;"
! rowspan=3 | Model
! rowspan=3 | Released
! rowspan=3 | [[Stepping level|Stepping]]
! colspan=5 | CPU
! rowspan=3 | Memory support
! rowspan=3 | TDP
! rowspan=3 | Part number(s)
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan=2 | Clock (GHz)
! colspan="2" | [[Cache memory|Cache]]
|-
! Base
! Turbo
! [[L1 cache|L1]]
! [[L2 cache|L2]]
|-
! Athlon X2 450<ref name="amdcpulist" />
|Jul 31, 2014
| rowspan="3" | KV-A1
| [1] 2
| 3.5
| 3.9
| rowspan="7" | 96 KB inst. per module 16 KB data per core
| 1 MB
| DDR3-1866
| rowspan="4" | 65 W
| AD450XYBI23JA
|-
! [https://www.cpu-world.com/CPUs/Bulldozer/AMD-Athlon%20X4%20830%20-%20AD830XYBI44JA.html Athlon X4 830]
| Feb 2015
| rowspan="6" | [2] 4
| 3.0
| 3.4
| rowspan="6" | 2 MB per module
| rowspan="6" |DDR3-2133
| AD830XYBI44JA
|-
! Athlon X4 840<ref name="amdcpulist" />
|Aug 2014
|3.1
|3.8
|AD840XYBJABOX AD840XYBI44JA
|-
! [https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/850.html Athlon X4 850]
|Q2 2015
|GV-A1
|3.2
|
|AD835XACI43KA
|-
! [https://www.amd.com/en/product/1361 Athlon X4 860K]
|Aug 2014
|KV-A1
| 3.7
| 4.0
| rowspan="3" | 95 W
| AD860KXBJABOX AD860KWOHLBOX AD860KXBJASBX AD860KXBI44JA
|-
! [https://www.amd.com/en/product/1366 Athlon X4 870K]
| Dec 2015
| rowspan=2 | GV-A1
| 3.9
| 4.1
| AD870KXBJCSBX AD870KXBI44JC
|-
! [https://www.amd.com/en/product/1371 Athlon X4 880K]
| Mar 1, 2016
| 4.0
| 4.2
| AD880KXBJCSBX
|}

===="Carrizo" (2016)====
* [[28 nm process|28 nm fabrication]] by [[GlobalFoundries]]
* Socket [[Socket FM2+|FM2+]], [[Socket AM4|AM4]], support for [[PCI Express#3.0|PCIe 3.0]]
* Two or four CPU cores based on the [[Excavator (microarchitecture)|Excavator]] microarchitecture
* Die Size: {{val|250.04|u=mm2}}, 3.1 Billion transistors<ref>{{cite web |author1=Hassan Mujtaba |title=AMD Details Carrizo APUs Energy Efficient Design at Hot Chips 2015 – 28nm Bulk High Density Design With 3.1 Billion Transistors, 250mm2 Die |url=https://wccftech.com/amd-carrizo-apu-architecture-hot-chips/ |website=Wccftech |access-date=20 March 2020 |date=26 August 2015}}</ref>
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[SSE4a]], [[AMD64]], [[AMD-V]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[Advanced Vector Extensions 2|AVX2]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], [[Turbo Core]]
* Dual-channel DDR3 or [[DDR4 SDRAM|DDR4]] memory controller

{| class="wikitable" style="text-align:center"
! rowspan="3" | Model
! rowspan="3" | Released
! rowspan="3" | [[Stepping level|Stepping]]
! rowspan="3" | Socket
! colspan="5" | CPU
! rowspan="3" | Memory support
! rowspan="3" | TDP
! rowspan="3" | Part number
|-
! rowspan="2" |[Modules/[[Floating-point unit|FPUs]]]
[[Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan="2" |[[Clock rate|Clock (GHz)]]
! colspan="2" |[[Cache memory|Cache]]
|-
! Base
! Turbo
! [[L1 cache|L1]]
! [[L2 cache|L2]]
|-
! [https://www.cpu-upgrade.com/CPUs/AMD/Athlon_X4/835.html Athlon X4 835]
| ?
| rowspan="2" | CZ-A1
| rowspan="2" | FM2+
| rowspan="2" | [2] 4
| 3.1
| ?
| rowspan="2" | 96 KB inst. per module 32 KB data per core
| rowspan="2" | 1 MB per module
| rowspan="2" | DDR3-2133 dual-channel
| rowspan="2" | 65 W
| AD835XACI43KA
|-
! [https://www.amd.com/en/products/cpu/845-near-silent-thermal-solution Athlon X4 845]
|Feb 2, 2016
|3.5
|3.8
|AD845XYBJCSBX{{efn|name="box"|Boxed part with cooler if available.}} AD845XACKASBX{{efn|name="box"}} AD845XACI43KA
|}
{{notelist}}

===="Bristol Ridge" (2016)====
* [[28 nm process|28 nm fabrication]] by [[GlobalFoundries]]
* [[Socket AM4]], support for [[PCI Express#3.0|PCIe 3.0]]
* Two or four "[[Excavator (microarchitecture)|Excavator+]]" CPU cores
* L1 Cache: 32 KB Data per core and 96 KB Instructions per module
* MMX, [[Streaming SIMD Extensions|SSE]], [[SSE2]], [[SSE3]], [[SSSE3]], [[SSE4.1]], [[SSE4.2]], [[SSE4a]], [[AMD64]], [[AMD-V]], [[AES instruction set|AES]], [[CLMUL instruction set|CLMUL]], [[Advanced Vector Extensions|AVX]], [[Advanced Vector Extensions|AVX 1.1]], [[Advanced Vector Extensions 2|AVX2]], [[XOP instruction set|XOP]], [[FMA instruction set#FMA3 instruction set|FMA3]], [[FMA4 instruction set#FMA4 instruction set|FMA4]], [[F16C]], [[Bit Manipulation Instruction Sets#ABM (Advanced Bit Manipulation)|ABM]], [[Bit Manipulation Instruction Sets#BMI1 (Bit Manipulation Instruction Set 1)|BMI1]], [[Bit Manipulation Instruction Sets#BMI2|BMI2]], [[Bit Manipulation Instruction Sets#TBM (Trailing Bit Manipulation)|TBM]], [[RDRAND]], [[Turbo Core]]
* Dual-channel [[DDR4 SDRAM|DDR4]] memory controller
* [[PCI Express]] 3.0 x8 (No Bifurcation support, requires a PCI-e switch for any configuration other than x8)
* [[PCI Express]] 3.0 x4 as link to optional external chipset
* 4x [[USB 3.1]] Gen 1
* Storage: 2x [[SATA]] and 2x [[NVMe]] or 2x PCI Express

{| class="wikitable" style="text-align:center;"
! rowspan=3 | Model
! rowspan=3 | Released
! rowspan=3 | [[Stepping level|Stepping]]
! colspan=6 | CPU
! rowspan=3 | Memory support
! rowspan=3 | TDP
! rowspan=3 | Stock Cooler (box)
! rowspan=3 | Part number(s)
|-
! rowspan=2 | [Modules/[[Floating-point unit|FPUs]]]
[[Bulldozer (microarchitecture)#Bulldozer core|Cores]]/[[Thread (computing)|threads]]
! colspan=2 | Clock (GHz)
! colspan=3 | [[Cache memory|Cache]]
|-
! Base
! Turbo
! [[L1 cache|L1]]
! [[L2 cache|L2]]
! [[L3 cache|L3]]
|-
! style="text-align: left" | [https://www.amd.com/en/product/2081 Athlon X4 940]
| rowspan=3 | July 27, 2017
| rowspan=3 | BR-A1
| rowspan=3 | [2] 4
| 3.2
| 3.6
| rowspan=3 | 96 KB inst. per module 32 KB data per core
| rowspan=3 | 1 MB per module
| rowspan=3 {{n/a}}
| rowspan=3 | DDR4-2400 dual-channel
| rowspan=3 | 65 W
| rowspan=3 | Near-silent 65 W
| AD940XAGABBOX{{efn|name="box"|Boxed part with cooler.}} AD940XAGM44AB
|-
! style="text-align: left" | [https://www.amd.com/en/product/2076 Athlon X4 950]
| 3.5
| 3.8
| AD950XAGABBOX{{efn|name="box"}} AD950XAGM44AB
|-
! style="text-align: left" | [https://www.amd.com/en/product/2071 Athlon X4 970]
| 3.8
| 4.0
| AD970XAUABBOX{{efn|name="box"}} AD970XAUM44AB
|}
{{notelist}}

===Athlon (Zen-based) ===
===="Raven Ridge", 14 nm====
* [[Zen (microarchitecture)|Zen]] CPU cores
{{AMD Zen based Athlon desktop APUs}}

===="Picasso", 12 nm====
* [[Zen+]] CPU cores
{{AMD Zen+ based Athlon desktop APUs}}

==Mobile processors==
===Athlon XP===
{{Main|List of AMD Athlon XP processors#Mobile Processors}}

===Athlon 64===
{{Main|List of AMD Athlon 64 processors#Mobile processors}}

===Athlon II===
{{Main|List of AMD Athlon II processors#Mobile processors}}

===Athlon (Zen-based) ===
===="Raven Ridge" or "Picasso", 14/12 nm====
* [[Zen (microarchitecture)|Zen]] and Zen+ CPU cores
{{AMD Raven based Athlon mobile APUs}}

===="Dalí", 14 nm====
* [[Zen (microarchitecture)|Zen]] CPU cores
{{AMD Athlon Mobile 3000 series}}

===Athlon (Zen 2 based) ===
===="Mendocino", 6 nm====
{{AMD Athlon Mobile 7020 series}}

==See also==
* [[List of AMD processors]]
* [[List of AMD Duron processors]]
* [[List of AMD Athlon XP processors]]
* [[List of AMD Athlon 64 processors]]
* [[List of AMD Athlon X2 processors]]
* [[List of AMD Athlon II processors]]
* [[List of AMD Phenom processors]]
* [[List of AMD Opteron processors]]
* [[List of AMD Sempron processors]]
* [[List of AMD Ryzen processors]]
* [[List of Intel processors]]
* [[Table of AMD processors]]

==Notes==
<cite id="fn_1">[[#fn_1_back|Note 1:]]</cite>
Athlons use a [[double data rate]] (DDR) [[front-side bus]], (EV-6) meaning that the actual data transfer rate of the bus is twice its physical clock rate. The FSB's true data rate, 200 or 266 MT/s, is used in the tables, and the physical clock rates are 100 and 133 MHz, respectively. The multipliers in the tables above apply to the physical clock rate, not the data transfer rate.

==References==
{{reflist}}

==External links==
* [https://www.amd.com/us-en/Processors/TechnicalResources/0%2c%2c30_182_739_2983,00.html AMD technical documentation for Athlon]
* ''[https://www.amd.com/us-en/Corporate/VirtualPressRoom/0,,51_104_543_544~125306,00.html AMD Delivers Business-Ready Desktop Offerings to Solution Providers with AMD Business Class Initiative]'' AMD, 28 April 2008

{{AMD_processors}}

[[Category:AMD x86 microprocessors|*Athlon]]
[[Category:Lists of microprocessors|AMD Athlon]]

List of AMD Athlon processors - Revision history

imported>Blethering Scot: /* "Pure" CPUs */ RM Empty Section