View source for MOSIS

{{Short description|Semiconductor manufacturer}}
{{distinguish|Moses}}

'''MOSIS''' (Metal Oxide Semiconductor Implementation Service) is [[multi-project wafer service]] that provides [[metal–oxide–semiconductor]] (MOS) [[Integrated circuit|chip]] design tools and related services that enable universities, government agencies, research institutes and businesses to prototype chips efficiently and cost-effectively.

Operated by the [[Information Sciences Institute|University of Southern California's Information Sciences Institute (ISI)]], MOSIS combines customers' orders onto shared multi-project [[Wafer (electronics)|wafers]] that speed production and reduce costs compared with underutilized single-project wafers. Customers are able to debug and adjust designs, or to commission small-volume runs, without making major production investments. Fabrication costs are also shared by combining multiple designs from a single customer onto one "[[Photomask|mask]] set," or wafer template. According to MOSIS, by the end of 2016, the service had delivered more than 60,000 [[integrated circuit]] designs.<ref>{{Cite web|url=https://web.archive.org/web/20161202154206/https://www.mosis.com/what-is-mosis|title = What is MOSIS? | access-date=2025-09-16}}</ref>

Funded by DARPA,<ref>{{Cite web |title=The MOSIS Service of ISI and SkyWater Collaborate on Silicon IC Design Enablement and Manufacturing Service |url=https://viterbischool.usc.edu/news/2022/11/the-mosis-service-of-the-usc-information-sciences-institute-and-skywater-collaborate-on-silicon-ic-design-enablement-and-manufacturing-service/ |access-date=2024-05-30 |website=USC Viterbi {{!}} School of Engineering |language=en-US}}</ref> MOSIS was created in 1980<ref name="conway-rem">{{cite journal |last1=Conway |first1=Lynn |last2= |first2= |date=2012 |title=Reminiscences of the VLSI Revolution: How a Series of Failures Triggered a Paradigm Shift in Digital Design |url=https://ieeexplore.ieee.org/document/6393023 |journal=IEEE Solid-State Circuits Magazine |volume=4 |issue=4 |publisher=IEEE |pages=8-31 |doi=10.1109/MSSC.2012.2215752 |access-date=2025-09-12|url-access=subscription }}</ref> by ISI's [[Danny Cohen (engineer)|Danny Cohen]], an Internet pioneer who also developed [[Network Voice Protocol|Voice over Internet Protocol]] and Video over Internet Protocol.<ref>{{Cite magazine|url=https://www.wired.com/2012/11/he-engineered-the-internet-to-take-flight/|title=Danny Cohen Engineered the Internet to Take Flight|magazine=Wired}}</ref> It was based on the [[Mead-Conway VLSI chip design revolution|revolutionary VLSI design methodology]] of [[Carver Mead]] and [[Lynn Conway]], who pioneered and/or popularized the use of technology-independent design rules and modular cell-based, hierarchical system design, testing this new approach to rapid prototyping and short-run fabrication at [[PARC (company)|Xerox PARC]].<ref>{{cite web|title=Lynn's Story|url=http://ai.eecs.umich.edu/people/conway/LynnsStory.html|accessdate=2018-03-10}}</ref> One of the first e-commerce providers, MOSIS also launched the "fabless foundry" industry, in which vendors outsource [[integrated circuit|chip]] [[semiconductor device fabrication|fabrication]] rather than manufacturing them in-house.<ref>{{cite web |url=http://www.isi.edu/about/history/timeline/ |url-status=dead |archive-url=https://web.archive.org/web/20131126032923/http://www.isi.edu/about/history/timeline/ |archive-date=2013-11-26 |title=Information Sciences Institute - Timeline}}</ref> Thousands of students also have learned chip design in MOSIS-associate programs.<ref>{{cite web |url=http://viterbi.usc.edu/news/publications/uscengineer/2005_fall/mosis_turns_25.htm/ |url-status=dead |archive-url=https://web.archive.org/web/20060901114938/http://viterbi.usc.edu/news/publications/uscengineer/2005_fall/mosis_turns_25.htm |archive-date=2006-09-01 |title=USC Viterbi School of Engineering : MOSIS Turns 25}}</ref>

Many early MOSIS users were students trying IC layout techniques from the seminal book  ''Introduction to VLSI Design'' ({{ISBN|0-201-04358-0}}) published in 1980 by [[Caltech]] professor [[Carver Mead]]<ref>{{cite web|title=Winners' Circle: Carver Mead |date= |accessdate=2005-04-28 |url=http://web.mit.edu/invent/a-winners/a-mead.html |archive-url=https://web.archive.org/web/20140305150838/http://web.mit.edu/invent/a-winners/a-mead.html |archive-date=2014-03-05}}<!--dated 1996?--></ref> and PARC researcher [[Lynn Conway]], who taught the world's first VLSI class at MIT.<ref>{{cite web|title=M.I.T. VLSI Systems Design Class|accessdate=2018-03-10|url=http://ai.eecs.umich.edu/people/conway/VLSI/MIT78/MIT78.html}}</ref><ref>{{cite web|title=IEEE History Center - Lynn Conway |date=2003-01-02 |accessdate=2004-05-18 |url=http://www.ieee.org/organizations/history_center/conway.html |archive-url=https://web.archive.org/web/20060618183746/http://www.ieee.org/organizations/history_center/conway.html |archive-date=2006-06-18}}</ref> Some early [[reduced instruction set computing]] (RISC) processors such as [[MIPS Technologies|MIPS]] (1984) and [[SPARC]] (1987) were run through MOSIS during their early design and testing phases.

== MOSIS in the 1980s ==

After the transfer of Xerox PARC's multi-project wafer (MPW) technology to USC/ISI,<ref name="conway-rem" /> the MOSIS Project was created, and the first trial run conducted in August 1980:<ref name="isi-1981">{{cite tech report |last=Uncapher |first=Keith W. |date=August 1981 |title=1980 Annual Technical Report: A Research Program in Computer Technology, Volume 2 |url=https://apps.dtic.mil/sti/citations/ADA115584 |work= |location= |publisher=USC/ISI |id=ISI/SR-81-20 |access-date=2025-09-16}}
</ref>

{{quote|In August 1980 MOSIS accepted designs for the first fabrication run using the software developed for automatic interaction with users. This run had 65 projects submitted by designers from 8 organizations: ISI, UCLA, Caltech, Jet Propulsion Lab, Stanford University, National Bureau of Standards, Carnegie-Mellon University and Washington University at St. Louis. These projects were packed into 18 dies on the wafer.}}

The service became operational in January 1981, with 5-micron [[NMOS logic|nMOS]] as the first fabrication technology offered; designs were submitted in [[Caltech Intermediate Form]] via the ARPANET.<ref name="isi-1981"/> By 1983, more than forty organizations were using the service.<ref name="isi-1984">{{cite tech report |last=Uncapher |first=Keith W. |date=July 1984 |title=1983 Annual Technical Report: A Research Program in Computer Technology, Volume 2 |url=https://apps.dtic.mil/sti/citations/ADA145776 |work= |location= |publisher=USC/ISI |id=ISI/SR-84-138 |access-date=2025-09-16}}
</ref>  Chips were returned to designers approximately a month after the close of a fabrication run.

Over the course of the 1980s, more than 12,000 projects were fabricated through the MOSIS service.<ref name="darpa-1991">{{cite tech report |last1=Van Atta |first1=Richard H |last2=Reed |first2=Sidney G. |last3=Deitchman |first3=Seymour J. |date=March 1991 |title=DARPA Technical Accomplishments. Volume 2. An Historical Review of Selected DARPA Projects
 |url=https://apps.dtic.mil/sti/citations/ADA241725 |work= |location= |publisher=INSTITUTE FOR DEFENSE ANALYSES ALEXANDRIA VA |id= |access-date=2025-09-16}}
</ref> After the initial 5-micron, 1-metal layer nMOS service, new technologies were introduced, advancing to 1.2-micron, 2-metal layer [[CMOS]] by 1988. At the end of the 1980s, [[gallium arsenide]] (GaAs) fabrication service was added.<ref>{{cite conference |last1=Long |first1=Stephen I. |last2=Butner |first2=Steven E. |date=May 1990 |title=GaAs IC fabrication with MOSIS-a user's perspective |url=https://ieeexplore.ieee.org/document/112532 |book-title= |conference=IEEE International Symposium on Circuits and Systems |location=New Orleans |publisher=IEEE |pages= |doi=10.1109/ISCAS.1990.112532 |access-date=2025-09-17|url-access=subscription }}</ref> 
{| class="wikitable"
|+MOSIS Projects in 1980s <ref name="darpa-1991" />
! colspan="4" |Technology
!
!
!
!
!
!
!
!
!
|
|-
|
|Size (μm)
|Layers
|Type
|1981
|1982
|1983
|1984
|1985
|1986
|1987
|1988
|1989
|'''TOTALS'''
|-
|[[NMOS FET|NMOS]]
|5
|1M
|D {{refn|group=nb|name=first|Digital<ref name="darpa-1991"/>}}
|238
|441
|
|
|
|
|
|
|
|679
|-
|NMOS
|4
|1M
|D
|20
|283
|1199
|1035
|234
|18
|
|
|
|2789
|-
|NMOS
|3
|1M
|D
|
|63
|56
|162
|439
|309
|131
|20
|
|1180
|-
|[[CMOS]]
|5
|1M
|D
|
|22
|45
|
|
|
|
|
|
|67
|-
|CMOS
|3
|2M
|D
|
|
|
|
|949
|1113
|887
|710
|231
|3890
|-
|CMOS
|3
|1M
|A {{refn|group=nb|name=second|Analog<ref name="darpa-1991"/>}}
|
|
|22
|437
|106
|146
|83
|5
|
|799
|-
|[[Silicon on sapphire|CMOS-SOS]]
|4
|
|D
|
|
|
|
|62
|11
|
|
|
|73
|-
|CMOS
|2
|2M
|D
|
|
|
|
|
|71
|225
|396
|615
|1307
|-
|CMOS
|2
|2M
|A
|
|
|
|
|
|
|
|185
|934
|1119
|-
|CMOS
|1.6
|2M
|D
|
|
|
|
|
|15
|70
|86
|55
|226
|-
|CMOS
|1.2
|2M
|D
|
|
|
|
|
|
|
|27
|45
|72
|-
|'''TOTALS'''
|
|
|
|258
|809
|1332
|1634
|1790
|1683
|1396
|1429
|1880
|
|-
|'''GRAND TOTAL'''
|
|
|
|
|
|
|
|
|
|
|
|
|12,201
|}
== Notes ==
{{reflist|group=nb}}
== See also ==
* [[Mead and Conway revolution]]

== References ==
{{reflist}}

== External links ==
* [https://themosisservice.com/ MOSIS web site]
* [https://web.archive.org/web/20050216045436/http://www.foveon.com/about_executive.html foveon.com - Foveon - Executive Profiles] (archived from 2005)
* [https://arxiv.org/abs/2311.02055 NSF Integrated Circuit Research, Education and Workforce Development Workshop Final Report]

[[Category:Integrated circuits]]
[[Category:Semiconductor device fabrication]]